JPH1167764A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent formation of a SOG film remaining on lower-layer interconnections by electrically connecting a plurality of interconnections via a conductive member formed on the lower portion of the interconnections through an insulating film. SOLUTION: A lower-layer interconnection is divided to be separated at a predetermined distance. A second lower-layer interconnection 6, which is in the same layer as a first lower-layer interconnection 5, is formed in a space that separates the interconnection 5 with an end portion of the interconnection 6 facing such space. That is, the interconnection 5 facing the end portion of the interconnection 6 is removed by cutting. A contact hole 4 is formed in a first inter-layer insulating film to connect the interconnection 5 to a conductive member 3. The interconnection 5 is located on the outermost side of a semiconductor chip and is in the same layer as the interconnection 6. Here, the interconnection 5 is electrically connected to a scribe region 2. The end portion of the interconnection 6 is formed so as to face the space, and a through hole for connecting an upperlayer interconnection is formed in the end portion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a multilayer wiring provided around a semiconductor chip.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements, the use of fine multilayer wiring is indispensable for forming semiconductor devices. For the purpose of reducing the parasitic capacitance between the upper wiring layer and the lower wiring layer and between the wiring layers of the same layer, the interlayer insulating film of the semiconductor device having such multilayer wiring has a small dielectric constant and stable quality. Insulating films based on silicon oxide films have become mainstream.

With the miniaturization of the semiconductor element, the line width and the wiring interval of the lower wiring layer are reduced. In order to avoid an increase in the resistance of the fine wiring, it is necessary to secure a certain cross-sectional area of the wiring layer. As a result, the aspect ratio between wirings (height of wiring layer / interval between wiring layers) increases as well as the aspect ratio of the wiring layer (height of wiring layer / line width of wiring layer). Then, it is required that an interlayer insulating film is filled between the wirings of the lower wiring layer and the surface thereof is flattened. In the case of an interlayer insulating film on an aluminum-based metal wiring, the temperature for forming the interlayer insulating film is required to be 450 ° C. or less.

An SOG (spin-on-glass) film is generally used as a method of forming an interlayer insulating film for such a fine multilayer wiring of an aluminum-based metal. However, with such an SOG film, it is difficult to evenly planarize the entire semiconductor chip. In particular, if there is a lower wiring layer having a large line width around the semiconductor chip, S
The OG film is formed thick around the semiconductor chip.

Hereinafter, this situation will be described with reference to FIG. FIG. 4 is a plan view and a sectional view of a lower wiring layer and an upper wiring layer around a semiconductor chip. Here, FIG.
FIG. 4B shows a cross section taken along the line EF shown in FIG.

[0006] As shown in FIGS. 4A and 4B, a scribe region 102 is formed on a silicon substrate 101 having a P-type conductivity. Here, the scribe region 102 is formed of a P-type diffusion layer. And
A field oxide film 103 is formed on the silicon substrate 101 other than the scribe region 102. Further, a first interlayer insulating film 104 is formed on the field oxide film 103 by a chemical vapor deposition (CVD) method. This first interlayer insulating film 104 is a silicon oxide film.

Then, as shown in FIGS. 4A and 4B, a lower wiring 10 is formed on the first interlayer insulating film 104.
5, 105a are formed. Here, the lower wiring 10
5 is electrically connected to the scribe area 102. The lower layer wiring 105 is formed of aluminum or tungsten metal, and prevents the generation of channel leakage current under the field oxide film 103 around the semiconductor chip, or the power supply of a substrate potential generating circuit in a semiconductor device such as a DRAM. Wire or ESD (Electro
It is also used as a discharge wire for Static Discharge. The line width of the lower wiring 105 is as large as about 15 μm.

Similarly, lower wiring 105a made of aluminum or tungsten metal is used as a power supply line, a GND line or a signal line. In this drawing, a power supply line or a GND line having a large line width, for example, about 10 μm is shown.

[0009] Then, a second interlayer insulating film 106 is formed so as to cover these lower wiring layers. This second interlayer insulating film 106 has a thickness of 3 deposited by a plasma CVD method.
It is a silicon oxide film of about 00 nm. On the second interlayer insulating film 106, an SOG film is formed as a planarizing material. The SOG film is formed by spin-coating an SOG coating solution on the second interlayer insulating film 106, thermally curing by heat treatment, and etching back by dry etching. Then, the inside of the semiconductor chip is completely flattened (not shown). Here, such SO
The G film is an inorganic silica or organic silica film.

However, when the SOG film is formed in this manner, the thickness of the SOG film is greatly different between the inside of the semiconductor chip and the end. This is the lower layer wiring 1 at the end of the semiconductor chip.
This is because the SOG film tends to remain between the layers 05 and 105a. Then, the remaining SOG film 107 is formed. This becomes more remarkable as the wiring width of the lower wirings 105 and 105a provided at the end of the semiconductor chip increases.

Then, a third interlayer insulating film 108 is formed by a plasma CVD method. This third interlayer insulating film 108 is a silicon oxide film having a thickness of about 400 nm. Here, at the end of the semiconductor chip, a third interlayer insulating film / SOG film / second interlayer insulating film is laminated on the lower wirings 105 and 105a.

Then, through holes 109 and 109a are formed in the interlayer insulating film on which the second interlayer insulating film 106 and the third interlayer insulating film 108 are laminated on the lower wiring 105a. Further, through the through hole 109, the lower wiring 10
Upper wiring 110 connected to 5a, through hole 109
upper wiring 11 connected to lower wiring 105a through a
0 are respectively formed. On the lower wiring 105a, an upper wiring 111 is formed via a second interlayer insulating film 106 and a third interlayer insulating film 108. Then, a cover film 112 is formed so as to cover the entire semiconductor chip.

[0013]

However, in the above-described conventional technique, the SOG film around the semiconductor chip, that is, the SOG film at the end of the semiconductor chip is formed to be thicker than that inside the semiconductor chip.

[0014] For this reason, the following two major problems arise. That is, first, the upper wiring is corroded at the connection between the lower wiring and the upper wiring at the end of the semiconductor chip,
This means that the electrical connection between the lower wiring and the upper wiring deteriorates. For this reason, the reliability of the semiconductor device is greatly reduced.

[0015] Such deterioration of the electrical connection occurs as follows. As described above, at the end of the semiconductor chip,
The remaining SOG film 107 is formed on the lower wiring having a large wiring width. For this purpose, SO
The G film is exposed. The SOG film has high hygroscopicity and easily contains moisture. The moisture in the SOG film corrodes the upper layer wiring at the through hole 109 and causes disconnection of the wiring or an increase in resistance.

Second, similarly, electrical connection becomes difficult in connection between the lower wiring and the upper wiring at the end of the semiconductor chip. This is because the SOG film similarly remains on the lower layer wiring at the end of the semiconductor chip, so that the through hole 109 becomes deeper and the through hole 109 may not reach the surface of the lower layer wiring 105a. Here, if the amount of etch back is increased to remove the remaining SOG film 107, the above-described SOG film inside the semiconductor chip is also removed and does not function as a planarizing material.

An object of the present invention is to provide a semiconductor device which prevents the formation of the residual SOG film 107 on the lower layer wiring at the end of the semiconductor chip as described above, and has a high reliability and a high yield. Is to do.

[0018]

For this purpose, in the semiconductor device according to the present invention, the first lower wiring located at the outermost side of the semiconductor chip and disposed along the scribe region is cut off so that a certain separation distance is obtained. The plurality of divided wirings are electrically connected to each other through a conductive material formed below the wirings via an insulating film.

Alternatively, a second lower layer wiring is provided in the same layer as the first lower layer wiring, and an end of the second lower layer wiring faces a divided region of the divided first lower layer wiring. A through hole is provided in the interlayer insulating film on the second lower layer wiring and located in the vicinity of the end portion, and the upper layer is connected to the second lower layer wiring through the through hole. Wiring is formed.

Here, the first lower wiring is connected to the semiconductor substrate in the scribe region. Further, a dummy pattern is formed below the conductor material via an insulating film.

A spin-on glass is formed inside the semiconductor chip and between lower wirings formed on the same layer as the first lower wiring or on the lower wiring.

If the multilayer wiring in the peripheral portion of the semiconductor chip has the structure according to the present invention, the SOG is formed on the lower wiring of the semiconductor device.
In the step of forming the film, the SOG film is not formed in unnecessary regions around the semiconductor chip. This is because, since the first lower wiring is divided, the coating solution flows through the divided region during the spin coating of the SOG coating solution, and the SOG coating solution does not accumulate in this region.
This is because the remaining amount of the G film is reduced.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a lower wiring layer and an upper wiring layer around a semiconductor chip.
FIG. 2 is a sectional view of a lower wiring layer and an upper wiring layer around the semiconductor chip. Here, AB shown in FIG.
FIG. 2A shows a portion cut along the line, and FIG. 2B shows a portion cut along the line CD. In FIG. 1, the lower wiring layer is hatched.

As shown in FIG. 1, for example, a scribe region 2 is formed on a silicon substrate 1 having a P-type conductivity. Here, the scribe region 2 is formed of a diffusion layer having a P-type conductivity. Then, the conductor material 3 is provided via an insulating film described later, and a first lower wiring 5 electrically connected to the conductor material 3 through a contact hole 4 formed in the interlayer insulating film is formed. As described above, according to the present invention, the lower wiring 105 described in the related art is divided and separated at a fixed distance (hereinafter, referred to as a space).

As shown in FIG. 1, a wiring in the same layer as the first lower wiring 5, that is, a second lower wiring 6, is formed in the divided space of the first lower wiring 5, and the second lower wiring 5 is formed. 6 are formed so as to face the space area. That is, the first lower-layer wiring facing the end of the second lower-layer wiring 6 is divided and removed.

Then, upper wirings 8 and 8a are formed which are electrically connected to the second lower wiring 6 through through holes 7 provided in the interlayer insulating film on the second lower wiring. An upper wiring 9 is provided on the second lower wiring 6 via an interlayer insulating film.

Next, the present invention will be described with reference to FIG. As shown in FIGS. 2A and 2B, a scribe region 2 is formed on a silicon substrate 1 having a P-type conductivity. Then, the field oxide film 10 is
Other than the silicon substrate 1. Further, a lower insulating film 11 is formed on the field oxide film 10 by a CVD method, and a patterned conductor material 3 is provided in a predetermined region on the lower insulating film 11. Here, the conductor material 3
Is made of a high melting point metal film such as tungsten, and its thickness is set to about 200 nm. Then, a first interlayer insulating film 12 covering the conductor material 3 is formed. The first interlayer insulating film 12 is a silicon oxide film,
The thickness is about 500 nm.

Then, as shown in FIG. 2A, the second region is formed on the first interlayer insulating film 12 in the space region described with reference to FIG.
The lower wiring 6 is formed. Here, the second lower wiring 6
Is made of a 500-nm-thick aluminum metal. The second lower wiring 6 is used as a power supply line, a GND line, or a signal line of the semiconductor device. Then, a second interlayer insulating film 13 is formed so as to cover the second lower wiring 6.
The second interlayer insulating film 13 is a silicon oxide film having a thickness of about 200 nm deposited by a plasma CVD method. Then, as described in the related art, an SOG film is formed on the second interlayer insulating film 13 as a planarizing material.

After the step of forming the SOG film, the remaining SOG
Only the film 14 is formed in the space region described above. The residual SOG film is not formed in the region located on the second lower wiring 6 as described in the related art. This is because the end of the second lower wiring 6 faces the space area, and the coating solution does not accumulate during the spin coating of the SOG coating solution unlike the related art, and the remaining SOG film does not remain. This is because the amount is reduced. Then, a third interlayer insulating film 15 is formed by a plasma CVD method. The third interlayer insulating film 15 is a silicon oxide film having a thickness of about 400 nm. Here, the third interlayer insulating film / the second interlayer insulating film is laminated on the second lower wiring 6.

Then, a through-hole 7 is formed in an end portion on the second lower layer wiring 6 and in the inter-layer insulating film in which the second inter-layer insulating film 13 and the third inter-layer insulating film 15 are laminated. Further, upper layer wirings 8 and 8a connected to the second lower layer wiring 6 through the through holes 7 are respectively formed. The second interlayer insulating film 13 and the third interlayer insulating film 15 are formed on the second lower wiring 6.
, An upper wiring 111 is provided. Then, a cover film 16 is formed so as to cover the entire semiconductor chip.

As shown in FIG. 2B, a contact hole 4 is formed in the first interlayer insulating film 12, and the first lower wiring 5 is connected to the conductor 3. This first lower layer wiring 5
Is disposed so as to be located on the outermost side of the semiconductor chip,
The wiring is in the same layer as the second lower wiring 6. Here, the first lower layer wiring 5 is electrically connected to the scribe region 2.

The first lower wiring 5 is used as a power supply line of a substrate potential generating circuit in a semiconductor device such as a DRAM or a discharge line for ESD as described in the related art.

Then, a second interlayer insulating film 13 covering the first lower wiring 5 is formed, and an SOG film is formed on the second interlayer insulating film 13 as a planarizing material. In the step of forming the SOG film, the remaining SOG film 14a is formed on the semiconductor chip center side of the first lower layer wiring 5 pattern.

Then, the third interlayer insulating film 15 is laminated, and the upper wirings 8 a and 9 are provided on the third interlayer insulating film 15.

As described above, according to the present invention, the wiring provided along the scribe area on the outermost side of the semiconductor chip is divided into predetermined areas and separated by a predetermined space. The wiring of the same layer as the first lower wiring 5, that is, the second lower wiring 6 is formed so that its end faces the space region, and a through hole for connecting to the upper wiring is provided on this end. .

Due to such a structure, a residual SOG film is never formed in the through-hole portion, and the problem caused by the conventional technique can be completely solved.

Next, a second embodiment of the present invention will be described with reference to FIG. Here, FIG. 3 is a cross-sectional view of a lower wiring layer and an upper wiring layer around the semiconductor chip, and FIG. 3A is a cross-sectional view taken along a line AB shown in FIG.
FIG. 3 shows a cut at a position corresponding to CD.
(B).

In the following description, the same components as those described in FIG. 1 or FIG. 2 are denoted by the same reference numerals. The description of the same structure as that of FIG. 2 is omitted.

As shown in FIGS. 3A and 3B, a scribe region 2 is formed on a silicon substrate 1. Then, a field oxide film 10 is formed on the silicon substrate 1 other than the scribe region 2.

A dummy pattern 17 is provided on the field oxide film 10. Here, the dummy pattern 17 is made of tungsten polycide having a thickness of about 300 nm. For example, it is formed in the same layer as the gate electrode of the MOS transistor, and is formed in the same pattern shape as the conductor material 3 as shown in FIG.

Then, the lower insulating film 11 is formed so as to cover the dummy pattern 17 by the CVD method. Thereafter, the first lower wiring 5, the second lower wiring 6, the upper wirings 8, 8a, 9 and the like are respectively provided in the same manner as described with reference to FIG.

In this case, the same effect as described in the first embodiment is produced. In the second embodiment, since the dummy pattern 17 is formed, a space region protrudes. For this reason, the remaining SOG in the SOG film formation
The thickness of the films 14 and 14a is further reduced, and the yield in the semiconductor device manufacturing process is improved.

[0043]

As described above, according to the present invention, the first lower wiring located at the outermost side of the semiconductor chip and disposed along the scribe region is divided and divided into a plurality of wirings. The plurality of divided wirings are electrically connected through a conductor material formed below the wirings via an insulating film.
Further, a second lower-layer wiring is provided on the same layer as the first lower-layer wiring, and an end of the second lower-layer wiring is formed facing the above-mentioned divided region of the first lower-layer wiring. A through hole is provided near the end and connected to the upper wiring. Further, a dummy pattern is formed below the conductor material via an insulating film. Then, a spin-on-on is performed between lower wirings or on the lower wiring formed in the same layer as the first lower wiring inside the semiconductor chip.
Glass is formed.

For this reason, a problem as occurred in the prior art, that is, the upper wiring is corroded at the connection between the lower wiring and the upper wiring at the end of the semiconductor chip, and the electrical connection between the lower wiring and the upper wiring is caused. There is no problem of the deterioration. For this reason, the reliability of the semiconductor device is greatly improved.

Similarly, in the connection between the lower wiring and the upper wiring at the end of the semiconductor chip, the difficulty of electrical connection is completely eliminated, and the yield in the manufacture of semiconductor devices is greatly improved.

As described above, the semiconductor device of the present invention has high reliability and high yield.

[Brief description of the drawings]

FIG. 1 is a plan view of the periphery of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the periphery of a semiconductor chip for explaining the first embodiment of the present invention.

FIG. 3 is a sectional view around a semiconductor chip for explaining a second embodiment of the present invention;

FIG. 4 is a plan view and a cross-sectional view around a semiconductor chip for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 Silicon substrate 2,102 Scribe area 3 Conductor material 4 Contact hole 5 1st lower layer wiring 6 2nd lower layer wiring 7,109,109a Through hole 8,8a, 9,110,110a, 111 Upper layer wiring 10,103 Field oxide film 11 Lower insulating film 12, 104 First interlayer insulating film 13, 106 Second interlayer insulating film 14, 14a, 107 Remaining SOG film 15, 108 Third interlayer insulating film 16, 112 Cover film 17 Dummy pattern

Claims (5)

[Claims] 1. A first lower-layer wiring, which is located along the scribe region and is located at the outermost part of a semiconductor chip, is divided into a plurality of wirings having a predetermined separation distance, and is divided into a plurality of wirings. A semiconductor device, wherein a wiring is electrically connected through a conductor material formed below the wiring via an insulating film. 2. A second lower layer wiring is provided in the same layer as the first lower layer wiring, and an end of the second lower layer wiring faces a divided region of the divided first lower layer wiring. A through hole is provided in the interlayer insulating film on the second lower layer wiring and located in the vicinity of the end portion, and the upper layer is connected to the second lower layer wiring through the through hole. The conductor device according to claim 1, wherein a wiring is formed. 3. The semiconductor device according to claim 1, wherein said first lower wiring is connected to a semiconductor substrate in said scribe region. 4. The semiconductor device according to claim 1, wherein a dummy pattern is formed below the conductor material via an insulating film. 5. A spin-on glass is formed inside the semiconductor chip and between lower wirings formed on the same layer as the first lower wiring or on the lower wiring. The semiconductor device according to any one of claims 1 to 4.