JPH0794481A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0794481A
JPH0794481A JP5238103A JP23810393A JPH0794481A JP H0794481 A JPH0794481 A JP H0794481A JP 5238103 A JP5238103 A JP 5238103A JP 23810393 A JP23810393 A JP 23810393A JP H0794481 A JPH0794481 A JP H0794481A
Authority
JP
Japan
Prior art keywords
opening
film
polyimide film
photoresist mask
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5238103A
Other languages
Japanese (ja)
Inventor
Masaharu Kondo
雅陽 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP5238103A priority Critical patent/JPH0794481A/en
Publication of JPH0794481A publication Critical patent/JPH0794481A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device by which step disconnection of a second layer wiring is reliably prevented by a slight change of the process. CONSTITUTION:A photoresist mask 5 having an opening pattern 6 is provided on an intermediate insulating film composed of a protective film 3 and a polyimid film 4 formed in multilayer from the side of a semiconductor substrate 1 for forming an opening 7 in the polyimide film 4 by etching and an opening 8 is formed in the protective film 3 by etching having the photoresist mask 5 and the polyimide film 4 as masks and the polyimide film 4 is again selectively etched using the photoresist mask 5. Then, the opening 7 of the polyimide film 4 is enlarged relative to the opening 8 of the protective film 3, and an opening to be formed getting together these openings is made into an upwardly opened shape and after removing the photoresist mask 5, a wiring 9 for plating connected to an ohmic electrode 2 provided on the polyimide film 4 is provided in order to reliably prevent step disconnection of the wiring 9 for plating on the way to the opening.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に、中間絶縁膜を介して多層配線を形成する方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a multi-layer wiring via an intermediate insulating film.

【0002】[0002]

【従来の技術】高周波領域で高効率な性能を発揮するガ
リウム砒素電界効果トランジスタ装置は、複数のトラン
ジスタ素子を並列接続した構造となっている。このた
め、トランジスタ素子の上に設けられた中間絶縁膜にエ
ッチングにより開口を設け、中間絶縁膜上に設けた配線
をこの開口を介してトランジスタ素子の電極に接続する
2層配線構造を形成する必要がある。
2. Description of the Related Art A gallium arsenide field effect transistor device which exhibits highly efficient performance in a high frequency region has a structure in which a plurality of transistor elements are connected in parallel. Therefore, it is necessary to form a two-layer wiring structure in which an opening is formed in the intermediate insulating film provided on the transistor element by etching and the wiring provided on the intermediate insulating film is connected to the electrode of the transistor element through this opening. There is.

【0003】2層配線構造を形成するための従来の方法
を図3乃至図6を参照して説明する。図3に示すよう
に、ガリウム砒素基板1には予めトランジスタ素子が形
成され、ソース或いはドレイン領域にオーミック接触す
るオーミック電極2が設けられている。そして、このガ
リウム砒素基板1上には順次、シリコン窒化膜(SiN
膜)3、ポリイミド膜4が設けられ、これらの膜3、4
で層間絶縁のための中間絶縁膜が構成されている。
A conventional method for forming a two-layer wiring structure will be described with reference to FIGS. As shown in FIG. 3, a gallium arsenide substrate 1 is preliminarily formed with a transistor element, and is provided with an ohmic electrode 2 which makes ohmic contact with a source or drain region. Then, on the gallium arsenide substrate 1, a silicon nitride film (SiN
3) and a polyimide film 4 are provided, and these films 3, 4 are provided.
The intermediate insulating film for interlayer insulation is constituted by.

【0004】上記のような中間絶縁膜まで設けられた状
態において、まず、中間絶縁膜上にはフォトレジスト膜
5を設け、このフォトレジスト膜5にオーミック電極2
に対応した開口6のパターンを形成する。
In the state where the intermediate insulating film is provided as described above, first, the photoresist film 5 is provided on the intermediate insulating film, and the ohmic electrode 2 is formed on the photoresist film 5.
To form a pattern of the openings 6.

【0005】次いで、図4に示すように、フォトレジス
ト膜5をマスクとして、ポリイミド膜4をシリコン窒化
膜3が露出するまで選択的にウエットエッチングし、フ
ォトレジスト膜5の開口6に連続した開口7を形成す
る。このウエットエッチングは、ポリイミド膜4の膜厚
が1μmの場合に、例えばエチレンジアミン;ヒドラジ
ンヒドラードを用いて約2分間行う。
Next, as shown in FIG. 4, the polyimide film 4 is selectively wet-etched using the photoresist film 5 as a mask until the silicon nitride film 3 is exposed, and an opening continuous to the opening 6 of the photoresist film 5. Form 7. This wet etching is performed for about 2 minutes by using, for example, ethylenediamine; hydrazine hydride when the thickness of the polyimide film 4 is 1 μm.

【0006】なお、このウエットエッチングにおいて、
ポリイミド膜4は若干サイドエッチングされ、開口7は
開口6より若干大きくなる。
In this wet etching,
The polyimide film 4 is slightly side-etched so that the opening 7 becomes slightly larger than the opening 6.

【0007】次いで、図5に示すように、フォトレジス
ト膜5及びポリイミド膜4をマスクとして、シリコン窒
化膜3をオーミック電極2が露出するまで選択的にドラ
イエッチングし、シリコン窒化膜3に開口6、7に連続
した開口8を形成する。このドライエッチングは、シリ
コン窒化膜3の膜厚が数千オングストロームの場合に、
ガスプラズマを用いて約30秒間行う。
Next, as shown in FIG. 5, the silicon nitride film 3 is selectively dry-etched until the ohmic electrode 2 is exposed by using the photoresist film 5 and the polyimide film 4 as a mask, and an opening 6 is formed in the silicon nitride film 3. , 7 to form a continuous opening 8. This dry etching is performed when the silicon nitride film 3 has a thickness of several thousand angstroms.
Perform for about 30 seconds using gas plasma.

【0008】なお、このドライエッチングにおいて、シ
リコン窒化膜3は若干サイドエッチングされ、開口8は
開口7より若干大きくなる。
In this dry etching, the silicon nitride film 3 is side-etched slightly and the opening 8 becomes slightly larger than the opening 7.

【0009】次いで、フォトレジスト膜5を除去し、ポ
リイミド膜4及び開口7の部分の全面に、金属(例え
ば、チタン、白金、金)を蒸着し、この金属の上に新た
なフォトレジスト膜を用いてマスクパターンを形成し、
電解メッキを行うことにより、2層目の配線9を形成す
る。
Next, the photoresist film 5 is removed, a metal (for example, titanium, platinum, gold) is vapor-deposited on the entire surface of the polyimide film 4 and the opening 7, and a new photoresist film is formed on this metal. Form a mask pattern using
By performing electrolytic plating, the second layer wiring 9 is formed.

【0010】[0010]

【発明が解決しようとする課題】上記に説明したよう
に、ポリイミド膜4及びシリコン窒化膜3を順次エッチ
ングして開口7及び開口8を形成すると、サイドエッチ
ングも生じて開口が順次大きくなり、これら開口7、8
によって形成される開口は下方に向かって(すなわち、
オーミック電極2に向かって)開いた段差形状となって
しまう。
As described above, when the polyimide film 4 and the silicon nitride film 3 are sequentially etched to form the opening 7 and the opening 8, side etching also occurs, and the opening becomes larger. Openings 7, 8
The opening formed by is downward (ie,
This results in an open step shape (toward the ohmic electrode 2).

【0011】しかしながら、図6に示すように従来の製
造方法にあっては、開口の形状が上記のような下方に向
かって開いた段差を有するものであるにもかかわらず、
そのまま金属を蒸着して2層目のメッキ用電極9を形成
するようにしていたため、上記開口の段差部分で蒸着し
た金属が切れ、メッキ用電極9が断線してしまうという
ステップ断線が生じてしまう場合があった。
However, in the conventional manufacturing method as shown in FIG. 6, although the shape of the opening has the above-described step opening downward,
Since the metal is vapor-deposited as it is to form the plating electrode 9 of the second layer, the vapor-deposited metal is cut off at the step portion of the opening, and the plating electrode 9 is disconnected, resulting in a step disconnection. There were cases.

【0012】本発明は上記従来の事情に鑑み為されたも
ので、工程のわずかな変更で上記のようなステップ断線
を確実に防止することができる半導体装置の製造方法を
提供することを目的とする。
The present invention has been made in view of the above conventional circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of reliably preventing the above-mentioned step disconnection with a slight change in the process. To do.

【0013】[0013]

【課題を解決するための手段】上記目的を達成する本発
明の半導体装置の製造方法は、電極が設けられた半導体
基板上に、半導体基板側から保護膜、ポリイミド膜を層
状に重ねて成る中間絶縁膜を設け、この中間絶縁膜に開
口を形成して配線を接続する半導体装置の製造方法にお
いて、中間絶縁膜上に開口パターンを有するフォトレジ
ストマスクを設けてエッチングによりポリイミド膜に開
口を形成する工程と、前記フォトレジストマスク及びポ
リイミド膜をマスクとしてエッチングにより保護膜に開
口を形成する工程と、前記フォトレジストマスクを利用
して再びポリイミド膜を選択的にエッチングし、保護膜
の開口縁部に対してポリイミド膜の開口縁部を側方へ後
退させる工程と、前記フォトレジストマスクを除去した
後に中間絶縁膜上に前記電極に接続したメッキ用電極を
設ける工程と、を備えたことを特徴とする。
A method of manufacturing a semiconductor device according to the present invention which achieves the above object, comprises an intermediate layer formed by stacking a protective film and a polyimide film in layers from the semiconductor substrate side on a semiconductor substrate provided with electrodes. In a method of manufacturing a semiconductor device in which an insulating film is provided and an opening is formed in the intermediate insulating film to connect wiring, a photoresist mask having an opening pattern is provided on the intermediate insulating film and an opening is formed in a polyimide film by etching. A step of forming an opening in the protective film by etching using the photoresist mask and the polyimide film as a mask; and selectively etching the polyimide film again using the photoresist mask to form an opening edge portion of the protective film. On the other hand, a step of retreating the opening edge of the polyimide film to the side, and after removing the photoresist mask, on the intermediate insulating film Characterized by comprising the the steps of providing a plating electrode connected to the electrode.

【0014】[0014]

【作用】従来例と同様に中間絶縁膜をエッチングして、
中間絶縁膜のポリイミド膜及び保護膜に順次開口を形成
する。そして、本発明では、2層目のメッキ用電極を形
成する前に、これら開口のエッチング形成に用いたフォ
トレジスト膜を再びマスクとして利用してポリイミド膜
のみを選択的にエッチングし、ポリイミド膜の開口を保
護膜の開口より大きくして、これら開口をまとめて形成
される開口を上方へ向かって開いた形状にする。そし
て、従来例と同様に、フォトレジスト膜を除去した後、
開口を介して半導体基板上の電極に接続した2層目のメ
ッキ用電極を中間絶縁膜上に形成する。
[Function] The intermediate insulating film is etched as in the conventional example,
Openings are sequentially formed in the polyimide film and the protective film of the intermediate insulating film. Then, in the present invention, before forming the second-layer plating electrode, only the polyimide film is selectively etched using the photoresist film used for etching formation of these openings again as a mask, The openings are made larger than the openings of the protective film, and the openings formed by combining these openings are shaped to open upward. Then, as in the conventional example, after removing the photoresist film,
A second-layer plating electrode connected to the electrode on the semiconductor substrate through the opening is formed on the intermediate insulating film.

【0015】[0015]

【実施例】以下、本発明の一実施例を図1及び図2に基
づいて説明する。なお、従来と同一の工程については説
明を省略し、符号も従来と同一部分には同一の符号を付
して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The description of the same steps as those in the related art will be omitted, and the same reference numerals will be given to the same portions as those in the related art.

【0016】本実施例は、上記した従来の製造方法によ
って対象の半導体装置を図5に示した状態とした後に、
工程を1つ追加したものである。すなわち、図5に示し
たようにポリイミド膜4及びシリコン窒化膜3をそれぞ
れ選択的にエッチングして開口7及び開口8を形成した
後、2層目のメッキ用電極を形成するための金属蒸着を
行う前に、ポリイミド膜4の選択的エッチングを再び行
う。
In this embodiment, after the target semiconductor device is brought into the state shown in FIG. 5 by the above-mentioned conventional manufacturing method,
It has one additional process. That is, as shown in FIG. 5, the polyimide film 4 and the silicon nitride film 3 are selectively etched to form the openings 7 and 8, and then metal deposition for forming a second-layer plating electrode is performed. Prior to this, selective etching of the polyimide film 4 is performed again.

【0017】このポリイミド膜4の再度のエッチング
は、図1に示すように、先に開口7及び開口8のエッチ
ング形成に用いたフォトレジスト膜5をそのまま再びマ
スクとして利用して行い、ポリイミド膜4のみを選択的
にウエットエッチングする。このウエットエッチング
は、ポリイミド膜4の膜厚が1μmの場合に、例えばエ
チレンジアミン;ヒドラジンヒドラード混合液を用いて
約90秒間(図2に示した工程の約3/4)行う。
The polyimide film 4 is again etched by using the photoresist film 5 previously used for etching the openings 7 and 8 as a mask as it is, as shown in FIG. Only the wet etching is selectively performed. This wet etching is performed for about 90 seconds (about 3/4 of the step shown in FIG. 2) using, for example, a mixed solution of ethylenediamine and hydrazine hydride when the thickness of the polyimide film 4 is 1 μm.

【0018】この結果、ポリイミド膜4の開口7の壁面
がサイドエッチングされ、開口7がシリコン窒化膜3の
開口8より大きくなる。したがって、これら開口7及び
開口8を総じて形成される開口は上方へ向かって開いた
形状になる。
As a result, the wall surface of the opening 7 of the polyimide film 4 is side-etched, and the opening 7 becomes larger than the opening 8 of the silicon nitride film 3. Therefore, the opening formed as a whole of the opening 7 and the opening 8 has a shape that opens upward.

【0019】この後、従来と同様にして、フォトレジス
ト膜5を除去した後、ポリイミド膜4及び開口7の部分
の全面に、チタン、白金、金等の金属を蒸着し、この金
属の上に新たなフォトレジスト膜を用いてマスクパター
ンを形成し、開口7及び開口8を介してガリウム砒素基
板1上のオーミック電極2に接続した2層目のメッキ用
電極9をポリイミド膜4上に形成する。
After that, the photoresist film 5 is removed in the same manner as in the prior art, and then a metal such as titanium, platinum or gold is vapor-deposited on the entire surface of the polyimide film 4 and the opening 7, and the metal is deposited on the metal. A mask pattern is formed using a new photoresist film, and a second-layer plating electrode 9 connected to the ohmic electrode 2 on the gallium arsenide substrate 1 through the openings 7 and 8 is formed on the polyimide film 4. .

【0020】ここで、図2に示すように、中間絶縁膜に
形成された開口は上方に向かって開いた段差形状となっ
ていることから、メッキ用電極9の形成のための金属は
ポリイミド膜4上からオーミック電極2上へなだらかに
蒸着されるため、この開口の段差部分で蒸着した金属が
切れてしまうことはなく、メッキ用電極9がステップ断
線してしまうことはない。そして、メッキ用電極9の上
にオーミック電極2の上に開口部を有するレジストパタ
ーンを形成し、メッキ用電極9を一方の電極として電流
を流す電解メッキ法により、メッキ用電極9の上に選択
的に導電金属を被着することでソースドレイン電極を形
成するものである。
Here, as shown in FIG. 2, since the opening formed in the intermediate insulating film has a step shape that opens upward, the metal for forming the plating electrode 9 is a polyimide film. Since the metal 4 is gently vapor-deposited on the ohmic electrode 2, the vapor-deposited metal will not be cut at the step portion of the opening, and the plating electrode 9 will not be step-broken. Then, a resist pattern having an opening is formed on the ohmic electrode 2 on the plating electrode 9 and selected on the plating electrode 9 by an electrolytic plating method in which a current is applied with the plating electrode 9 as one electrode. The source / drain electrodes are formed by selectively depositing a conductive metal.

【0021】なお、上記実施例ではガリウム砒素基板を
用いた半導体装置を例にとって説明したが、本発明はこ
れに限定されるのもではなく、他の種類の化合物半導体
基板やシリコン半導体基板など、種々の半導体基板を用
いた半導体装置に適用することができる。例えばシリコ
ン半導体装置の多層配線構造に適用するには、図2の工
程においてメッキ用電極9の代わりに2層目配線層用の
導電金属層を堆積し、該導電金属層をフォトエッチング
にてパターニングすることにより、2層目の配線層を形
成する。
In the above embodiments, the semiconductor device using the gallium arsenide substrate has been described as an example, but the present invention is not limited to this, and other types of compound semiconductor substrates, silicon semiconductor substrates, etc. It can be applied to semiconductor devices using various semiconductor substrates. For example, to apply to a multilayer wiring structure of a silicon semiconductor device, a conductive metal layer for the second wiring layer is deposited instead of the plating electrode 9 in the process of FIG. 2 and the conductive metal layer is patterned by photoetching. By doing so, the second wiring layer is formed.

【0022】また、上記実施例では保護膜としてシリコ
ン窒化膜を用いた例を説明したが、本発明はこれに限定
されるものではなく、シリコン酸化膜(SiO2)を保
護膜として用いた半導体装置にも適用することができ
る。
Further, in the above embodiment, an example in which a silicon nitride film is used as a protective film has been described, but the present invention is not limited to this, and a semiconductor using a silicon oxide film (SiO 2 ) as a protective film. It can also be applied to a device.

【0023】[0023]

【発明の効果】以上説明したように本発明によれば、中
間絶縁膜上に2層目のメッキ用電極を形成する前に、開
口形成に用いたフォトレジスト膜を利用してポリイミド
膜のみを再び選択的にエッチングして中間絶縁膜に形成
される開口を上方へ向かって開いた形状にし、この後
に、2層目のメッキ用電極を形成するようにしたため、
メッキ用電極のステップ断線を確実に防止することがで
きる。そして、この効果は、元々用いていたフォトレジ
スト膜を利用してポリイミド膜のみを再びエッチングす
るというわずかな工程の追加だけで得ることができ、製
造ラインの大幅な変更やコストの大幅な増大を招くこと
はない。
As described above, according to the present invention, only the polyimide film is formed by using the photoresist film used for forming the opening before forming the second-layer plating electrode on the intermediate insulating film. By selectively etching again, the opening formed in the intermediate insulating film is opened upward, and after that, the plating electrode of the second layer is formed.
Step disconnection of the plating electrode can be reliably prevented. And, this effect can be obtained by only adding a slight step of re-etching only the polyimide film using the photoresist film that was originally used, which causes a drastic change in the manufacturing line and a drastic increase in cost. There is no invitation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の方法を説明する断面図。FIG. 1 is a sectional view illustrating a method according to an embodiment of the present invention.

【図2】本発明の一実施例の方法を説明する断面図。FIG. 2 is a sectional view illustrating a method according to an embodiment of the present invention.

【図3】従来例の方法を説明する断面図。FIG. 3 is a sectional view illustrating a method of a conventional example.

【図4】従来例の方法を説明する断面図。FIG. 4 is a cross-sectional view illustrating a method of a conventional example.

【図5】従来例の方法を説明する断面図。FIG. 5 is a cross-sectional view illustrating a method of a conventional example.

【図6】従来例の方法を説明する断面図。FIG. 6 is a cross-sectional view illustrating a method of a conventional example.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/90 B ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 21/90 B

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電極が設けられた半導体基板上に、半導
体基板側から保護膜、ポリイミド膜を層状に重ねて成る
中間絶縁膜を設け、この中間絶縁膜に開口を形成して配
線を接続する半導体装置の製造方法において、前記中間
絶縁膜上に開口パターンを有するフォトレジストマスク
を設けてエッチングによりポリイミド膜に開口を形成す
る工程と、前記フォトレジストマスク及びポリイミド膜
をマスクとしてエッチングにより保護膜に開口を形成す
る工程と、前記フォトレジストマスクを利用して再びポ
リイミド膜を選択的にエッチングし、保護膜の開口縁部
に対してポリイミド膜の開口縁部を側方へ後退させる工
程と、前記フォトレジストマスクを除去した後に中間絶
縁膜上に前記電極に接続した配線を設ける工程と、を備
えたことを特徴とする半導体装置の製造方法。
1. An intermediate insulating film formed by stacking a protective film and a polyimide film in layers from the semiconductor substrate side on a semiconductor substrate provided with electrodes, and an opening is formed in this intermediate insulating film to connect wiring. In the method of manufacturing a semiconductor device, a step of forming an opening in a polyimide film by etching by providing a photoresist mask having an opening pattern on the intermediate insulating film, and a protective film by etching using the photoresist mask and the polyimide film as a mask. A step of forming an opening, a step of selectively etching the polyimide film again by using the photoresist mask, and a step of laterally retreating the opening edge portion of the polyimide film with respect to the opening edge portion of the protective film, Providing a wiring connected to the electrode on the intermediate insulating film after removing the photoresist mask. Manufacturing method of semiconductor device.
JP5238103A 1993-09-24 1993-09-24 Manufacture of semiconductor device Pending JPH0794481A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5238103A JPH0794481A (en) 1993-09-24 1993-09-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5238103A JPH0794481A (en) 1993-09-24 1993-09-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0794481A true JPH0794481A (en) 1995-04-07

Family

ID=17025227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5238103A Pending JPH0794481A (en) 1993-09-24 1993-09-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0794481A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012008075A1 (en) * 2010-07-12 2012-01-19 パナソニック株式会社 Nitride semiconductor device
US8569843B2 (en) 2008-10-21 2013-10-29 Panasonic Corporation Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569843B2 (en) 2008-10-21 2013-10-29 Panasonic Corporation Semiconductor device
WO2012008075A1 (en) * 2010-07-12 2012-01-19 パナソニック株式会社 Nitride semiconductor device
JP2012023074A (en) * 2010-07-12 2012-02-02 Panasonic Corp Nitride semiconductor device
CN102959686A (en) * 2010-07-12 2013-03-06 松下电器产业株式会社 Nitride semiconductor device
US8748995B2 (en) 2010-07-12 2014-06-10 Panasonic Corporation Nitride semiconductor device with metal layer formed on active region and coupled with electrode interconnect

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