JPS5911647A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS5911647A JPS5911647A JP12090382A JP12090382A JPS5911647A JP S5911647 A JPS5911647 A JP S5911647A JP 12090382 A JP12090382 A JP 12090382A JP 12090382 A JP12090382 A JP 12090382A JP S5911647 A JPS5911647 A JP S5911647A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring
- photo resist
- steep
- metal wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 230000000873 masking effect Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 230000001429 stepping effect Effects 0.000 abstract 3
- 239000010408 film Substances 0.000 description 22
- 238000007747 plating Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 241000209507 Camellia Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 235000018597 common camellia Nutrition 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Weting (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置及び製造方法に係り、特に多層配線
構造を有する半導体装置の層間連絡孔及びその製造方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a manufacturing method, and more particularly to an interlayer communication hole of a semiconductor device having a multilayer wiring structure and a manufacturing method thereof.
半導体装置の集積度を高める為には多層配線を行なう８
璧があり、また小型で急峻な層間連絡孔が用いられてｂ
る。Multilayer wiring is used to increase the degree of integration of semiconductor devices8
There is a wall, and a small and steep interlayer communication hole is used.
Ru.
また、第１図の如〈従来回避されていた第一の眉間連絡
孔直上に第２の層間連絡孔を形成すること鬼用いられて
いる。Furthermore, as shown in FIG. 1, it is now possible to form a second interlayer communication hole directly above the first glabella communication hole, which has been avoided in the past.
第１図は半導体基板上に第１の金属配線形成後、第１の
Ｃ縁ｗ′ｆｔ成長し急峻な第１の層間連絡孔を形成し、
該第１の層間連絡孔を被覆するよう第２の金属配線を形
成し、第２の絶縁膜成長後、第１の層間連絡孔上に第２
の層間連絡孔を形成した所である。FIG. 1 shows that after a first metal wiring is formed on a semiconductor substrate, a first C edge w'ft is grown to form a steep first interlayer communication hole,
A second metal wiring is formed to cover the first interlayer communication hole, and after the second insulating film is grown, a second metal wiring is formed on the first interlayer communication hole.
This is where the interlayer communication holes were formed.
該方法は第１の層間連絡孔及び第２の金属配線により非
常に急峻な段ができてしまう。次に第３の配線形成の為
金属蒸着物例えばアルミニウム（／ｙｌ）を蒸着すると
第２図の如く該段部でのステップカバレッジが悪くなり
配線寿命等の信頼性上の大きな問題となる。In this method, a very steep step is created due to the first interlayer communication hole and the second metal wiring. Next, when a metal vapor deposit such as aluminum (/yl) is vapor-deposited to form the third wiring, the step coverage at the stepped portion deteriorates as shown in FIG. 2, causing a serious problem in terms of reliability such as the life of the wiring.
又、第３の配線をメッキ等で行なう場合にはメ、キ用の
電極を形成する訳だが第２図の如く第２配線の保護膜と
してチタン＜Ｔｉ ＞等の薄い膜を蒸着するが該方法で
も段部でのステップカバレッジが悪く完全な保抑膜には
ならない。該保護膜上に八ｌを蒸着しフォトリゾグラフ
ィ技術及び金属腐食技術を用いて電極を形成する訳だが
、Ｔｉのステ、プカバレッジが悪い為第３図の如く第２
の金属配線も腐食され、第２の金属配線の断線あるいは
配線寿命等の問題がある。In addition, when the third wiring is formed by plating or the like, electrodes for the holes and keys are formed, but as shown in Figure 2, a thin film of titanium or the like is deposited as a protective film for the second wiring. Even with this method, the step coverage at the stepped portion is poor and a complete retention film cannot be obtained. On the protective film, 8L is vapor deposited and electrodes are formed using photolithography and metal corrosion techniques. However, due to the poor step coverage of Ti, the second step was performed as shown in Figure 3.
The second metal wiring is also corroded, causing problems such as disconnection of the second metal wiring or shortened wiring life.
本発明は第２の金属配線の断線あるいは配線寿命等の信
頼性上の問題をなくした半導体装置及びその製造方法を
提供するものである。The present invention provides a semiconductor device and a method for manufacturing the same, which eliminate reliability problems such as disconnection of the second metal wiring or the life of the wiring.
本発明の％徴は第１の絶縁膜の第１の層間連絡孔及び第
２の金属配線形成後に生じた急峻な段を第２の絶縁膜を
用いて埋めつくした半導体装置の構造にある。さらに本
発明の他の特徴は、半導体製造工程に於いて第１の絶縁
膜に第１の層間連絡孔を形成し、該第１の層間連絡孔を
被覆するよう第２の金属配線を形成して、第２の絶縁膜
を成長する工程と、該第２の絶縁膜上に７オトレジスト
を塗布し、選択露光により第１の層間連絡孔直上に、該
第１の層間連絡孔と同等以上の開口部を形成し、急峻な
段部にのみフォトレジストが残るよう露光してパターン
を形成する工程と、該フォトレジストパターン全マスク
に第２の絶縁膜をエッチアウトし急峻な段部が第２の絶
縁膜により埋めつくされることを特徴とする半導体装置
の製造方法にある。The % characteristic of the present invention lies in the structure of the semiconductor device in which the first interlayer communication hole of the first insulating film and the steep step formed after the formation of the second metal wiring are completely filled with the second insulating film. Furthermore, another feature of the present invention is that a first interlayer communication hole is formed in the first insulating film in the semiconductor manufacturing process, and a second metal wiring is formed to cover the first interlayer communication hole. Then, a step of growing a second insulating film, coating a 7-layer photoresist on the second insulating film, and applying a selective exposure to directly above the first interlayer communication hole to form a film with a thickness equal to or higher than that of the first interlayer communication hole. A process of forming an opening and exposing the photoresist to form a pattern so that the photoresist remains only on the steep step portions, and etching out the second insulating film on the entire mask of the photoresist pattern so that the steep step portions are removed from the second insulating film. A method of manufacturing a semiconductor device characterized in that the semiconductor device is completely filled with an insulating film.
該方法によれば、第１の層間連絡孔及び第２の金属配線
による急峻な段を完全に埋めつくされ、第３の配線のス
テ、プカバレッジの問題は解決する。又、メッキ配線を
行なう場合でも保護膜は完全に第２の金属配線を被覆で
き電極形成の際の金属腐食の際でも第２の金属配線を腐
食することはない、。According to this method, the first interlayer communication hole and the second metal wiring completely fill the steep steps, and the problem of step coverage of the third wiring is solved. Further, even when plating wiring is performed, the protective film can completely cover the second metal wiring, and the second metal wiring will not be corroded even when metal corrosion occurs during electrode formation.
次に本発明の実施例？順を追って説明する。Next, an example of the present invention? I will explain step by step.
第４図は半導体基板１上に第１の配線３を形成し、その
後、第一の絶縁膜４を成長し、第１の層間連絡孔を形成
し、第２の金属配線５を形成した構造を示す。次に全面
に層間絶縁膜６を全面に成長後フォトレジスト９を塗布
した所全第５図に示す。該状態に於いては、第１の層間
連絡孔、第２金属配線及び第２の層間絶縁膜により形成
される急峻な段部には厚くポジフォトレジストが塗布さ
れる。次に第１の層間連絡孔直上に第１の層間連絡孔と
同等以上の開孔部を該フォトレジストに選択露光して開
孔部全形成する。この露光条件を適度に設定すれば急峻
な段部にはフォトレジストが残っている。該状態を第６
図に示す。次に該フオトレジス）ｋマスクに第２の絶縁
膜をエツチングし、フォトレジスト層を除去した図を第
７図に示す。第８図に第２の金属配線保護膜（Ｔｔ）７
゜電第１５用σ）Δｌ、８を蒸着後フォトレジスト１０
でノくターン形成した構造を示す。FIG. 4 shows a structure in which a first wiring 3 is formed on a semiconductor substrate 1, then a first insulating film 4 is grown, a first interlayer communication hole is formed, and a second metal wiring 5 is formed. shows. Next, an interlayer insulating film 6 is grown on the entire surface, and then a photoresist 9 is applied, as shown in FIG. In this state, a thick positive photoresist is applied to the steep steps formed by the first interlayer communication hole, the second metal wiring, and the second interlayer insulating film. Next, the entire opening is formed by selectively exposing the photoresist to an opening that is equal to or larger than the first interlayer communication hole directly above the first interlayer communication hole. If the exposure conditions are set appropriately, photoresist remains on the steep steps. The state is the sixth
As shown in the figure. Next, a second insulating film is etched on the photoresist mask and the photoresist layer is removed, as shown in FIG. FIG. 8 shows a second metal wiring protective film (Tt) 7.
゜Photoresist 10 after depositing σ) Δl, 8 for electron No. 15
It shows a structure formed with a number of turns.
次に該フォトレジスト層をマスクにＡｌを金属腐食技術
を用いて電極形成後金メッキ等で第３の配線を形成した
構造を９図に示す。次にフォトレジスト、Ａｌ、Ｔｉを
除去し、第３の配線を形成した構造を１０図に示す。Next, using the photoresist layer as a mask, electrodes are formed on Al using a metal corrosion technique, and then a third wiring is formed by gold plating or the like, as shown in FIG. 9. Next, the photoresist, Al, and Ti are removed, and the structure in which the third wiring is formed is shown in FIG.
該方法により第２の金属配線も腐食されず、又第３の配
線もステップカバレッジ等の問題なく、信頼性の高い多
層配線が形成できる。By this method, the second metal wiring is not corroded, and the third wiring is also free from problems such as step coverage, and a highly reliable multilayer wiring can be formed.
第１図乃至第３図は従来の半導体装置の断面図、第４図
乃至第１０向は本発明の製造方法の一実施例を工程順に
説明する為の断面図である。
尚、図に於いて、
１・・・・・シリコン基板、２・・・・・・酸化膜、３
・・・第１の配線、４ ・・・第１の絶縁膜、５・・
・第２の金属配線、６・・・・・第２の絶縁膜、７・・
・・保梅膜（チタン）、８・・・・・・電極用アルミニ
ウム、９・ ・フォトレジスト、１０・・・・・フォ）
・レジスト、１１・・第３のメッキ配線、である。
椿１図
惨４ 図
第５ 図
篠乙図
第７図
委δ 図
湘ｅ召５９−１１６４７（４）
１／1 to 3 are cross-sectional views of a conventional semiconductor device, and FIGS. 4 to 10 are cross-sectional views for explaining an embodiment of the manufacturing method of the present invention in the order of steps. In the figure, 1... silicon substrate, 2... oxide film, 3
...first wiring, 4 ...first insulating film, 5...
・Second metal wiring, 6...Second insulating film, 7...
・・Houme membrane (titanium), 8・・・・Aluminum for electrodes, 9・・Photoresist, 10・・・・・F)
-Resist, 11...Third plating wiring. Camellia 1 Figure 4 Figure 5 Shinotsu Figure 7 Figure δ Figure 59-11647 (4) 1/
Claims (2)
連絡孔及び該第１の層間連絡孔を被覆するよう第２の金
属配線形成後に生じた第１の層間連絡孔上の急峻な段を
第２の絶縁膜で埋めつくしたことを特徴とする半導体装
置。(1) In a semiconductor device, a first interlayer communication hole in a first insulating film and a second metal wiring formed on the first interlayer communication hole formed after forming a second metal wiring to cover the first interlayer communication hole; A semiconductor device characterized in that a steep step is completely filled with a second insulating film.
孔全形成し該第１の層間連絡孔を被覆して第２の金属配
線を形成し第２の絶縁膜を成長する工程と、該第２の絶
縁膜上にフォトレジストを塗布し選択露光により該第１
の層間連絡孔直上に第１の層間連絡孔と同等以上の開孔
部を形成し、かつ急峻な段部にのみフォトレジストヲ残
すよう露光してパターンニングする工程と、該フォトレ
ジストパターン全マスクに第２の絶縁膜を工、チアウド
し前記急峻な段部を前記第２の絶縁膜により埋めつくす
ことを特徴とする半導体装置の製造方法。(2) In the manufacturing process of a semiconductor device, a step of forming all the first interlayer communication holes, forming a second metal wiring to cover the first interlayer communication holes, and growing a second insulating film; , apply a photoresist on the second insulating film and selectively expose the first insulating film.
A step of forming an aperture equal to or larger than the first interlayer communication hole directly above the interlayer communication hole, and exposing and patterning the photoresist so as to leave it only in the steep steps, and masking the entire photoresist pattern. 1. A method of manufacturing a semiconductor device, characterized in that a second insulating film is etched and bonded, and the steep stepped portion is completely filled with the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12090382A JPS5911647A (en) | 1982-07-12 | 1982-07-12 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12090382A JPS5911647A (en) | 1982-07-12 | 1982-07-12 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5911647A true JPS5911647A (en) | 1984-01-21 |
| JPS6362104B2 JPS6362104B2 (en) | 1988-12-01 |
Family
ID=14797844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12090382A Granted JPS5911647A (en) | 1982-07-12 | 1982-07-12 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5911647A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62146224A (en) * | 1985-12-20 | 1987-06-30 | Kobe Steel Ltd | Manufacture of high carbon steel wire having high toughness and tension and less variance in strength |
| JPH03116852A (en) * | 1989-09-29 | 1991-05-17 | Nec Corp | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57100748A (en) * | 1980-12-15 | 1982-06-23 | Toshiba Corp | Manufacture of semiconductor device |
-
1982
- 1982-07-12 JP JP12090382A patent/JPS5911647A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57100748A (en) * | 1980-12-15 | 1982-06-23 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62146224A (en) * | 1985-12-20 | 1987-06-30 | Kobe Steel Ltd | Manufacture of high carbon steel wire having high toughness and tension and less variance in strength |
| JPH03116852A (en) * | 1989-09-29 | 1991-05-17 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6362104B2 (en) | 1988-12-01 |
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