JPS59181031A - Forming method of aerial wiring - Google Patents

Forming method of aerial wiring

Info

Publication number
JPS59181031A
JPS59181031A JP5629883A JP5629883A JPS59181031A JP S59181031 A JPS59181031 A JP S59181031A JP 5629883 A JP5629883 A JP 5629883A JP 5629883 A JP5629883 A JP 5629883A JP S59181031 A JPS59181031 A JP S59181031A
Authority
JP
Japan
Prior art keywords
film
forming
resist film
insulating film
aerial wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5629883A
Other languages
Japanese (ja)
Other versions
JPH0223029B2 (en
Inventor
Osamu Akanuma
赤沼 収
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5629883A priority Critical patent/JPS59181031A/en
Publication of JPS59181031A publication Critical patent/JPS59181031A/en
Publication of JPH0223029B2 publication Critical patent/JPH0223029B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the disconnection of wirings by selectivey removing an insulating film on an element to be crosslinked by aerial wirings covered with an insulating film on a substrate, opening a contacting hole, and forming a resist film with the element exposed on the surface in the hole as a hole. CONSTITUTION:A strip line 2, a capacitor 3, a lower electrode 4, an upper electrode 5 and a dielectric layer 6 are formed on a dielectric substrate 1, and an insulating film 7 is covered. Then, a negative resist film 8 formed on the film 7 as a mask, the film 7 is selectively removed, and a contacting hole 9 is formed on the element to be connected in a bridge. Then, the resist film is selectively removed by the same photomask used in case of patterning the film 8. Thus, the recess 10 is buried by the film 21. Then, a base metal layer 11 made of Cr-Pt-Au layer is formed entirely, Au is further covered to form a conductive metal layer 15. Subsequently, the films 11, 7 are removed.

Description

【発明の詳細な説明】 (al  発明の技術分野 本発明は半導体集積回路装置或いはマイクロ波集積回路
装置等における空中配線の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for forming aerial wiring in a semiconductor integrated circuit device, a microwave integrated circuit device, or the like.

(b)  従来技術と問題点 ガリウム・砒素(GaAs)よりなる超高周波用半導体
装置、或いは超高周波用GaAs半導体素子を用いて作
成するマイクロ波集積回路装置(IG)等を製作するに
際し、回路素子間の接続に空中配線がしばしば用いられ
る。
(b) Prior art and problems When manufacturing ultra-high frequency semiconductor devices made of gallium arsenide (GaAs) or microwave integrated circuit devices (IG) made using ultra-high frequency GaAs semiconductor elements, circuit elements Aerial wiring is often used to connect between

第1図は従来の空中配線(以下ブリッジと称する)の形
成方法を工程の順に示す要部断面図であって、マイクロ
波集積回路装置を製作する例である。
FIG. 1 is a sectional view of a main part showing the conventional method for forming an aerial wiring (hereinafter referred to as a bridge) in the order of steps, and is an example of manufacturing a microwave integrated circuit device.

同図(alにおいて、1はセラミック、サファイア等か
らなる誘電体基板、2はストリップライン、3はキャパ
シタで、導電金属からなる下部電極4゜上部電極5.及
び誘電体層6からなり、また7は絶縁層である。図示し
たようにキャパシタ3等の素子及びストリップライン2
のような配線等を形成した後、ポリイミド等の絶縁膜7
を全面に被覆して表面を平坦にする。
In the same figure (al), 1 is a dielectric substrate made of ceramic, sapphire, etc., 2 is a strip line, 3 is a capacitor, and consists of a lower electrode 4, an upper electrode 5, and a dielectric layer 6 made of conductive metal, and 7 is an insulating layer.As shown in the figure, elements such as capacitor 3 and strip line 2
After forming wiring etc., an insulating film 7 of polyimide etc.
Cover the entire surface to make the surface flat.

次いで同図(b)に示すように、この絶縁膜7上に選択
的に形成したネガ型レジスト膜8をマスクとして、上記
絶縁膜7を選択的に除去し、ブリッジにて互いに接続す
べき素子上にコンタクトホール9を形成する。同図はス
トリップライン2及びキャパシタ3の上部電極5表面に
コンタクトホール9を形成した例である。本工程におい
て、各コンタクトホール9の大きさ及びその直下の各素
子上のレジスト膜8の厚さが異なるため、エツチング所
要時間は各コンタクトホール毎に相違する。このため同
図の10に示すような窪みが出来ることとなる。
Next, as shown in FIG. 3B, using the negative resist film 8 selectively formed on the insulating film 7 as a mask, the insulating film 7 is selectively removed, and the elements to be connected to each other by a bridge are removed. A contact hole 9 is formed above. This figure shows an example in which a contact hole 9 is formed on the surface of the strip line 2 and the upper electrode 5 of the capacitor 3. In this step, since the size of each contact hole 9 and the thickness of the resist film 8 on each element directly below it are different, the time required for etching is different for each contact hole. For this reason, a depression as shown in 10 in the same figure is formed.

上記工程の後同図(C)に見られる如く、レジスト膜8
を除去し、蒸着法により全面にクローム(Cr)−白金
(Pt)−金(Au)を順次被着させて下地金属[11
を形成し、次いでブリッジを形成すべき部分を開口部と
するレジスト膜12を形成する。この工程において、前
述の窪み10があるとそこにレジストの溜り13が出来
る。このあと上記レジスト膜12をマスクとして下地金
属層11上にメッキ法により凡そ5〔μm〕の厚さにA
uを被着せしめ、導電配線層14を形成するのであるが
、上記レジストの溜り13上にはAu層が形成されない
After the above step, as shown in the same figure (C), the resist film 8
was removed, and chromium (Cr)-platinum (Pt)-gold (Au) was sequentially deposited on the entire surface by vapor deposition to form the base metal [11
, and then a resist film 12 is formed having an opening at the portion where the bridge is to be formed. In this step, if the aforementioned depression 10 exists, a resist pool 13 is formed there. After that, using the resist film 12 as a mask, the base metal layer 11 is plated to a thickness of about 5 [μm].
Although the conductive wiring layer 14 is formed by depositing Au, the Au layer is not formed on the resist pool 13.

そのため上記レジスト膜12を除去し、導電配線層I4
をマスクとしてイオンミリング法等の乾式エツチング(
ドライエツチング)法により下地金属層11の不要部を
除去し、更に酸素プラズマによるアッシング法等によっ
て絶縁膜7を除去すると、同図fd)に見られる如く前
記レジスト溜り13が存在していた部分にブリッジ15
が形成されず、断線状態となってしまう。
Therefore, the resist film 12 is removed and the conductive wiring layer I4 is removed.
Dry etching such as ion milling method (
When unnecessary portions of the base metal layer 11 are removed by a dry etching method and the insulating film 7 is further removed by an ashing method using oxygen plasma, as shown in fd) in the same figure, the portion where the resist pool 13 was present is removed. bridge 15
is not formed, resulting in a disconnection state.

(C1発明の目的 本発明の目的は上記問題点を解消して、断線の生じるこ
とのない空中配線の形成方法を提供することにある。
(C1 Purpose of the Invention The purpose of the present invention is to solve the above-mentioned problems and to provide a method for forming an aerial wiring in which disconnection does not occur.

(dl  発明の構成 本発明の特徴は、所定の基板上に配設された多数の素子
間の要部に空中配線を形成するに際し、前記基板上を絶
縁膜で被覆し、前記空中配線で橋絡すべき素子上の絶縁
膜を選択的に除去してコンタクトホールを開口した後、
上記コンタクトホール内で表面を露呈せる素子上を開口
部とするレジスト膜を形成する工程と、該レジスト膜及
び前記露呈せる素子上に所定の金属よりなる配線を形成
する工程とを含むことにある。
(dl Structure of the Invention The feature of the present invention is that when forming aerial wiring in the main parts between a large number of elements arranged on a predetermined substrate, the substrate is covered with an insulating film, and the aerial wiring is used as a bridge. After selectively removing the insulating film on the element to be connected and opening a contact hole,
The method includes the steps of forming a resist film having an opening on the element whose surface is exposed in the contact hole, and forming a wiring made of a predetermined metal on the resist film and the exposed element. .

tel  発明の実施例 以下本発明の一実施例を製造工程の順に図面を参照しな
がら説明する。
tel Embodiment of the Invention An embodiment of the present invention will be described below in the order of manufacturing steps with reference to the drawings.

第2図は上記一実施例の製造工程を順に示す要部断面図
である。同図(alは前記第1図(blを再出したもの
であって、ここまでは従来の製造工程に従って進めて良
い。なお第2図において前記第1図と同一部分は同一符
号を付して示しである。
FIG. 2 is a cross-sectional view of a main part sequentially showing the manufacturing process of the above embodiment. The same figure (al is a reproduction of the above-mentioned figure 1 (bl), and up to this point you can proceed according to the conventional manufacturing process. In addition, in Fig. 2, the same parts as in the above-mentioned Fig. 1 are given the same reference numerals. This is an indication.

従来の製造方法ではこの後、Cr−Pt−Au層からな
る下地金属層11を被着せしめる工程を施したが、オー
バエツチング等により形成された窪み10部に上記下地
金属層11が形成されないという問題があった。
In the conventional manufacturing method, a step of depositing a base metal layer 11 made of a Cr-Pt-Au layer was then carried out, but the base metal layer 11 was not formed in the 10 depressions formed by over-etching or the like. There was a problem.

そこで第2図(blに示す如く本実施例では下地金属層
11を形成するに先立ち、同図(a)のレジスト膜8の
パターニングに使用したのと同一フォトマスクを用いて
レジスト膜21を選択的に形成する。このようにするこ
とにより、前記窪み10はレジスト膜21により埋めら
れ消滅する。
Therefore, as shown in FIG. 2 (bl), in this embodiment, before forming the base metal layer 11, a resist film 21 is selected using the same photomask used for patterning the resist film 8 in FIG. 2(a). By doing so, the depression 10 is filled with the resist film 21 and disappears.

このあとの工程は再び従来の製造工程に従って進めて良
い。即ち第2図(C)に見られる如く上記レジスト膜2
1を選択的に形成したのち、Cr−Pt−’Au層より
なる下地金属層11を全面に形成し、次いでブリッジを
形成すべき部分を開口部とするレジスト膜12を選択的
に形成し、次いでメッキ法により上記下地金属Jiil
lの露呈部上にAuを被着せしめて導電金属[14を形
成する。
The subsequent steps may proceed according to the conventional manufacturing process again. That is, as shown in FIG. 2(C), the resist film 2
1 is selectively formed, a base metal layer 11 made of a Cr-Pt-'Au layer is formed on the entire surface, and then a resist film 12 is selectively formed with openings in the portion where the bridge is to be formed. Next, the above-mentioned base metal JIIL is coated by plating method.
Au is deposited on the exposed portion of 1 to form a conductive metal [14].

次いで同図(dlに示すように、レジス日順2を除去し
、上記導電金属層14をマスクとしてイオンミリング法
等のドライエツチング法を施すことにより、下地金属層
11の不要部を除去し、更に酸素プラズマによるアッシ
ング法等によって絶縁膜7を除去する。なお導電金属層
14は上記ドライエツチング工程を終了した後において
、凡そ5 〔μm〕の厚さを有するよう、被着時にはこ
れより若干厚くしておく。
Next, as shown in FIG. 2, the unnecessary portions of the base metal layer 11 are removed by removing the resist layer 2 and applying a dry etching method such as ion milling using the conductive metal layer 14 as a mask. Furthermore, the insulating film 7 is removed by an ashing method using oxygen plasma, etc.The conductive metal layer 14 is slightly thicker than this when deposited so that it has a thickness of approximately 5 μm after the dry etching process is completed. I'll keep it.

以上のようにして得られた本実施例による空中配線15
は、従来の製造方法で問題となった窪み10をレジスト
により埋めた上で下地金属層11を形成するので、下地
金属Jiillの欠如を生じることがなく、従って空中
配線の断線の発生は完全に防止される。
Aerial wiring 15 according to this example obtained as described above
Since the base metal layer 11 is formed after filling the depression 10, which was a problem in the conventional manufacturing method, with a resist, there is no lack of the base metal, and therefore, the occurrence of disconnections in the aerial wiring is completely eliminated. Prevented.

if)  発明の詳細 な説明した如く本発明により、断線の生じることのない
空中配線の形成方法が提供され、超高周波用マイクロ波
集積回路装置、あるいは超高周波用半導体装置の信頼度
が向上し、且つその製造工程が安定する。
if) As described in detail, the present invention provides a method for forming an aerial wiring without causing disconnection, and improves the reliability of an ultra-high frequency microwave integrated circuit device or an ultra-high frequency semiconductor device. Moreover, the manufacturing process is stable.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al〜(diは従来の空中配線の形成方法の問
題点を説明するための要部断面図、第2図ta>〜fd
)は本発明の一実施例を製造工程の順に示す要部断面図
である。 図において、1は誘電体基板、2はストリップライン、
3はキャパシタで、導電金属からなる下7は絶縁層、8
.12.21はいずれもレジスト膜、9はコンタクトホ
ール、10は窪み、11は下地金属層、13はレジスト
溜り、14は導電金属層、15は空中配線を示す。
Figure 1 (al ~ (di is a sectional view of the main part for explaining the problems of the conventional method of forming aerial wiring, Figure 2 ta > ~ fd
) is a sectional view of a main part showing an embodiment of the present invention in the order of manufacturing steps. In the figure, 1 is a dielectric substrate, 2 is a strip line,
3 is a capacitor, the lower part 7 made of conductive metal is an insulating layer, and the lower part 8 is an insulating layer.
.. 12 and 21 are all resist films, 9 is a contact hole, 10 is a depression, 11 is a base metal layer, 13 is a resist reservoir, 14 is a conductive metal layer, and 15 is an aerial wiring.

Claims (1)

【特許請求の範囲】[Claims] 所定の基板上に配設された多数の素子間の要部に空中配
線を形成するに際し、前記基板上を絶縁膜で被覆し、前
記空中配線で橋絡すべき素子上の絶縁膜を選択的に除去
してコンタクトホールを開口した後、上記コンタクトホ
ール内で表面を露呈せる素子上を開口部とするレジスト
膜を形成する工程と、該レジスト股上に所定の金属より
なる下地金属層を形成する工程と、次いで前記空中配線
を接続すべき素子上を含む所定領域を開口部とするレジ
スト膜を形成する工程と、該レジスト膜及び前記露呈廿
る素子上に所定の金属よりなる配線を形成する工程とを
含むことを特徴とする空中配線の形成方法。
When forming aerial wiring in the main parts between a large number of elements arranged on a predetermined substrate, the substrate is covered with an insulating film, and the insulating film on the elements to be bridged by the aerial wiring is selectively covered. After removing the contact hole to open a contact hole, forming a resist film having an opening over the element whose surface is exposed in the contact hole, and forming a base metal layer made of a predetermined metal on the resist crotch. a step of forming a resist film having an opening in a predetermined area including the top of the element to which the aerial wiring is to be connected; and forming a wiring made of a predetermined metal on the resist film and the exposed element. A method for forming an aerial wiring, comprising the steps of:
JP5629883A 1983-03-30 1983-03-30 Forming method of aerial wiring Granted JPS59181031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5629883A JPS59181031A (en) 1983-03-30 1983-03-30 Forming method of aerial wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5629883A JPS59181031A (en) 1983-03-30 1983-03-30 Forming method of aerial wiring

Publications (2)

Publication Number Publication Date
JPS59181031A true JPS59181031A (en) 1984-10-15
JPH0223029B2 JPH0223029B2 (en) 1990-05-22

Family

ID=13023209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5629883A Granted JPS59181031A (en) 1983-03-30 1983-03-30 Forming method of aerial wiring

Country Status (1)

Country Link
JP (1) JPS59181031A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6376458A (en) * 1986-09-19 1988-04-06 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6376458A (en) * 1986-09-19 1988-04-06 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH0223029B2 (en) 1990-05-22

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