JPS62281356A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS62281356A
JPS62281356A JP12324586A JP12324586A JPS62281356A JP S62281356 A JPS62281356 A JP S62281356A JP 12324586 A JP12324586 A JP 12324586A JP 12324586 A JP12324586 A JP 12324586A JP S62281356 A JPS62281356 A JP S62281356A
Authority
JP
Japan
Prior art keywords
film
metal
forming
protrusion electrode
protruding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12324586A
Other languages
Japanese (ja)
Inventor
Takaaki Kobayashi
孝彰 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12324586A priority Critical patent/JPS62281356A/en
Publication of JPS62281356A publication Critical patent/JPS62281356A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent the yield of the etching residue of a protecting film on the surface of a protruding metallic electrode, by forming a hole in a region, where the protruding metallic electrode for the protecting film is formed, and forming the protruding metallic electrode in a metallic conductor film, which is exposed in the hole by a plating method. CONSTITUTION:An insulating film 4 is formed on the surface of a semiconductor substrate 1. A platinum film 5 is formed in a region, where a protruding gold electrode is to be formed, on the insulating film 4. Thereafter, a photoresist film is formed on the entire surface. The film is patterned by an ordinary way, and a photoresist mask 8 is formed. After the photoresist mask 8 is removed, e.g., a polyimide resin film 9 is applied and formed to a required thickness as a protecting film on the entire surface. The polyimide resin film 9, which is the protecting film, is formed at first, and thereafter the protruding gold electrode 3 is formed by a plating method. Therefore it is not required to perform the etching process of the polyimide resin film 9 after the protruding gold electrode 3 is formed. Even if the surface layer part of the protruding gold electrode is formed in a porous state, etching residue is not yielded on the surface layer part.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にテープキャ
リア式半導体装置のように金属突起電極を有する半導体
装置の製造方法に関する。
[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and in particular a method of manufacturing a semiconductor device having metal protruding electrodes such as a tape carrier type semiconductor device. Regarding.

〔従来の技術] 一般にテープキャリア式半導体装置では、半導体基板の
表面に金属突起電極を形成しておき、この金属突起電極
をテープキャリアの導電面に圧接して実装を行うように
構成されている。
[Prior Art] Tape carrier type semiconductor devices are generally configured such that a metal protrusion electrode is formed on the surface of a semiconductor substrate, and the metal protrusion electrode is pressed against the conductive surface of the tape carrier for mounting. .

従来、この種の半導体装置の製造方法、特に金属突起電
極の製造方法は、次の工程により行なわれている。
Conventionally, a method for manufacturing this type of semiconductor device, particularly a method for manufacturing metal protrusion electrodes, has been carried out by the following steps.

先ず、所要の素子を形成した半導体基板の全面に金属導
電膜を被着し、この上にフォトレジスト膜を形成しかつ
これをパターニングして金属電極形成箇所に窓を開設し
、この部分において金属導電膜を露呈させる。そして、
前記金属導電膜を電流路としてメッキを行い、フォトレ
ジストの窓内に露呈された部分に厚い金属メッキを施し
て金属突起電極を形成する。
First, a metal conductive film is deposited on the entire surface of a semiconductor substrate on which the required elements are formed, a photoresist film is formed on this, and this is patterned to open a window at the location where the metal electrode is to be formed. Expose the conductive film. and,
Plating is performed using the metal conductive film as a current path, and thick metal plating is applied to the portion exposed within the photoresist window to form a metal protrusion electrode.

しかる上で、前記金属導電膜の不要部分をエツチング除
去し、その後に保護膜を全面に塗布形成させ、更にその
後に金属突起上に被着している保護膜を選択的にエツチ
ング除去することにより金属突起電極を露呈させている
Then, unnecessary portions of the metal conductive film are removed by etching, a protective film is then applied to the entire surface, and then the protective film deposited on the metal protrusions is selectively etched away. The metal protrusion electrode is exposed.

〔発明が解決しようとする間°照点〕[While the invention is trying to solve the problem]

上述した従来の金属突起電極の製造方決では、金属突起
電極を形成した後に保護膜を塗布し、かつその後にこの
保護膜をエツチング除去して金属突起電極の表面を露呈
させる工程となっているため、金属突起電極の表面上の
保j!膜に対するエツチングを行うことになる。
The conventional manufacturing method for metal protrusion electrodes described above involves coating a protective film after forming the metal protrusion electrode, and then removing the protective film by etching to expose the surface of the metal protrusion electrode. Therefore, the retention on the surface of the metal protrusion electrode! The film will be etched.

ところが、金属突起電極はメッキ法によりポーラス状に
成長させているため、金属突起電極の表層部には保護膜
のエツチング残渣が極めて高い確率で発生し易くなる。
However, since the metal protrusion electrode is grown in a porous manner by a plating method, etching residue of the protective film is likely to be generated on the surface layer of the metal protrusion electrode with an extremely high probability.

このため、金属突起電極をテープキャリアの導電面に圧
着させると、金属突起電極と導電面との間にこの残渣が
介在して両者の密着性を劣化させ、機械的及び電気的な
接続不良を発生させるという問題が生じる。
Therefore, when the metal protrusion electrode is pressed onto the conductive surface of the tape carrier, this residue will be present between the metal protrusion electrode and the conductive surface, degrading the adhesion between the two and causing mechanical and electrical connection failures. The problem arises that this occurs.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の半導体装置の製造方法は、金属突起電極の表面
における保護膜のエツチング残渣の発生を防止し、実装
に際しての導電面への機械的及び電気的な接続の信顛性
を高めるものである。
The method for manufacturing a semiconductor device of the present invention prevents the generation of etching residue of a protective film on the surface of a metal protrusion electrode, and improves the reliability of mechanical and electrical connection to a conductive surface during mounting. .

本発明の半導体装置の製造方法は、メンキ時の電流路と
しての金属導電膜を形成する工程と、この金属導電膜上
に保護膜を形成する工程と、この保護膜の金属突起電極
を形成する領域に開口を形成する工程と、この開口内に
露呈された前記金属導電膜上にメッキ法により金属突起
電極を形成する工程と、その後に前記金属導電膜の不要
部分をエツチング除去する工程を含むものである。
The method for manufacturing a semiconductor device of the present invention includes a step of forming a metal conductive film as a current path during thinning, a step of forming a protective film on the metal conductive film, and a step of forming metal protruding electrodes of the protective film. The method includes a step of forming an opening in a region, a step of forming a metal protrusion electrode by plating on the metal conductive film exposed in the opening, and a step of etching away unnecessary portions of the metal conductive film. It is something that

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明方法により形成する金属突起電極を備え
た半導体装置の平面図であり、その製造工程を第2図(
a)〜(g)に示している。なお、第2図の各図は第1
図のAA線に沿う断面図である。
FIG. 1 is a plan view of a semiconductor device equipped with metal protruding electrodes formed by the method of the present invention, and FIG.
Shown in a) to (g). Note that each figure in Figure 2 is the same as Figure 1.
FIG. 3 is a cross-sectional view taken along line AA in the figure.

即ち、この実施例では、第1図のように、所要の素子を
形成した半導体基板(シリコンウェハ)lに複数の素子
チップを形成し、各素子チップには素子チップを相互に
切断分離するダイシングライン2に近接配置して金属突
起電極、ここでは金(Au)を用いた金突起電極3を配
設している。
That is, in this embodiment, as shown in FIG. 1, a plurality of element chips are formed on a semiconductor substrate (silicon wafer) l on which required elements are formed, and each element chip is subjected to dicing to cut and separate the element chips from each other. A metal protrusion electrode, here a gold protrusion electrode 3 made of gold (Au), is disposed close to the line 2 .

先ず、第2図(a)のように、半導体基板1の表面には
絶縁膜4を形成し、かつこの絶縁膜4上には金突起電掻
を形成する領域に白金膜5を形成する。この白金膜5の
形成には選択エツチング法或いはリフトオフ法等が用い
られる。なお、ダイシングライン2の領域では、前記絶
縁膜4を除去して半導体基板1面を露呈させている。
First, as shown in FIG. 2(a), an insulating film 4 is formed on the surface of a semiconductor substrate 1, and a platinum film 5 is formed on this insulating film 4 in a region where a gold protrusion is to be formed. A selective etching method, a lift-off method, or the like is used to form the platinum film 5. Note that in the region of the dicing line 2, the insulating film 4 is removed to expose the surface of the semiconductor substrate 1.

次いで、同図(b)のように蒸着法又はスパッタ法によ
りアルミニウム6を全面に被着し、その後陽極酸化法に
よりアルミろラム6の表面部のみを酸化して酸化アルミ
ニウム層7を形成する。
Next, as shown in FIG. 2B, aluminum 6 is deposited on the entire surface by vapor deposition or sputtering, and then only the surface of the aluminum filter 6 is oxidized by anodizing to form an aluminum oxide layer 7.

その後、同図(C)のように、全面にフォトレジスト膜
を形成した上で常法によりこれをバターニングしてフォ
トレジストマスク8を形成し、これをマスクとして前記
酸化アルミニウム層7及びアルミニウム6を選択的にエ
ツチングする。これにより、前記ダイシングライン2の
領域及びここから前記白金膜5に繋がる領域にのみアル
ミニウム6及び酸化アルミニウム層7が残存される。
Thereafter, as shown in FIG. 2C, a photoresist film is formed on the entire surface and then buttered by a conventional method to form a photoresist mask 8, and this is used as a mask to cover the aluminum oxide layer 7 and the aluminum 6. selectively etched. As a result, the aluminum 6 and the aluminum oxide layer 7 remain only in the region of the dicing line 2 and the region connected from this to the platinum film 5.

なお、このアルミニウム6及び酸化アルミニウム層7の
平面パターン形状は、第3図に示す通りである。この結
果、各素子チップに夫々独立して形成されている白金膜
5はアルミニウム6によって電気的に相互接続され、こ
れが後述するメッキ時の電流路としての金属導電膜とし
て構成されることになる。
Note that the planar pattern shapes of the aluminum 6 and the aluminum oxide layer 7 are as shown in FIG. As a result, the platinum films 5 formed independently on each element chip are electrically interconnected by the aluminum 6, and this constitutes a metal conductive film that serves as a current path during plating, which will be described later.

次いで、前記フォトレジストマスク8を除去した後、同
図(d)のように全面に保護膜として例えばポリイミド
樹脂膜9を所要の厚さに塗布形成する。そして、同図(
e)のように、常法によりパターニングしたフォトレジ
ストlOをマスクにしてこのポリイミド樹脂膜9をエツ
チングし、金突起電極形成領域とダイシングライン領域
をエツチング除去して夫々窓9a、9bを開設する。こ
れにより、金突起電極形成領域の窓9aには白金膜5が
露呈され、ダイシングライン領域2では酸化アルミニウ
ム層7が露呈される。この平面状態は前記第3図に示す
通りである。
After removing the photoresist mask 8, a protective film, such as a polyimide resin film 9, is coated on the entire surface to a desired thickness, as shown in FIG. 3(d). And the same figure (
As shown in e), the polyimide resin film 9 is etched using a photoresist lO patterned by a conventional method as a mask, and the gold protrusion electrode forming area and the dicing line area are etched away to form windows 9a and 9b, respectively. As a result, the platinum film 5 is exposed in the window 9a of the gold protrusion electrode formation region, and the aluminum oxide layer 7 is exposed in the dicing line region 2. This planar state is as shown in FIG. 3 above.

しかる上で、半導体基板1を金メツキ液中に浸漬し、ア
ルミニウム6及び白金TIIJ、5からなる金属導電膜
を電流路として、メッキ装置の陽極電極板との間に電流
を流してメッキを行うことにより、同図(f)のように
、窓9a内の白金膜5上に所要厚さの金メッキ層、即ち
金突起電極3が形成される。
Then, the semiconductor substrate 1 is immersed in a gold plating solution, and plating is performed by passing a current between it and the anode electrode plate of the plating device, using the metal conductive film made of aluminum 6 and platinum TIIJ, 5 as a current path. As a result, as shown in FIG. 9(f), a gold plating layer of a required thickness, that is, a gold protrusion electrode 3, is formed on the platinum film 5 within the window 9a.

その後、前記フォトレジスト10及び形成した金突起電
極3をマスクにし、同図(g)のように窓9b内のダイ
シングライン領域2に露呈されている酸化アルミニウム
層7及びアルミニウム6をエツチング除去する。これに
より、各白金膜5及び金突起電極3は夫々電気的に独立
され、相互に絶縁状態とされる。
Thereafter, using the photoresist 10 and the formed gold protrusion electrode 3 as a mask, the aluminum oxide layer 7 and aluminum 6 exposed in the dicing line region 2 within the window 9b are etched away, as shown in FIG. 3(g). As a result, each platinum film 5 and gold protrusion electrode 3 are electrically independent and insulated from each other.

そして、前記フォトレジスト10を除去することにより
、半導体装置が完成される。第1図はこの完成状態の平
面図であることは前述の通りである。
Then, by removing the photoresist 10, the semiconductor device is completed. As mentioned above, FIG. 1 is a plan view of this completed state.

したがって、この方法によると、先に保護膜であるポリ
イミド樹脂膜9を形成しておき、その後に金突起電極3
をメッキ法により形成しているので、金突起電極3の形
成後にポリイミド樹脂膜9のエツチング工程を行う必要
がない。このため、金突起電掻3の表層部がポーラス状
に形成されていてもエツチング残渣が表層部に生じるこ
とはなく、したがって金突起電掻3をテープキャリアの
導電面に圧接させた時の機械的及び電気的接続を高い信
頼性で行うことができる。
Therefore, according to this method, the polyimide resin film 9 as a protective film is first formed, and then the gold protrusion electrode 3 is formed.
Since it is formed by a plating method, there is no need to perform an etching process on the polyimide resin film 9 after forming the gold protrusion electrode 3. Therefore, even if the surface layer of the gold protrusion electric scraper 3 is formed in a porous shape, no etching residue is generated on the surface layer, and therefore, when the gold protrusion electric scraper 3 is pressed against the conductive surface of the tape carrier, the mechanical physical and electrical connections can be made with high reliability.

また、この方法では先にポリイミド樹脂膜9に窓9aを
開設して金突起電極の形成領域を限定しているので、金
メッキの等方成長による金メッキ層の横方向への拡大を
抑制することができ、金突起電極3の平面寸法を低減し
て半導体装置の微細化を図ることもできる。
In addition, in this method, since the window 9a is first opened in the polyimide resin film 9 to limit the formation area of the gold protrusion electrode, it is possible to suppress the horizontal expansion of the gold plating layer due to isotropic growth of the gold plating. It is also possible to miniaturize the semiconductor device by reducing the planar dimension of the gold protrusion electrode 3.

ここで、メッキ時の電流路としての白金膜やアルミニウ
ム膜には他の金属を使用してもよく、また突起電極は金
以外の金属を使用することができるのは勿論である。
It goes without saying that other metals may be used for the platinum film and aluminum film that serve as current paths during plating, and metals other than gold may be used for the protruding electrodes.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、メッキ時の電流路として
の金属導電膜を形成した後、この金属導電膜上に保護膜
を形成し、かつその金属突起電極を形成する領域に開口
を形成した上でメッキ法により金属突起電極を形成し、
その後に前記金属導電膜の不要部分をエツチング除去す
る工程を含むので、金属突起電極を形成した後に保護膜
をエツチングする工程は不要であり、金属突起電極の表
層部にエツチング残渣が生じることを防止でき、金属突
起電極における機械的及び電気向な接続の信頼性を向上
できる。また、保護膜に開口を設けた上でメッキ法によ
る金属突起電極の形成を行っているので、金属突起電極
の横方向の寸法拡大を防止してその微細化を図り、半導
体装置の高集積化を図ることもできる。
As explained above, in the present invention, after forming a metal conductive film as a current path during plating, a protective film is formed on this metal conductive film, and an opening is formed in the area where the metal protrusion electrode is to be formed. A metal protrusion electrode is formed on the top by plating method,
After that, a step of etching away unnecessary parts of the metal conductive film is included, so there is no need to etch the protective film after forming the metal protrusion electrode, and it is possible to prevent etching residue from forming on the surface layer of the metal protrusion electrode. The mechanical and electrical connection reliability of the metal protrusion electrode can be improved. In addition, since the metal protrusion electrodes are formed by plating after providing an opening in the protective film, it is possible to prevent the lateral dimension of the metal protrusion electrodes from expanding and to miniaturize the metal protrusion electrodes, allowing for highly integrated semiconductor devices. It is also possible to aim for

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法により形成する半導体装置の平面図
、第2図(a)〜(g)は本発明方法を工程順に示す図
で、第1図のAA線に沿う断面図、第3図は製造工程途
中における平面図である。 1・・・半導体基板、2・・・ダイシングライン領域、
3・・・金属(金)突起電極、4・・・絶縁膜、5・・
・白金膜(金属膜)、6・・・アルミニウム、7・・・
酸化アルミニウム層、8・・・フォトレジストマスク、
9・・・保護膜(ポリイミド樹脂膜)、9a、9b・・
・窓、10・・・フォトレジスト、。 、、、/−−51゛ 代理人 弁理士  鈴 木 章 芙ト□1〜、リ一、− 第2図 第3図
FIG. 1 is a plan view of a semiconductor device formed by the method of the present invention, and FIGS. The figure is a plan view in the middle of the manufacturing process. 1... Semiconductor substrate, 2... Dicing line area,
3... Metal (gold) protruding electrode, 4... Insulating film, 5...
・Platinum film (metal film), 6...aluminum, 7...
aluminum oxide layer, 8... photoresist mask,
9... Protective film (polyimide resin film), 9a, 9b...
・Window, 10...Photoresist. ,,,/--51゛Agent Patent Attorney Akira Suzuki Futo□1~,Liichi,- Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上の金属突起電極形成領域を含む領域
にメッキ時の電流路としての金属導電膜を形成する工程
と、この金属導電膜上に保護膜を形成する工程と、この
保護膜の金属突起電極を形成する領域に開口を形成する
工程と、この開口内に露呈された前記金属導電膜上にメ
ッキ法により金属突起電極を形成する工程と、その後に
前記金属導電膜の不要部分をエッチング除去する工程を
含むことを特徴とする半導体装置の製造方法。
(1) A process of forming a metal conductive film as a current path during plating in an area including a metal protrusion electrode formation area on a semiconductor substrate, a process of forming a protective film on this metal conductive film, and a process of forming a protective film on this metal conductive film. A step of forming an opening in a region where a metal protrusion electrode is to be formed, a step of forming a metal protrusion electrode by a plating method on the metal conductive film exposed in the opening, and then removing an unnecessary portion of the metal conductive film. A method for manufacturing a semiconductor device, comprising a step of removing by etching.
(2)金属導電膜は金属突起電極形成領域に対応して夫
々独立して形成した金属膜と、これらの金属膜を相互に
電気接続する金属膜とで構成し、金属突起電極形成後に
は相互に電気接続する金属膜の一部をエッチング除去し
てなる特許請求の範囲第1項記載の半導体装置の製造方
法。
(2) The metal conductive film is composed of metal films formed independently corresponding to the metal protrusion electrode formation areas, and a metal film that electrically connects these metal films to each other. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a part of the metal film that is electrically connected to the semiconductor device is etched away.
JP12324586A 1986-05-30 1986-05-30 Manufacture of semiconductor device Pending JPS62281356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12324586A JPS62281356A (en) 1986-05-30 1986-05-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12324586A JPS62281356A (en) 1986-05-30 1986-05-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62281356A true JPS62281356A (en) 1987-12-07

Family

ID=14855797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12324586A Pending JPS62281356A (en) 1986-05-30 1986-05-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62281356A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187948A (en) * 1988-01-22 1989-07-27 Nec Corp Semiconductor device
JP2009004744A (en) * 2007-06-20 2009-01-08 Samsung Electro Mech Co Ltd Printed-circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187948A (en) * 1988-01-22 1989-07-27 Nec Corp Semiconductor device
JP2009004744A (en) * 2007-06-20 2009-01-08 Samsung Electro Mech Co Ltd Printed-circuit board
US8080741B2 (en) 2007-06-20 2011-12-20 Samsung Electro-Mechanics Co., Ltd. Printed circuit board

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