KR0138008B1 - Fabrication method of metal contact in semiconductor device - Google Patents
Fabrication method of metal contact in semiconductor deviceInfo
- Publication number
- KR0138008B1 KR0138008B1 KR1019930027229A KR930027229A KR0138008B1 KR 0138008 B1 KR0138008 B1 KR 0138008B1 KR 1019930027229 A KR1019930027229 A KR 1019930027229A KR 930027229 A KR930027229 A KR 930027229A KR 0138008 B1 KR0138008 B1 KR 0138008B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- metal layer
- layer
- forming
- film
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 45
- 239000002184 metal Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title abstract description 8
- 238000004519 manufacturing process Methods 0.000 title 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 15
- 239000010937 tungsten Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000002401 inhibitory effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000009036 growth inhibition Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 41
- 238000001465 metallisation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 금속 배선층 형성방법에 관한 것으로, 반도체소자의 광역적 단차를 성장억제용으로 산화막을 이용하여 선택적텅스텐을 단차가 깊은 곳에서만 선택적으로 증착시킨 후, 금속배선층을 형성함으로써 금속배선층을 형성하는 사진, 식각공정의 공정마진을 확보할 수 있어 반도체소자의 수율 및 신뢰성을 증가시키는 기술이다.The present invention relates to a method for forming a metal wiring layer, wherein the selective step of selectively depositing tungsten only in a deep step by using an oxide film for the growth inhibition of the semiconductor device to form a metal wiring layer by forming a metal wiring layer It is a technology that increases the yield and reliability of semiconductor devices by securing process margins for photo and etching processes.
Description
제 1 도 내지 제 4 도는 본 발명에 의한 금속배선층 형성공정을 도시한 단면도.1 to 4 are cross-sectional views showing a metal wiring layer forming process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:실리콘 기판2:활성층1: Silicon Substrate 2: Active Layer
3:소자분리막4:셀부3: device isolation membrane 4: cell section
5:주변회로부6:콘택홀5: peripheral circuit part 6: contact hole
7:장벽금속층8:금속층7: barrier metal layer 8: metal layer
9:산화막10:선택적텅스텐9: oxide film 10: selective tungsten
11:감광막패턴12:산화막패턴11: photosensitive film pattern 12: oxide film pattern
본 발명은 금속배선층 형성방법에 관한 것으로, 반도체소자의 광역적 단차를 성장억제용으로 산화막을 이용하여 선택적텅스텐을 단차가 깊은 곳에만 선택적으로 증착시킨 후, 금속배선층을 형성함으로써 금속배선층을 형성하는 사진, 식각공정의 공정마진을 확보할 수 있게 반도체소자의 수율 및 신뢰성을 증가시키는 기술이다.The present invention relates to a method for forming a metal wiring layer, wherein the selective step of selectively depositing tungsten only in a deep step by using an oxide film for growth inhibition of a semiconductor device to form a metal wiring layer by forming a metal wiring layer. It is a technology to increase the yield and reliability of the semiconductor device to ensure the process margin of the etching process.
종래기술에 의한 금속배선층 형성공정은 몇가지 어려움이 있다. 사진 공정시, 단차가 낮은 곳을 기준으로 노광시키면 단차가 높은 곳에서 과도한 노광으로 감광막의 손실이 크고, 단차가 높은 곳을 기준으로 노광시키면 단차가 낮은 곳에서는 감광막패턴이 형성되지 않고 노광부족으로 붙어 버리는 등과같은 문제점이 있고 상기 금속배선층 형성은 후속공정에 속하기 때문에 단차의 형향을 심각하게 받는다. 그리고, 금속층은 전원공급의 역할을 하기 때문에 저항값을 낮게하기위해 반도체소자의 다른층보다 두꺼울 수 밖에 없으므로 높은 단차비는 필연적이다. 그래서, 금속층 식각시 공정이 아주 어렵다. 한편, 금속층과 감광막의 식각선택비는 통상의 다른층, 예를들어 산화막, 질화막 또는 다결정실리콘막과 감광막의 식각선택비 보다 현저하게 낮은 1.5 : 1 정도이다. 그러므로 금속층 모양을 손실없이 형성하려고 하면 충분한 두께의 감광막이 필요하고, 그러면 감광막의 두께 증가로 인하여 사진공정의 해상력(resolution)이 금속히 감소하여 패턴형성이 불가능해진다.The metallization layer forming process according to the prior art has some difficulties. In the photographic process, if the exposure is based on the low step, the photoresist film is lost due to excessive exposure at the high step. If the exposure is taken based on the high step, the photoresist pattern is not formed at the low step. There is a problem such as sticking, and since the metal wiring layer formation belongs to a subsequent process, the shape of the step is seriously affected. In addition, since the metal layer serves as a power supply, a high step ratio is inevitable because the metal layer must be thicker than other layers of the semiconductor device in order to lower the resistance value. Therefore, the process is very difficult when etching the metal layer. On the other hand, the etching selectivity of the metal layer and the photosensitive film is about 1.5: 1, which is significantly lower than the etching selectivity of other conventional layers, for example, an oxide film, a nitride film, or a polysilicon film and a photosensitive film. Therefore, if the shape of the metal layer is to be formed without loss, a photosensitive film having a sufficient thickness is required. Then, the resolution of the photographing process is reduced due to the increase in the thickness of the photosensitive film, thereby making pattern formation impossible.
따라서, 본 발명에서는 셀부와 주변회로부의 수직높이, 즉 광역단차의 1 / 2 지점에서부터 단차가 높은 셀부로 산화막 또는 질화막패턴을 사진, 식각공정으로 형성한 다음, 금속배선층이 노출된 곳에만 선택적텅스텐을 증착시켜 단차를 감소시키고 후속공정을 실시함으로써 금속배선층을 형성하여 소자의 신뢰성 및 수율을 높이는데 그 목적이 있다.Therefore, in the present invention, the oxide layer or nitride pattern is formed by photolithography and etching process from the vertical height of the cell portion and the peripheral circuit portion, that is, the one-half point of the regional step, by the photolithography process. The purpose is to increase the reliability and yield of the device by forming a metallization layer by reducing the step by depositing and performing a subsequent process.
이상의 목적을 달성하기위한 본 발명의 특징은, 실리콘기판의 상부에 소자분리막 및 콘택홀을 형성하고 그상부에 기판과의 접착성을 양호하게 하는 장벽금속층과 금속층을 증착하는 고정과, 금속층의 상부에 산화막을 도포하고 셀부와 주변회로부의 광역단차의 1 / 2 되는 곳에서 산화막을 사진, 식각공정으로 형성하는 공정과, 상기 산화막을 성장억제층으로 이용하여 선택적텅스텐을 토출된 금속층 상부에 증착시키는 공정과, 상기 상부구조전체에 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로 하여 먼저 셀부의 산화막을 건식식각하여 산화막패턴을 형성한 다음, 주변회로부의 선택적텅스텐을 식각하는 공정과, 상기 산화막을 마스크로 하여 금속층 및 장벽금속층을 식각하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above object is a fixing for depositing a barrier metal layer and a metal layer to form a device isolation film and a contact hole on top of a silicon substrate and to improve adhesion to the substrate thereon, and the top of the metal layer Forming an oxide film by a photo-etching process at a place where 1/2 of the wide-area step of the cell part and the peripheral circuit part is applied to the oxide film, and depositing selective tungsten on the discharged metal layer by using the oxide film as a growth inhibitory layer. Forming a photoresist pattern on the entire upper structure; first, by dry etching the oxide film of the cell part using the photoresist pattern as a mask, forming an oxide film pattern, and then etching the selective tungsten of the peripheral circuit part; And etching the metal layer and the barrier metal layer using the oxide film as a mask.
이하, 첨부된 도면을 참고로하여 본 발명을 설명하기로 한다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
제1도 내지 제4도는 본 발명에 의한 금속배선층 형성공정을 도시한 단면도이다.1 to 4 are cross-sectional views showing the metal wiring layer forming process according to the present invention.
제1도는 반도체기판(1) 상부의 셀(cell) 부(주변회로(periphery) 부(5)에 소자분리막(3)을 형성하고 금속배선층 콘택홀(6)을 충입한 다음, 전체상부구조에 접착층 역할을 하는 장벽금속층(7)과 금속층(8)을 스퍼터링(sputtering) 방법으로 증착하고 산화막 또는 질화막(9)을 증착한 후, 광역단차의 1 / 2 지점부터 단차의 상부인 셀부전체에 사진식각공정으로 산화막 또는 질화막(9)을 남긴 것을 도시한 단면도이다. 상기 산화막(9)은 플라즈마 유도 화학기상증착(PECVD : Plasma Enhancement Chemical Vapor Deposition) 방법으로 증착하며, 상기 금속층(8)은 알루미늄(Al), 구리(Cu) 및 몰리브덴(Mo) 등을 사용하며 산화막(9)은 질화막을 사용할 수도 있다. 그리고, 장벽금속층(7)은 Ti, TiN 또는 Ti / TiN 층을 사용하여 스퍼터링 방법으로 증착한다. 여기서, 산화막(9)을 광역단차의 1 / 2 되는 곳에 형성한 이유는 선택적텅스텐(11) 증착시 종심방향으로 성장함과 동시에 횡심방향으로도 같은 두께만큼 성장함으로써 셀부(4)의 끝부분, 즉 셀부(4)에서 주변회로부(5)로 단차가 생기기 직전의 셀부(4)에서 텅스텐의 횡심방향성장을 이용하여 평탄화되도록하기 위해서이다.FIG. 1 shows that the device isolation film 3 is formed in the cell portion (periphery portion 5) on the upper portion of the semiconductor substrate 1, the metal wiring layer contact hole 6 is filled, and then the entire upper structure is formed. After depositing the barrier metal layer 7 and the metal layer 8 serving as an adhesive layer by the sputtering method and depositing the oxide film or the nitride film 9, the photo is placed on the cell subsidiary body which is the upper part of the step from 1/2 of the wide step. It is a sectional view which shows the oxide film or the nitride film 9 by the etching process, The oxide film 9 is deposited by the Plasma Enhancement Chemical Vapor Deposition (PECVD) method, The metal layer 8 is aluminum ( Al), copper (Cu), molybdenum (Mo), and the like, and an oxide film 9 may be a nitride film, and the barrier metal layer 7 is deposited by a sputtering method using a Ti, TiN, or Ti / TiN layer. Here, the oxide film 9 is placed at one half of the wide area difference. The reason for this is that when the selective tungsten 11 is deposited, it grows in the longitudinal direction and at the same thickness in the transverse direction, so that the step of the cell portion 4, i.e., just before the step is generated from the cell portion 4 to the peripheral circuit portion 5, is formed. This is to make the cell portion 4 planarized using lateral growth of tungsten.
제2도는 광역단차를 제거하기 위하여 선택적텅스텐(11)을 단차가 낮은 주변회로부(5)에만 증착하여 평탄화시킨 것을 도시한 단면도이다.2 is a cross-sectional view showing that the selective tungsten 11 is deposited only on the peripheral circuit portion 5 having a low step level in order to remove the wide step.
제3도는 금속배선층을 형성하기위한 감광막을 도포한 후, 사진공정으로 감광막패턴(13)을 형성한 것을 도시한 단면도이다.3 is a cross-sectional view showing that the photosensitive film pattern 13 is formed by a photo process after coating the photosensitive film for forming the metal wiring layer.
제4도는 상기 감광막패턴(13)을 마스크로하여 셀부(4)에 있는 산화막(9)을 식각하여 산화막패턴(19)을 형성한 다음, 주변회로부(5)에 있는 선택적텅스텐(11)을 식각하고 금속층(8)과 장벽금속층(7)을 차례로 건식식각하여 금속배선층을 형성한 것을 도시한 단면도이다. 여기서, 산화막패턴(19)은 금속층(8) 식각시 감광막패턴(13)과 함께 마스크 역할을 한다.4 shows that the oxide film 9 in the cell part 4 is etched using the photoresist pattern 13 as a mask to form the oxide film pattern 19, and then the selective tungsten 11 in the peripheral circuit part 5 is etched. And a metal wiring layer formed by sequentially dry etching the metal layer 8 and the barrier metal layer 7 in sequence. Here, the oxide layer pattern 19 serves as a mask together with the photoresist layer pattern 13 when the metal layer 8 is etched.
상기한 본 발명에 의하면, 금속배선층 형성시 단차로 인하여 발생되는 문제점을 해결하기 위하여 산화막 및 선택적텅스텐을 사용함으로써 단차를 완화시킨 다음, 금속배선층을 형성함으로써 식각공정마진을 향상시켜 반도체소자의 수율 및 신뢰성을 증가시킬 수 있다.According to the present invention described above, in order to solve the problems caused by the step difference in forming the metal wiring layer, by using an oxide film and selective tungsten to reduce the step, by forming a metal wiring layer to improve the etching process margin to improve the yield of the semiconductor device and It can increase the reliability.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930027229A KR0138008B1 (en) | 1993-12-10 | 1993-12-10 | Fabrication method of metal contact in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930027229A KR0138008B1 (en) | 1993-12-10 | 1993-12-10 | Fabrication method of metal contact in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950021285A KR950021285A (en) | 1995-07-26 |
| KR0138008B1 true KR0138008B1 (en) | 1998-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930027229A KR0138008B1 (en) | 1993-12-10 | 1993-12-10 | Fabrication method of metal contact in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100457407B1 (en) * | 1997-12-30 | 2005-02-23 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to improve electrical characteristic of metal interconnection |
-
1993
- 1993-12-10 KR KR1019930027229A patent/KR0138008B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100457407B1 (en) * | 1997-12-30 | 2005-02-23 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to improve electrical characteristic of metal interconnection |
Also Published As
| Publication number | Publication date |
|---|---|
| KR950021285A (en) | 1995-07-26 |
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