KR0140483B1 - Manufacture method of wiring metal in semiconductor device - Google Patents
Manufacture method of wiring metal in semiconductor deviceInfo
- Publication number
- KR0140483B1 KR0140483B1 KR1019940010998A KR19940010998A KR0140483B1 KR 0140483 B1 KR0140483 B1 KR 0140483B1 KR 1019940010998 A KR1019940010998 A KR 1019940010998A KR 19940010998 A KR19940010998 A KR 19940010998A KR 0140483 B1 KR0140483 B1 KR 0140483B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- semiconductor device
- contact hole
- tungsten film
- tungsten
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 23
- 239000002184 metal Substances 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 26
- 229910052721 tungsten Inorganic materials 0.000 claims description 25
- 239000010937 tungsten Substances 0.000 claims description 25
- 229910052782 aluminium Inorganic materials 0.000 claims description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000000460 chlorine Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 고집적 반도체소자의 금속배선 제조방법에 관한 것으로, 고집적 반도체소자의 콘택홀에 금속층을 충입하되 보이드가 발생되지 않도록 하고 면저항을 줄여서 반도체소자의 신뢰성과 수율을 증대시킬 수 있는 금속배선 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a metal wiring of a highly integrated semiconductor device, but filling the metal layer into the contact hole of the highly integrated semiconductor device to prevent voids and to reduce the sheet resistance to increase the reliability and yield of the semiconductor device. It is about.
Description
제1도 내지 제4도는 본 발명에 의해 반도체소자의 금속배선을 형성하는 단계를 도시한 단면도.1 to 4 are cross-sectional views showing the step of forming a metal wiring of a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:실리콘기판 2:확산영역1: Silicon substrate 2: Diffusion area
3:소자분리절연막 4:절연막3: device isolation insulating film 4: insulating film
6:콘택홀 7:텅스텐막6: contact hole 7: tungsten film
8:알루미늄막 9:감광막패턴8: Aluminum film 9: Photoresist pattern
본 발명은 고집적 반도체소자의 금속배선 제조방법에 관한 것으로, 특히 64메가 이상의 반도체소자의 콘택홀에 금속층을 충입하되 보이드가 발생되지 않도록 하고 면저항을 줄여서 반도체소자의 신뢰성과 수율을 증대시킬 수 있는 금속배선 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a metal wiring of a highly integrated semiconductor device, in particular, a metal layer is filled into the contact hole of a semiconductor device of more than 64 megabytes to prevent voids and to reduce the sheet resistance to increase the reliability and yield of the semiconductor device It relates to a wiring manufacturing method.
최근에 반도체소자의 집적도가 높아짐에 따라 단위셀의 면적이 감소하게 되고, 이에 따라 상부의 도전층을 콘택홀을 통해 하부의 도전층에 콘택하는 기술이 대두되었다.Recently, as the degree of integration of semiconductor devices increases, the area of a unit cell decreases. Accordingly, a technique of contacting an upper conductive layer to a lower conductive layer through a contact hole has emerged.
종래 기술에 의해 하부층에 콘택되는 금속배선 형성방법을 설명하면 다음과 같다.Referring to the metal wiring forming method of contacting the lower layer by the prior art as follows.
첫째는 블랭킷 텅스텐만을 이용하여 금속배선을 형성하면 콘택홀에 보이드없이 금속을 충입할 수 있으나 금속배선의 면저항이 증가하여 회로 설계시 심각한 장애요인으로 작용한다.First, if the metal wiring is formed using only blanket tungsten, the metal can be filled without voids in the contact hole, but the sheet resistance of the metal wiring increases, which is a serious obstacle in designing the circuit.
둘째는 알루미늄을 사용하여 금속배선을 형성하면 낮은 면저항을 얻을수 있으나 금속배선 콘택홀에 보이드(void)가 없이 금속을 충입하기가 불가능하다.Second, if the metal wiring is formed using aluminum, low sheet resistance can be obtained, but it is impossible to fill the metal without a void in the metal wiring contact hole.
셋째는 블랭킷 텅스텐으로 콘택홀에 금속을 충입한 후 에치백 공정으로 콘택홀 상부에 있는 텅스텐을 식각한 후 알루미늄으로 스퍼터링하여 금속배선으로 형성하는 방법이 있으나 단차 부위에서 텅스텐 잔여물이 남을 수 있고 에치백공정에서 파티클이 발생할 수 있는 단점이 있다.Thirdly, blanket tungsten is used to fill metal into the contact hole, and then the etchback process is used to etch the tungsten on the upper part of the contact hole and sputter with aluminum to form metal wiring. However, tungsten residue may remain at the stepped area. There is a drawback that particles may occur in the tooth back process.
따라서 본 발명은 상기한 문제점을 해결하기 위하여 텅스텐을 콘택홀에 증착한 다음, 알루미늄을 증착하고 마스크를 이용하여 금속배선을 형성하는 반도체소자의 금속배선 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing metal wiring of a semiconductor device in which tungsten is deposited in a contact hole and then aluminum is deposited and a metal wiring is formed using a mask to solve the above problems.
상기 목적을 달성하기 위해 본 발명에 의한 반도체소자의 금속배선 제조방법은 셀지역과 주변회로지역을 갖는 실리콘기판상에 소자분리절연막을 형성하고, 예정된 소자들을 셀 지역에 형성하는 단계와,In order to achieve the above object, a method of manufacturing a metal wiring of a semiconductor device according to the present invention includes forming a device isolation insulating film on a silicon substrate having a cell region and a peripheral circuit region, and forming predetermined elements in the cell region;
전체구조 상부에 절연막을 도포하고 주변회로지역의 절연막의 일정부분을 제거하여 실리콘기판에 형성된 확산영역이 노출된 콘택홀을 형성하는 단계와,Forming a contact hole exposing the diffusion region formed on the silicon substrate by applying an insulating film over the entire structure and removing a portion of the insulating film in the peripheral circuit area;
블랭킷 텅스텐막으로 상기 콘택홀을 충입한 후, 그 상부에 알루미늄막을 예정된 두께로 증착하고 금속배선 마스크용 감광막패턴을 형성하는 단계와,Filling the contact hole with a blanket tungsten film, depositing an aluminum film thereon to a predetermined thickness, and forming a photoresist pattern for a metallization mask;
노출된 알루미늄막을 식각하여 알루미늄막패턴을 형성하는 단계와,Etching the exposed aluminum film to form an aluminum film pattern;
노출된 텅스텐막을 식각하여 텅스텐막패턴을 형성하고 남아있는 상기 감광막패턴을 제거하는 단계로 이루어지는 것을 특징으로 한다.Etching the exposed tungsten film to form a tungsten film pattern and removing the remaining photosensitive film pattern.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1도 내지 제4도는 본 발명에 의해 반도체소자의 금속배선 제조단계를 도시한 단면도이다.1 to 4 are cross-sectional views showing a metallization manufacturing step of a semiconductor device according to the present invention.
제1도는 셀지역과 주변회로지역을 갖는 실리콘기판(1)상에 소자분리절연막(3)과 확산영역(2)을 형성하고, 예정된 소자를 셀지역에 형성하고(도시안됨), 전체구조상부에 절연막(4)을 도포한 후, 주변회로지역의 절연막(4)의 일정부분을 제거하고 실리콘기판(1)에 형성된 확산영역(2)이 노출된 콘택홀(6)을 형성하고, 블랭킷 텅스텐막(7)으로 상기 콘택홀(6)을 충입한다. 이때 상기 텅스텐막(7)의 두께는 콘택홀의 크기와 텅스텐막의 스텝커버리지를 고려하여 콘택홀(6)을 완전히 메울 수 잇으면 된다. 또한 상기 텅스텐막(7)을 증착하기 전에 글루층(GLUE LAYER)으로 Ti, TiN 또는 Ti/TiN층을 형성할 수도 있다.1 shows a device isolation insulating film 3 and a diffusion region 2 on a silicon substrate 1 having a cell region and a peripheral circuit region, a predetermined element is formed in a cell region (not shown), and the overall structure After the insulating film 4 was applied to the film, a portion of the insulating film 4 in the peripheral circuit region was removed to form a contact hole 6 in which the diffusion region 2 formed in the silicon substrate 1 was exposed. The contact hole 6 is filled into the film 7. In this case, the thickness of the tungsten film 7 may completely fill the contact hole 6 in consideration of the size of the contact hole and the step coverage of the tungsten film. In addition, before depositing the tungsten film 7, a Ti, TiN or Ti / TiN layer may be formed of a glue layer.
그 다음 상기 구조의 전표면에 알루미늄막(8)을 종래 두께의 절반 두께로 증착하고 금속배선 식각 마스크용 감광막패턴(9)을 형성한 단면도이다. 상기와 같이 텅스텐막(7)을 콘택홀에 매립할 경우 보이드가 발생되지 않으며, 그 상부에 알루미늄막(8)을 증착함으로써 면저항을 낮출 수 있다.Next, the aluminum film 8 is deposited on the entire surface of the structure to a half thickness of the conventional thickness, and a photosensitive film pattern 9 for a metallization etch mask is formed. As described above, when the tungsten film 7 is embedded in the contact hole, no void is generated, and the sheet resistance can be lowered by depositing the aluminum film 8 thereon.
제2도는 상기 공정후 노출된 알루미늄막(8)을 Cl 가스를 이용하여 식각함으로써 알루미늄막패턴(8')을 형성한 단면도이다. 여기서 노출되는 텅스텐막(7)은 염소(Cl) 가스로 제거가 되지 않음으로 식각정지층으로 이용할 수 있다.2 is a cross-sectional view of the aluminum film pattern 8 ′ formed by etching the exposed aluminum film 8 using Cl gas. The exposed tungsten film 7 may not be removed by chlorine (Cl) gas, and thus may be used as an etch stop layer.
제3도는 계속하여 노출된 텅스텐막(7)을 불소(F) 가스를 이용한 식각공정으로 감광막패턴(9)과 하드마스크 역활을 하는 알루미늄막패턴(8')을 식각정지층으로 이용하여 텅스텐막패턴(7')을 형성한 단면도로소, 상기 F가스에서는 상기 알루미늄막패턴(8')은 거의 식각되지 않아 알루미늄패턴(8')의 측벽을 보호할 수 있다.FIG. 3 shows the tungsten film 7 using the exposed tungsten film 7 as an etch stop layer using an etch stop layer using an aluminum film pattern 8 ′ which acts as a hard mask and a photosensitive film pattern 9 in an etching process using fluorine (F) gas. In the cross-sectional view of the pattern 7 ', the aluminum film pattern 8' is hardly etched in the F gas, thereby protecting the sidewall of the aluminum pattern 8 '.
제4도는 상기의 남아있는 감광막패턴(9)을 제거한 상태의 단면도이다.4 is a cross-sectional view of a state in which the remaining photosensitive film pattern 9 is removed.
상기한 본 발명에 의하면 면저항이 증대되는 것을 방지하고 콘택홀에 보이드가 발생되는 것을 해결할 수 있으며 텅스텐 증착후에 텅스텐을 에치백하지 않고 알루미늄막을 얇게 스퍼터링한 후 감광막패턴을 이용하여 금속배선을 형성함으로 파티클 발생을 줄일 수 있다.According to the present invention, it is possible to prevent the sheet resistance from increasing and to solve the generation of voids in the contact holes, and after forming tungsten by sputtering the aluminum film thinly without etching tungsten after tungsten deposition, a metal wiring is formed using a photoresist pattern. It can reduce the occurrence.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940010998A KR0140483B1 (en) | 1994-05-20 | 1994-05-20 | Manufacture method of wiring metal in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940010998A KR0140483B1 (en) | 1994-05-20 | 1994-05-20 | Manufacture method of wiring metal in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950034439A KR950034439A (en) | 1995-12-28 |
| KR0140483B1 true KR0140483B1 (en) | 1998-07-15 |
Family
ID=19383445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940010998A KR0140483B1 (en) | 1994-05-20 | 1994-05-20 | Manufacture method of wiring metal in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0140483B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100457407B1 (en) * | 1997-12-30 | 2005-02-23 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to improve electrical characteristic of metal interconnection |
-
1994
- 1994-05-20 KR KR1019940010998A patent/KR0140483B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100457407B1 (en) * | 1997-12-30 | 2005-02-23 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to improve electrical characteristic of metal interconnection |
Also Published As
| Publication number | Publication date |
|---|---|
| KR950034439A (en) | 1995-12-28 |
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