KR100187677B1 - Forming method of diffusion prevention layer - Google Patents
Forming method of diffusion prevention layer Download PDFInfo
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- KR100187677B1 KR100187677B1 KR1019950012707A KR19950012707A KR100187677B1 KR 100187677 B1 KR100187677 B1 KR 100187677B1 KR 1019950012707 A KR1019950012707 A KR 1019950012707A KR 19950012707 A KR19950012707 A KR 19950012707A KR 100187677 B1 KR100187677 B1 KR 100187677B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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Abstract
본 발명은 반도체 소자의 확산방지층 형성방법이 개시된다.The present invention discloses a method for forming a diffusion barrier layer of a semiconductor device.
본 발명은 알루미늄 이온과 실리콘 이온이 반응하는 것을 확실하게 방지하기 위하여 충분한 두께를 필요로 하는 콘택홀내부에는 제1 및 2확산방지층으로 이중층이 되게하고, 콘택홀의 단차비 증가를 최소한으로 하기 위하여 얇은 두께를 필요로 하는 콘택홀이외의 부분에는 제2확산방지층만으로 단층이 되게한다.The present invention provides a double layer with first and second diffusion barrier layers inside a contact hole that requires a sufficient thickness in order to reliably prevent aluminum ions and silicon ions from reacting, and to minimize the increase in the step difference ratio of the contact holes. In portions other than the contact holes requiring thickness, only the second diffusion barrier layer becomes a single layer.
따라서, 본 발명은 콘택홀이외의 부분에 형성되는 확산방지층의 두께를 증가시키지 않으면서 콘택홀 내부의 확산방지층을 두껍게 형성하므로써, 고온의 알루미늄 합금 증착공정시 알루미늄 이온과 접합부의 실리콘 이온이 상호 반응되는 것을 방지하여 스파킹(spiking)등을 효과적으로 방지할 수 있고, 콘택홀의 다차비 증가를 최소화하여 금속배선공정을 용이하게 할 수 있다.Therefore, the present invention forms a thick diffusion barrier layer inside the contact hole without increasing the thickness of the diffusion barrier layer formed at the portion other than the contact hole, so that the silicon ions react with each other during the high temperature aluminum alloy deposition process. It is possible to effectively prevent sparking (spiking), etc., and to facilitate the metal wiring process by minimizing the increase in the dacha ratio of the contact hole.
Description
제1a 내지 제1f도는 본 발명에 의한 확산방지층 형성방법을 설명하기 위해 도시한 소자의 단면도1A to 1F are cross-sectional views of the device shown for explaining the method for forming the diffusion barrier layer according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 접합부1 silicon substrate 2 junction
3 : 층간 절연막 4 : 콘택홀3: interlayer insulating film 4: contact hole
5a : 제1 확산방지층 5b : 제2 확산방지층5a: first diffusion barrier layer 5b: second diffusion barrier layer
5 : 확산방지층 6 : 포토레지스트 패턴5: diffusion barrier layer 6: photoresist pattern
7 : 금속배선7: metal wiring
본 발명은 반도체 소자의 확산방지층 형성방법에 관한 것으로, 특히 금속배선 재료로 알루미늄 합금을 사용할 때, 접합부에서 알루미늄 이온과 실리콘 이온이 상호 반응하는 것을 방지하기 위해 사용되고 있는 확산방지층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a diffusion barrier layer of a semiconductor device, and more particularly, to a method of forming a diffusion barrier layer which is used to prevent an interaction between aluminum ions and silicon ions at a junction when an aluminum alloy is used as a metal wiring material.
일반적으로, 반도체 소자가 고집적화 됨에 따라 콘택홀은 크기가 감소되고 단차비가 증가된다. 이러한 콘택홀을 통해 접합부에 접속되는 금속배선의 재료로 알루미늄 합금을 사용할 경우, 알루미늄 합금이 콘택홀의 저부에서 나쁜 층덮힘율로 인하여 이의 개선을 위해서는 고온에서의 공정이 필수적이다. 이 경우 알루니늄과 실리콘 이온이 확산하여 상호 반응하는 것을 방지하기 위하여 확산방지층을 사용하게 되는데, 고온에서 확산방지역할을 충분히 해주기 위해서는 어느 정도이상의 두께가 필요하다. 그러나 확산방지층의 증착방식을 물리적 증착방법(Physical Vapor Deposition; PVD)으로 할 경우 콘택홀의 저부와 그 이외의 부분과는 상당한 두께의 차이를 가져온다. 이러한 문제점으로 인하여 콘택홀의 저부에 원하는 두께의 확산방지층을 형성하기 위하여 증착공정을 실시할 경우 콘택홀 바깥부분의 확산방지층이 필요이상의 두께로 형성되어 후속공정인 알루미늄 합금 증착공정시의 실제 단차비를 증가시키는 결과를 초래하게 되며, 이로인하여 알루미늄 합금증착시의 층덮힘을 더욱 악화시키게 된다.In general, as semiconductor devices are highly integrated, the contact holes are reduced in size and the stepped ratio is increased. When the aluminum alloy is used as the material for the metal wiring connected to the joint through the contact hole, the process at high temperature is essential for the improvement of the aluminum alloy due to the bad layer coverage at the bottom of the contact hole. In this case, a diffusion barrier layer is used to prevent the aluminium and silicon ions from diffusing and reacting with each other. In order to sufficiently diffuse the diffusion barrier at a high temperature, a certain thickness or more is required. However, if the deposition method of the diffusion barrier layer is a physical vapor deposition method (PVD), there is a significant thickness difference between the bottom of the contact hole and the other parts. Due to these problems, when the deposition process is performed to form a diffusion barrier layer having a desired thickness on the bottom of the contact hole, the diffusion barrier layer outside the contact hole is formed to have a thickness greater than necessary, thereby reducing the actual step ratio in the subsequent aluminum alloy deposition process. This results in an increase, which further exacerbates the layer covering during aluminum alloy deposition.
따라서, 본 발명은 확산방지층 형성공정을 2단계로 실시하되, 1차 확산방지층 형성공정후에 마스크공정을 통하여 콘택홀 내에만 확산방지층이 잔류되게 한 다음 2차 확산방지층 형성공정을 실시하므로써, 콘택홀 이외의 부분에서는 종래와 같은 두께로 확산방지층을 형성하면서 콘택홀부분에는 충분한 두께의 확산방지층을 형성하여 상기한 문제점을 해결할 수 있는 반도체 소자의 확산방지층 형성방법을 제공함에 그 목적이 있다.Therefore, in the present invention, the diffusion barrier layer forming process is performed in two stages, but after the primary diffusion barrier layer forming process, the diffusion barrier layer remains only in the contact hole through the mask process, and then the second diffusion barrier layer forming process is performed. In other parts, the purpose of the present invention is to provide a method of forming a diffusion barrier layer of a semiconductor device which can solve the above problems by forming a diffusion barrier layer having a thickness as in the prior art while forming a diffusion barrier layer having a sufficient thickness in the contact hole portion.
이러한 목적을 달성하기 위한 본 발명의 확산방지층 형성방법은실리콘 기판상에 층간 절연막을 형성한 후, 상기 층간 절연막의 소정부분을 식각하여 접합부가 노출되는 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 상기 층간 절연막상에 제1 확산방지층을 형성하는 단계와, 상기 콘택홀 부분의 상기 제1 확산방지층상에 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 마스크로 하여 상게 제1 확산방지층의 노출된 부분을 제거하므로, 이로 인하여 상기 콘택홀내에만 상기 제1 확산방지층이 잔류도는 단계와, 상기 포토레지스트 패턴을 제거한 후, 상기 콘택홀내부에 잔류된 상기 제1 확산방지층을 포함한 상기 층간 절연막상에 제2 확산방지층을 형성하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming a diffusion barrier layer, after forming an interlayer insulating film on a silicon substrate, etching a predetermined portion of the interlayer insulating film to form a contact hole through which a junction is exposed, and forming the contact hole. Forming a first diffusion barrier layer on the interlayer insulating layer including the first diffusion barrier layer, forming a photoresist pattern on the first diffusion barrier layer of the contact hole, and using the photoresist pattern as an etching mask Since the exposed portion of the barrier layer is removed, the first diffusion barrier layer remains only in the contact hole, and after the photoresist pattern is removed, the barrier layer includes the first diffusion barrier layer remaining in the contact hole. And forming a second diffusion barrier layer on the interlayer insulating film.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a 내지 1f도는 본 발명에 의한 확산방지층 형성방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1F are cross-sectional views of the device shown for explaining the method for forming the diffusion barrier layer according to the present invention.
제1a도는 실리콘 기판(1)상에 층간 절연막(3)을 형성한 후, 콘택홀 마스크를 사용한 리소그라피 공정 및 층간 절연막(3)식각공정으로 접합부(2)가 노출되는 콘택홀(4)을 형성한 것이 도시된다. 콘택홀(4)을 형성하기 위한 식각공정은 콘택홀(4)의 단차비를 낮추어 층덮힘을 향상시키기 위하여 등방성과 비등방성의 2단계 식각공정으로 실시한다.In FIG. 1A, after forming the interlayer insulating film 3 on the silicon substrate 1, the contact hole 4 through which the junction part 2 is exposed is formed by a lithography process using a contact hole mask and an etching process between the interlayer insulating film 3. One is shown. The etching process for forming the contact hole 4 is performed in a two-step etching process of isotropic and anisotropic in order to lower the step ratio of the contact hole 4 to improve the layer covering.
제1b도는 콘택홀(4)을 포함한 층간 절연막(3)상에 제1 확산방지층(5a)을 형성한 것이 도시된다.FIG. 1B shows the formation of the first diffusion barrier layer 5a on the interlayer insulating film 3 including the contact hole 4.
상기에서, 제1 확산방지층(5a)은 층덮힘이 나빠 콘택홀(4)내부에는 얇게 증착되고, 콘택홀(4)이외의 부분에는 두껍게 증착된다. 반도체 소자의 제조공정에서 알루미늄 합금으로 금속배선을 형성할 경우 알루미늄 합금의 층덮힘율을 높기기 위해 고온공정이 필수적이며, 이때 알루미늄 이온과 접합부(2)의 실리콘 이온이 반응하는 것을 확실하게 방지하기 위하여 접합부(2) 부분에서 제1 확산방지층(5a)의 두께가 충분히 두꺼워야 한다. 그런데 접합부(2) 부분에서 제1 확산방지층(5a)을 충분히 두껍게 할 경우 콘택홀(4)이외의 부분에 필요이상으로 두껍게 형성되어 콘택홀(4)의 단차비가 증가되고, 이로 인하여 알루미늄 합금 증착공정을 어렵게 한다. 이러한 문제점을 해결하기 위한 공정이 하기에서 설명된다.In the above, the first diffusion barrier layer 5a has a poor layer covering and is deposited thinly in the contact hole 4, and is thickly deposited in portions other than the contact hole 4. When forming a metal wiring with aluminum alloy in the manufacturing process of a semiconductor device, a high temperature process is essential to increase the layer covering ratio of the aluminum alloy, and in order to reliably prevent the reaction between the aluminum ions and the silicon ions of the junction 2. At the junction 2, the thickness of the first diffusion barrier layer 5a should be sufficiently thick. However, when the first diffusion barrier layer 5a is sufficiently thick at the junction part 2, the step difference ratio of the contact hole 4 is increased because it is formed thicker than necessary in the parts other than the contact hole 4, thereby depositing aluminum alloy. Make the process difficult. A process for solving this problem is described below.
제1c도는 제1 확산방지층(5a)상에 포토레지스트를 도포한 후 마스크를 사용한 노광공정 및 현상공정으로 콘택홀(4)부분에 포토레지스트 패턴(6)을 형성한 것이 도시된다.FIG. 1C shows that the photoresist pattern 6 is formed in the contact hole 4 by the exposure process and the development process using a mask after applying the photoresist on the first diffusion barrier layer 5a.
제1d도는 포토레지스트 패턴(6)을 식각 마스크로 하여 제1 확산방지층(5a)의 노출된 부분을 제거하므로, 이로인하여 콘택홀(4)내에만 제1 확산방지층(5a)이 잔류된 것이 도시된다.FIG. 1d illustrates that the exposed portion of the first diffusion barrier layer 5a is removed using the photoresist pattern 6 as an etch mask, and thus, the first diffusion barrier layer 5a remains only in the contact hole 4. do.
제1e도는 포토레지스트 패턴(6)을 제거한 후, 콘택홀(4)내부에 잔류된 제1 확산방지층(5a)을 포함한 층간 절연막(3)상에 제2확산방지층(5b)을 형성하여 제1 및 제2 확산방지층(5a 및 5b)으로 된 본 발명의 확산방지층(5)을 형성한 것이 도시된다.In FIG. 1E, after the photoresist pattern 6 is removed, the second diffusion barrier layer 5b is formed on the interlayer insulating layer 3 including the first diffusion barrier layer 5a remaining in the contact hole 4. And forming the diffusion barrier layer 5 of the present invention consisting of the second diffusion barrier layers 5a and 5b.
본 발명의 확산방지층(5)은 알루미늄 이온과 실리콘 이온이 반응하는 것을 확실하게 방지하기 위하여 충분한 두께를 필요로한는 콘택홀(4)내부에는 제1 및 2 확산방지층(5a 및 5b)으로 이중층이 되게하고, 콘택홀(4)의 단차비 증가를 최소한으로 하기 위하여 얇은 두께를 필요로 하는 콘택홀(4)이외의 부분에는 제2 확산방지층(5b)만으로 단층이 되게한다.The diffusion barrier layer 5 of the present invention has a double layer with first and second diffusion barrier layers 5a and 5b inside the contact hole 4, which needs a sufficient thickness to reliably prevent the aluminum ions and silicon ions from reacting. In order to minimize the increase in the step difference ratio of the contact hole 4, the portions other than the contact hole 4 requiring a thin thickness are formed to be a single layer only with the second diffusion barrier layer 5b.
제1 및 제2확산방지층(5a 및 5b)은 주로 Ti/TiN을 물리적 증착방법(PVD)또는 화학적 증착방법(Chemical Vapor Deposition; CVD)으로 증착하여 형성된다.The first and second diffusion barrier layers 5a and 5b are mainly formed by depositing Ti / TiN by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
제1f도는 확산방지층(5)상에 물리적 증착방법(PVD)으로 알루미늄합금을 고온증착하여 금속배선(7)을 형성한 것이 도시된다. 이때, 접합부(2)상의 확산방지층(5)이 두껍기 때문에 알루미늄 이온과 실리콘 이온이 상호 반응되는 것이 방지된다.FIG. 1F shows that the metal wiring 7 is formed by high temperature deposition of aluminum alloy on the diffusion barrier layer 5 by physical vapor deposition (PVD). At this time, since the diffusion barrier layer 5 on the junction portion 2 is thick, the aluminum ions and the silicon ions are prevented from reacting with each other.
상술한 바와같이 본 발명은 콘택홀이외의 부분에 형성되는 확산방지층의 두께를 증가시키기 않으면서 콘택홀 내부의 확산방지층을 두껍게 형성하므로써, 고온의 알루미늄 합금 증착공정시 알루미늄 이온과 접합부의 실리콘 이온이 상호 반응되는 것을 방지하여 스파킹(spiking)등을 효과적으로 방지할 수 있고, 콘택홀의 단차비 증가를 최소화하여 금속배선공정을 용이하게 할 수 있다.As described above, the present invention forms a thick diffusion barrier layer inside the contact hole without increasing the thickness of the diffusion barrier layer formed in the portion other than the contact hole, so that the silicon ion at the junction of the aluminum ion and the junction portion during the high temperature aluminum alloy deposition process is increased. It is possible to effectively prevent sparking (spiking, etc.) by preventing the mutual reaction, and to facilitate the metal wiring process by minimizing the increase in the step difference ratio of the contact hole.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012707A KR100187677B1 (en) | 1995-05-22 | 1995-05-22 | Forming method of diffusion prevention layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012707A KR100187677B1 (en) | 1995-05-22 | 1995-05-22 | Forming method of diffusion prevention layer |
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| Publication Number | Publication Date |
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| KR960042957A KR960042957A (en) | 1996-12-21 |
| KR100187677B1 true KR100187677B1 (en) | 1999-06-01 |
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| KR1019950012707A KR100187677B1 (en) | 1995-05-22 | 1995-05-22 | Forming method of diffusion prevention layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100953022B1 (en) * | 2007-03-15 | 2010-04-14 | 주식회사 하이닉스반도체 | Method of forming a contact plug in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000269222A (en) * | 1999-03-18 | 2000-09-29 | Toshiba Corp | Semiconductor device and manufacture thereof |
| KR100323719B1 (en) * | 1999-12-28 | 2002-02-19 | 박종섭 | Metal line of semiconductor device and method for fabricating the same |
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1995
- 1995-05-22 KR KR1019950012707A patent/KR100187677B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100953022B1 (en) * | 2007-03-15 | 2010-04-14 | 주식회사 하이닉스반도체 | Method of forming a contact plug in semiconductor device |
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| Publication number | Publication date |
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| KR960042957A (en) | 1996-12-21 |
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