KR0167607B1 - Method of making gate electrode of rom - Google Patents
Method of making gate electrode of rom Download PDFInfo
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- KR0167607B1 KR0167607B1 KR1019940037660A KR19940037660A KR0167607B1 KR 0167607 B1 KR0167607 B1 KR 0167607B1 KR 1019940037660 A KR1019940037660 A KR 1019940037660A KR 19940037660 A KR19940037660 A KR 19940037660A KR 0167607 B1 KR0167607 B1 KR 0167607B1
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- South Korea
- Prior art keywords
- gate electrode
- pattern
- mask
- rom
- patterns
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims 2
- 239000011810 insulating material Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/36—Gate programmed, e.g. different gate material or no gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
내용 없음.No content.
Description
제1도는 낸드(NAND)형 마스크롬의 기본 회로도.1 is a basic circuit diagram of a NAND mask mask.
제2도는 종래 방법에 따라 형성된 제1도의 마스크롬의 스트링의 단면도.2 is a cross-sectional view of the string of maskroms of FIG. 1 formed according to a conventional method.
제3a도 내지 제3c도는 본 발명에 따른 상기 제1도의 마스크롬의 제조과정을 나타내는 공정단면도.3a to 3c is a cross-sectional view showing a manufacturing process of the mask rom of FIG. 1 according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
31 : 반도체기판 32 : 게이트산화층31 semiconductor substrate 32 gate oxide layer
33 : 게이트폴리실리콘층 34,35,35' : 감광막 패턴33: gate polysilicon layer 34, 35, 35 ': photosensitive film pattern
본 발명은 롬의 게이트전극 제조방법에 관한 것으로, 특히 콘택 형성 없이 워드라인 선택라인(W/L select line)과 롬코드라인(ROM code line) 형성시 워드라인과 워드라인 사이 간격을 최소화하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate electrode of a ROM, and in particular, to minimize the gap between a word line and a word line when forming a word line selection line and a ROM code line without forming a contact. It is about a method.
콘택-레스(contact-less) 마스크롬(Mask ROM)은 콘택홀이 필요 없이 웨이퍼에 이온 주입된 불순물의 확산에 의해 스트링이 형성되는 마스크롬을 일컫는다Contact-less mask ROM refers to a mask ROM in which a string is formed by diffusion of impurities implanted into a wafer without requiring a contact hole.
제1도는 낸드(NAND)형 마스크롬의 기본 회로도로서, 비트라인은 콘택에 의해 메탈라인으로 구성되며, 롬코드(W/LO 내지 W/L7) 및 워드라인 선택라인(W/L선택1, W/L선택2)은 폴리실리콘 라인으로 구성된다. 즉, 콘택-레스로 연결되어 있다.FIG. 1 is a basic circuit diagram of a NAND type mask ROM, in which a bit line is formed of a metal line by a contact, and a ROM code (W / LO to W / L7) and a word line selection line (W / L selection 1, W / L selection 2) consists of polysilicon lines. That is, contactless.
한편, 제2도는 종래 방법에 따라 형성된 제1도의 마스크롬의 단면도로서, 이를 통하여 종래 기술을 개략적으로 설명하면 다음과 같다.On the other hand, Figure 2 is a cross-sectional view of the mask ROM of Figure 1 formed in accordance with the conventional method, through which the prior art will be outlined as follows.
도시된 바와 같이 반도체기판(1) 위에 게이트산화층(2), 게이트폴리실리콘층(3)을 차례로 증착한 다음, 워드라인선택1, 2(11, 12)와 워드라인 0 내지 워드라인 7(21 내지 28)의 폴리실리콘라인은 포토리소그라피 공정에 의한 감광막 패턴을 식각마스크로 상기 게이트폴리실리콘층(3), 게이트산화층(2)을 차례로 선택식각함으로써 이루어진다.As illustrated, the gate oxide layer 2 and the gate polysilicon layer 3 are sequentially deposited on the semiconductor substrate 1, and then word line selection 1, 2 (11, 12) and word lines 0 to word line 7 (21). The polysilicon lines of (28) to (28) are formed by selectively etching the gate polysilicon layer (3) and the gate oxide layer (2) with the photoresist pattern by the photolithography process as an etch mask.
그러나, 상기 종래 방법은 노광기의 해상력을 고려할 때 패턴된 게이트폴리실리콘층(즉, 워드라인) 간의 간격(도면의 A)이 가장 적어야 0.5㎛ 내지 0.7㎛로 형성되기 때문에 집적도에는 한계가 따른다.However, the conventional method has a limitation in integration degree because the gap between the patterned gate polysilicon layers (ie, word lines) is formed to be 0.5 μm to 0.7 μm at least when considering the resolution of the exposure machine.
상기와 같은 종래 기술의 문제점을 해결하기 위하여 안출된 본 발명은 노광기의 해상력과는 무관하게 패턴간 간격을 최소화할 수 있는 롬의 게이트전극 제조방법을 제공하는데 그 목적이 있다.The present invention devised to solve the problems of the prior art as described above is an object of the present invention to provide a method for manufacturing a gate electrode of the ROM that can minimize the gap between patterns irrespective of the resolution of the exposure machine.
상기 목적을 달성하기 위하여 본 발명은, 롬의 게이트전극 제조방법에 있어서, 게이트전극층 상부에 상기 게이트전극 형성을 위한 다수의 제1마스크패턴을 형성하되, 패턴의 크기는 원하는 게이트전극의 크기와 동일하게 형성하고, 패턴간 간격은 상기 게이트전극의 페턴 크기보다 크게 형성하는 제1단계; 그 에지가 상기 제1마스크페턴의 에지와 분리되도록, 상기 제1마스크패턴 사이에 상기 게이트전극의 크기와 동일한 크기의 제2마스크패턴을 형성하는 제2단계; 및 상기 제1 및 제2 마스크패턴을 식각마스크로 하여 상기 게이트전극층을 식각하는 제3단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method for manufacturing a gate electrode of a ROM, wherein a plurality of first mask patterns for forming the gate electrode are formed on the gate electrode layer, and the size of the pattern is the same as that of the desired gate electrode. A first step of forming a gap between the patterns larger than the pattern size of the gate electrode; Forming a second mask pattern having a size equal to that of the gate electrode between the first mask pattern such that an edge thereof is separated from an edge of the first mask pattern; And etching the gate electrode layer using the first and second mask patterns as an etching mask.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
제3a도 내지 제3d도는 본 발명에 따른 상기 제1도의 마스크롬의 제조과정을 나타내는 공정단면도로서, 먼저, 제3a도에 도시된 바와 같이 반도체기판(31) 위에 게이트산화층(32), 게이트폴리실리콘층(33)을 증착한 다음 감광막 패턴(34)을 형성한다. 이때, 상기 감광막 패턴(34)은 게이트 전극 형성 영역 이외의 영역에 0.6㎛(B)의 크기로 형성되며, 패턴간 간격은 1.2㎛(C)가 되도록 한다. 또한, 감광막 패턴(34) 외에 화학기상증착(CVD)법에 의한 산화막 패턴도 가능하다.3A through 3D are cross-sectional views illustrating a process of manufacturing the mask rom of FIG. 1 according to the present invention. First, as shown in FIG. 3A, the gate oxide layer 32 and the gate poly are formed on the semiconductor substrate 31. After the silicon layer 33 is deposited, a photoresist pattern 34 is formed. In this case, the photoresist pattern 34 is formed to have a size of 0.6 μm (B) in regions other than the gate electrode formation region, and the interval between patterns is 1.2 μm (C). In addition to the photosensitive film pattern 34, an oxide film pattern by chemical vapor deposition (CVD) is also possible.
이어서, 상기 감광막 패턴을 130℃에서 2분간 하드베이크(hard-bake)한 다음제3b도에 도시된 바와 같이 상기 전체구조 상부에 감광막(35)을 도포 한다. 이때, 하드베이크를 실시할 경우 감광막 내의 포토액티브 구성성분(photo active compound)이 그 기능을 상실하여 차후 빛 에너지를 받아도 감광막이 현상용액에 현상되지 않는다.Subsequently, the photoresist pattern is hard-baked at 130 ° C. for 2 minutes, and then the photoresist layer 35 is coated on the entire structure as shown in FIG. 3B. In this case, when the hard bake is performed, the photoactive compound in the photoresist film loses its function, and the photoresist film is not developed in the developing solution even after receiving light energy.
계속해서, 제3c도와 같이, 상기 감광막(35)을 선택 식각하여 상기 감광막패턴(34) 사이에 또다른 감광막 패턴(35')을 패턴 크기는 0.6㎛(D)으로, 패턴간 간격은 1.2㎛(E)로 형성한다.Subsequently, as shown in FIG. 3C, another photoresist layer pattern 35 ′ is selectively etched between the photoresist layer patterns by patterning the photoresist layer 35 with a pattern size of 0.6 μm (D) and an interval between patterns of 1.2 μm. It is formed as (E).
끝으로, 상기 감광막 패턴(34, 35')을 식각마스크로 하부의 상기 게이트폴리 실리콘층(33)을 선택식각함으로써 제3d도에 도시된 바와 같이 패턴간 간격이 0.3㎛(A')인 게이트 전극을 형성한다.Finally, the gate polysilicon layer 33 is selectively etched using the photoresist patterns 34 and 35 'as an etch mask, so that the gap between the patterns is 0.3 mu m (A') as shown in FIG. Form an electrode.
한편, 낸드형 EPROM 형성 공정에서도 콘택-레스 컨트롤 게이트가 사용되므로 본 발명이 적용될 수 있다.On the other hand, since the contact-less control gate is also used in the NAND-type EPROM forming process, the present invention can be applied.
상기와 같이 이루어지는 본 발명은 마스크롬 제조시 게이트전극 패턴간 간격을 줄임으로써 소자의 집적도를 증대시킬 수 있다.The present invention made as described above can increase the degree of integration of the device by reducing the gap between the gate electrode pattern when manufacturing the mask rom.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037660A KR0167607B1 (en) | 1994-12-28 | 1994-12-28 | Method of making gate electrode of rom |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037660A KR0167607B1 (en) | 1994-12-28 | 1994-12-28 | Method of making gate electrode of rom |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960026891A KR960026891A (en) | 1996-07-22 |
| KR0167607B1 true KR0167607B1 (en) | 1999-01-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940037660A KR0167607B1 (en) | 1994-12-28 | 1994-12-28 | Method of making gate electrode of rom |
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| Country | Link |
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| KR (1) | KR0167607B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100370137B1 (en) * | 2000-12-29 | 2003-01-30 | 주식회사 하이닉스반도체 | A array of flat rom cell method for fabricating the same |
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1994
- 1994-12-28 KR KR1019940037660A patent/KR0167607B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR960026891A (en) | 1996-07-22 |
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