KR100398576B1 - A method for improving alignment accuracy - Google Patents
A method for improving alignment accuracy Download PDFInfo
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- KR100398576B1 KR100398576B1 KR10-2001-0047460A KR20010047460A KR100398576B1 KR 100398576 B1 KR100398576 B1 KR 100398576B1 KR 20010047460 A KR20010047460 A KR 20010047460A KR 100398576 B1 KR100398576 B1 KR 100398576B1
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- insulating layer
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 92
- 230000002093 peripheral effect Effects 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000000903 blocking effect Effects 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005259 measurement Methods 0.000 description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
본 발명은 기판의 주변영역에 오버레이키(overlay key) 형성 시, 상기 오버레이키의 정렬 정확도(alignment accuracy)를 향상시킬 수 있는 정렬 정확도의 향상방법에 관해 개시한다.The present invention discloses a method of improving the alignment accuracy that can improve the alignment accuracy of the overlay key when the overlay key is formed in the peripheral area of the substrate.
개시된 본 발명의 정렬 정확도의 향상방법은 반도체기판의 셀영역 및 주변영역에 절연층 및 제 1도전층을 차례로 형성하는 공정과, 절연층 및 제 1도전층을 선택 식각하여 셀영역에 게이트절연층 및 게이트를 형성하는 동시에 주변영역에 블로킹패턴을 각각 형성하는 공정과, 셀영역의 게이트 및 상기 주변영역의 블로킹패턴을 덮으며, 셀영역 및 주변영역에 기판의 소정부위를 노출시키는 각각의 콘택홀을 가진 층간절연층을 형성하는 공정과, 층간절연층 상에 콘택홀을 덮도록 제 2도전층을 형성하는 공정과, 제 2도전층을 식각하여 상기 셀영역에 상기 콘택홀을 매립시키는 도전플러그를 형성하는 동시에 주변영역에 층간절연층과 단차진 오버레이키를 형성하는 공정을 구비한다.The method of improving the alignment accuracy according to the present invention includes the steps of sequentially forming an insulating layer and a first conductive layer in the cell region and the peripheral region of the semiconductor substrate, and selectively etching the insulating layer and the first conductive layer to form a gate insulating layer in the cell region. And forming a gate and simultaneously forming a blocking pattern in the peripheral area, and covering each of the gate and the blocking pattern in the peripheral area and exposing a predetermined portion of the substrate in the cell area and the peripheral area. Forming an interlayer insulating layer having an insulating layer; forming a second conductive layer covering the contact hole on the interlayer insulating layer; and etching a second conductive layer to fill the contact hole in the cell region. And forming an interlayer dielectric layer and a stepped overlay key in the peripheral area.
Description
본 발명은 정렬 정확도 향상방법에 관한 것으로, 보다 상세하게는 기판의 주변영역에 오버레이(overlay) 측정부를 형성할 경우, 상기 오버레이 측정부의 어라인 정확도를 향상시킬 수 있는 정렬 정확도 향상방법에 관한 것이다.The present invention relates to a method for improving alignment accuracy, and more particularly, to an alignment accuracy improving method for improving the alignment accuracy of the overlay measuring unit when an overlay measuring unit is formed in a peripheral area of the substrate.
일반적으로 알려진 바와 같이, 반도체소자의 집적도가 증가함에 따라 미세한 패턴의 형성뿐만 아니라 노광공정에서 마스크 패턴과 반도체기판 간의 정확한 겹침 정확도(registration accuracy)가 요구되고 있다.As is generally known, as the degree of integration of semiconductor devices increases, precise registration accuracy between the mask pattern and the semiconductor substrate is required in the exposure process as well as the formation of fine patterns.
반도체 기판 상에 패턴을 형성하기 위해서는, 포토레지스트와 같은 감광성 물질을 도포한 후 유리 마스크상의 이미지를 감광성 물질 위에 전사시켜 노광시켜야 한다. 즉, 마스크상의 특정표지를 반도체 기판의 임의의 지점(얼라인 키)과 일치시킨 다음, 유리 마스크 위로 광선을 투사하여 그 패턴의 이미지를 기판 위로 전사하여야 한다.In order to form a pattern on a semiconductor substrate, after applying a photosensitive material such as a photoresist, the image on the glass mask must be transferred onto the photosensitive material and exposed. That is, the specific mark on the mask must be matched with an arbitrary point (align key) of the semiconductor substrate, and then a light beam is projected onto the glass mask to transfer the image of the pattern onto the substrate.
한편, 반도체장치의 고집적화와 더불어 각 층마다 미스얼라인 마진(misalign margin)이 감소함으로 인해 보다 정확한 얼라인이 요구된다.On the other hand, due to the high integration of semiconductor devices and the misalign margin of each layer is reduced, more accurate alignment is required.
얼라인 장치가 얼라인 키의 위치를 찾지 못하여 마스크 얼라인이 제대로 되지 않을 경우 미스얼라인(misalign), 패턴이동(kpotern shift) 등의 여러 문제를 일으키게 되고 제품의 수율 및 실패에 직접적인 영향을 미치므로, 얼라인 키의 능력의향상이 절실히 요구되고 있다. 뿐만 아니라, 반도체 소자의 고집적화 추세에 따라 공정이 더욱 복잡해지고, 포토레지스트패턴의 마스킹 및 노광의 횟수가 증가함으로 인하여 초기 단계에서 형성된 얼라인 키의 패턴이 마모되거나 소실되어 그능력을 발휘할 수 없게 되는 경향이 있다.If the alignment device does not locate the alignment key and the mask alignment is not correct, it causes various problems such as misalignment and kpotern shift, and directly affects the yield and failure of the product. Therefore, the improvement of the ability of the align key is urgently required. In addition, the process becomes more complicated according to the trend of higher integration of semiconductor devices, and as the number of masking and exposure of the photoresist pattern increases, the pattern of the alignment key formed in the initial stage is worn out or lost, so that the ability of the semiconductor device cannot be exhibited. There is a tendency.
따라서, 얼라인 키를 형성할 때 오버레이 키(overlay key)를 동시에 형성하는데, 이는 마스크와 반도체 기판을 얼라인한 후에 얼라인 상태를 확인하기 위한 것으로 얼라인 키보다 큰 패턴으로 형성하여 어미자로 하고 상기 어미자 상에 감광막을 사용하여 아들자를 형성한다.Therefore, when forming the alignment key, an overlay key is simultaneously formed, which is to check the alignment state after aligning the mask and the semiconductor substrate, and forming a larger pattern than the alignment key as a mother. A photosensitive film is used on the mother to form the son.
도 1a 내지 도 1c는 종래 기술에 따른 오버레이키의 제조를 보인 공정순서도이다.1A to 1C are process flowcharts showing the manufacture of an overlay key according to the prior art.
종래 기술에 따른 오버레이키의 제조방법은, 도 1a에 도시된 바와 같이, 먼저 셀영역 및 주변영역을 포함한 반도체기판(100) 전면에 제 1절연층(102)과, 다결정실리콘층(104), 텅스텐실리사이드층(106), 제 2절연층(108), 제 3절연층(110)을 차례로 형성한 후, 도 1b에 도시된 바와 같이, 주변영역은 제거하고, 셀영역에는 포토리쏘그라피(photolithography)공정에 의해 식각하여 게이트(120)를 형성한다.In the overlay key manufacturing method according to the related art, as shown in FIG. 1A, first, the first insulating layer 102, the polycrystalline silicon layer 104, and the front surface of the semiconductor substrate 100 including the cell region and the peripheral region, After forming the tungsten silicide layer 106, the second insulating layer 108, and the third insulating layer 110 in order, as shown in FIG. 1B, the peripheral region is removed and the photolithography is performed in the cell region. Etching to form a gate 120.
이때, 제 1절연층과 제 3절연층으로는 산화막을 이용하며, 제 2절연층으로는 질화막을 이용한다. 또한, 게이트 하부의 잔류된 제 1절연층은 게이트절연층(121)이 된다.In this case, an oxide film is used as the first insulating layer and a third insulating layer, and a nitride film is used as the second insulating layer. In addition, the remaining first insulating layer under the gate becomes the gate insulating layer 121.
이어서, 상기 결과의 셀영역 및 주변영역에 BPSG(BoroPhosphor Silicate Glass)를 증착하여 층간절연층(112)을 형성한 후, 상기 층간절연층(112)을 식각하여 각각의 랜딩플러그콘택(LPC:Landing Plug Contact)(114)을 형성한다.Subsequently, BPSG (BoroPhosphor Silicate Glass) is deposited on the resultant cell region and the surrounding region to form an interlayer insulating layer 112, and then the interlayer insulating layer 112 is etched to each landing plug contact (LPC). Plug Contact 114 is formed.
그 다음, 도 1c에 도시된 바와 같이, 랜딩플러그콘택(114)을 포함한 상기 구조 상에 다결정실리콘층 등의 도전물질을 증착한 후, 화학기계적연마(CMP:Chemical Mechanical Polishing) 방법으로 폴리싱(polishing)하여 셀영역 에 도전플러그(116) 및 주변영역에 오버레이키(118)를 형성한다.Next, as illustrated in FIG. 1C, a conductive material such as a polysilicon layer is deposited on the structure including the landing plug contact 114, and then polished by chemical mechanical polishing (CMP). ) To form a conductive plug 116 in the cell region and an overlay key 118 in the peripheral region.
그러나, 종래의 반도체장치의 제조방법에서는 도전플러그 형성 시, 층간절연층과 다결정실리콘층 간의 단차가 거의 없으므로, 랜딩플러그콘택 오버레이 측정부에서 층간절연층과 다결정실리콘층을 구분하기가 어려웠다.However, in the manufacturing method of the conventional semiconductor device, when the conductive plug is formed, there is almost no step between the interlayer insulating layer and the polycrystalline silicon layer, so it is difficult to distinguish between the interlayer insulating layer and the polycrystalline silicon layer in the landing plug contact overlay measurement unit.
즉, 후속의 공정에서 도전플러그 패턴과의 오버레이(overlay)를 계측할 경우, 도 2a 내지 도 2c에 도시된 바와 같이, 층간절연층과 다결정실리콘층 간의 시그널 (signal) 구분이 어려워서 오버레이 계측 불량이 초래되는 문제점이 있었다.That is, when measuring the overlay with the conductive plug pattern in a subsequent process, as shown in Figs. 2a to 2c, it is difficult to distinguish the signal between the interlayer insulating layer and the polysilicon layer, so that the overlay measurement failure is difficult. There was a problem brought about.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 랜딩플러크콘택의 오버레이의 계측을 정확하게 진행하여 정렬 정확도를 향상시킬 수 있는 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for improving alignment accuracy by accurately measuring the overlay of a landing plug contact.
도 1a 내지 도 1c는 종래 기술에 따른 오버레이키의 제조를 보인 공정순서도.1a to 1c is a process flowchart showing the manufacture of the overlay key according to the prior art.
도 2a 내지 도 2c는 종래의 오버레이키의 평면도, 단면도 및 시그널을 도시한 도면.2A to 2C show a plan view, a cross sectional view, and a signal of a conventional overlay key;
도 3a 내지 도 3c는 본 발명에 따른 오버레이키의 제조를 보인 공정순서도.3a to 3c is a process flow chart showing the manufacture of the overlay key according to the present invention.
도 4a 내지 도 4c는 본 발명에 따른 오버레이키의 평면도, 단면도 및 시그널을 도시한 도면.4a to 4c show a plan view, a cross sectional view and a signal of an overlay key according to the invention;
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
200. 반도체기판 202. 제 1절연층200. Semiconductor substrate 202. First insulating layer
204. 다결정실리콘층 206. 텅스텐실리사이드층204. Polycrystalline silicon layer 206. Tungsten silicide layer
208. 제 2절연층 210. 제 3절연층208. Second insulating layer 210. Third insulating layer
212. 층간절연층 214. 랜딩플러그콘택212. Insulation layer 214. Landing plug contact
216. 도전플러그 220. 게이트216.Conductive Plug 220.Gate
221. 게이트절연층 230. 보조패턴221. Gate insulating layer 230. Auxiliary pattern
상기 목적을 달성하기 위한 본 발명의 정렬 정확도 향상방법은 반도체기판의 셀영역 및 주변영역에 절연층 및 제 1도전층을 차례로 형성하는 공정과, 절연층 및 제 1도전층을 선택 식각하여 셀영역에 게이트절연층 및 게이트를 형성하는 동시에 주변영역에 블로킹패턴을 각각 형성하는 공정과, 셀영역의 게이트 및 상기 주변영역의 블로킹패턴을 덮으며, 셀영역 및 주변영역에 기판의 소정부위를 노출시키는 각각의 콘택홀을 가진 층간절연층을 형성하는 공정과, 층간절연층 상에 콘택홀을덮도록 제 2도전층을 형성하는 공정과, 제 2도전층을 식각하여 상기 셀영역에 상기 콘택홀을 매립시키는 도전플러그를 형성하는 동시에 주변영역에 층간절연층과의 단차진 오버레이키를 형성하는 공정을 구비한 것을 특징으로 한다.The method of improving the alignment accuracy of the present invention for achieving the above object is a step of sequentially forming the insulating layer and the first conductive layer in the cell region and the peripheral region of the semiconductor substrate, and selectively etching the insulating layer and the first conductive layer to the cell region Forming a gate insulating layer and a gate at the same time, and forming a blocking pattern in the peripheral region, covering the gate of the cell region and the blocking pattern of the peripheral region, and exposing a predetermined portion of the substrate in the cell region and the peripheral region. Forming an interlayer insulating layer having respective contact holes; forming a second conductive layer covering the contact hole on the interlayer insulating layer; and etching the second conductive layer to form the contact hole in the cell region. And forming a stepped overlay key with the interlayer insulating layer in the peripheral area while forming a conductive plug to be embedded.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3c는 본 발명에 따른 반도체장치의 제조를 보인 공정순서도이다.3A to 3C are process flowcharts showing the manufacture of a semiconductor device according to the present invention.
본 발명의 오버레이키의 제조는, 도 3a에 도시된 바와 같이, 먼저, 셀영역 및 주변영역을 포함한 반도체기판(200) 전면에 제 1절연층(202), 다결정실리콘층In the manufacture of the overlay key of the present invention, as shown in FIG. 3A, first, the first insulating layer 202 and the polysilicon layer on the front surface of the semiconductor substrate 200 including the cell region and the peripheral region.
(204), 텅스텐실리사이드층(206), 제 2절연층(208) 및 제 3절연층(210)을 차례로 형성한다. 이때, 상기 제 1절연층(202)과 제 3절연층(210)은 산화막을 화학기상증착하고, 제 2절연층(208)은 질화막을 화학기상증착하여 이를 이용한다.204, a tungsten silicide layer 206, a second insulating layer 208, and a third insulating layer 210 are formed in this order. In this case, the first insulating layer 202 and the third insulating layer 210 are chemically vapor deposited on the oxide film, and the second insulating layer 208 uses the chemical vapor deposition on the nitride film.
이어서, 도 3b에 도시된 바와 같이, 포토리쏘그라피 공정에 의해 제 1절연층(202)과, 다결정실리콘층(204), 텅스텐실리사이드층(206), 제 2절연층(208) 및 제 3절연층(210)의 소정부위를 식각하여 셀영역에는 게이트절연층을 포함한 게이트(220)를 형성하고, 주변영역에는 보조패턴(230)을 형성한다.Subsequently, as shown in FIG. 3B, the first insulating layer 202, the polycrystalline silicon layer 204, the tungsten silicide layer 206, the second insulating layer 208, and the third insulating layer are formed by a photolithography process. A predetermined portion of the layer 210 is etched to form a gate 220 including a gate insulating layer in the cell region, and an auxiliary pattern 230 is formed in the peripheral region.
이때, 게이트(220) 하부의 잔류된 제 1절연층은 게이트절연층(121)이 된다.In this case, the remaining first insulating layer under the gate 220 becomes the gate insulating layer 121.
그 다음, 상기 결과의 셀영역 및 주변영역에 BPSG를 증착하여 층간절연층(212)을 형성한 후, 상기 층간절연층(212)을 식각하여 각각의 랜딩플러그콘택(LPC)(214)을 형성한다.Then, the interlayer dielectric layer 212 is formed by depositing BPSG on the resultant cell region and the peripheral region, and then the respective landing plug contacts (LPC) 214 are formed by etching the interlayer dielectric layer 212. do.
이 후, 도 3c에 도시된 바와 같이, 랜딩플러그콘택(214)을 포함한 상기 구조 상에 다결정실리콘층을 증착한 후, 화학기계적 연마 등의 방법으로 폴리싱하여 셀영역 및 주변영역에 각각의 도전플러그(216) 및 오버레이키(218)을 형성한다.Thereafter, as shown in FIG. 3C, a polysilicon layer is deposited on the structure including the landing plug contact 214, and then polished by chemical mechanical polishing or the like, and the respective conductive plugs are applied to the cell region and the peripheral region. 216 and the overlay key 218 are formed.
상기 오버레이키(218)는 층간절연층(212)의 표면으로 부터 돌출된 형상을 가지도록 형성되며, 이 과정에서 보조패턴(230)의 최상층인 제 3절연층(210)이 식각될 수 있으며, 도면에는 도시되어 있지 않지만, 그 하부의 제 2절연층(208)까지 모두 식각될 수 있다.The overlay key 218 is formed to have a shape protruding from the surface of the interlayer insulating layer 212. In this process, the third insulating layer 210, which is the uppermost layer of the auxiliary pattern 230, may be etched. Although not shown in the drawings, all of the underlying second insulating layer 208 may be etched.
따라서, 상기 보조패턴(230)은 층간절연층(212)과 다결정실리콘층의 경계부분의 선택적 폴리싱이 가능하도록 해주는 역할을 한다.Thus, the auxiliary pattern 230 serves to enable selective polishing of the boundary between the interlayer insulating layer 212 and the polysilicon layer.
도 4a 내지 도 4c는 본 발명에 따른 오버레이키의 평면도, 단면도 및 시그널을 도시한 도면이다.4A to 4C are a plan view, a cross-sectional view and a signal of the overlay key according to the present invention.
본 발명은, 도 4a 내지 도 4c에 도시된 바와 같이, 주변영역에 보조패턴 (230)을 추가하여 층간절연층의 표면으로 부터 돌출된 형상을 가지는 오버레이키4A to 4C, the overlay key having a shape protruding from the surface of the interlayer insulating layer by adding the auxiliary pattern 230 to the peripheral area is shown in FIGS.
(218)를 형성함으로써, 층간절연층과 다결정실리콘층 간의 오버레이 계측 시그널By forming 218, an overlay measurement signal between the interlayer insulating layer and the polysilicon layer
(signal) 구분하기가 용이해지므로 랜딩플러크콘택의 오버레이 계측을 정확하게 할 수 있다.This makes it easy to distinguish the signal so that the measurement of the overlay of the landing plug contact can be precise.
이상에서와 같이, 본 발명의 정렬 정확도의 향상방법에서는 셀영역에 게이트을 패터닝 시 주변영역의 랜딩플러그콘택 형성영역 주변에 보조패턴을 함께 패터닝함으로써, 이 후의 도전플러그 형성을 위한 폴리싱 공정 진행에서 층간절연층과 다결정실리콘층의 경계부분의 선택적 폴리싱이 가능하다.As described above, in the method of improving alignment accuracy according to the present invention, when the gate is patterned in the cell region, the auxiliary pattern is patterned around the landing plug contact forming region of the peripheral region, thereby interlayer insulation in the polishing process for forming the conductive plug thereafter. Selective polishing of the boundary of the layer and the polysilicon layer is possible.
따라서, 본 발명에서는 층간절연층과 다결정실리콘층 간의 오버레이 계측 시그널 구분이 용이해지므로 후속의 공정에서 도전플러그 패턴과의 오버레이 계측 시에 정확한 정렬이 가능하다.Therefore, in the present invention, it is easy to distinguish the overlay measurement signal between the interlayer insulating layer and the polysilicon layer, so that accurate alignment may be performed during overlay measurement with the conductive plug pattern in a subsequent process.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970017953A (en) * | 1995-09-29 | 1997-04-30 | 김광호 | How to form ALIGN KEY pattern |
| JPH1187488A (en) * | 1997-09-09 | 1999-03-30 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR19990067745A (en) * | 1998-01-05 | 1999-08-25 | 가네꼬 히사시 | Semiconductor integrated circuit device having alignment mark anchored to lower layer |
| JPH11297617A (en) * | 1998-04-13 | 1999-10-29 | Canon Inc | Substrate with alignment mark and manufacture of device |
| JPH11330382A (en) * | 1998-05-13 | 1999-11-30 | Denso Corp | Manufacture of semiconductor device |
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2001
- 2001-08-07 KR KR10-2001-0047460A patent/KR100398576B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970017953A (en) * | 1995-09-29 | 1997-04-30 | 김광호 | How to form ALIGN KEY pattern |
| JPH1187488A (en) * | 1997-09-09 | 1999-03-30 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR19990067745A (en) * | 1998-01-05 | 1999-08-25 | 가네꼬 히사시 | Semiconductor integrated circuit device having alignment mark anchored to lower layer |
| JPH11297617A (en) * | 1998-04-13 | 1999-10-29 | Canon Inc | Substrate with alignment mark and manufacture of device |
| JPH11330382A (en) * | 1998-05-13 | 1999-11-30 | Denso Corp | Manufacture of semiconductor device |
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