KR970017953A - How to form ALIGN KEY pattern - Google Patents

How to form ALIGN KEY pattern Download PDF

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Publication number
KR970017953A
KR970017953A KR1019950032954A KR19950032954A KR970017953A KR 970017953 A KR970017953 A KR 970017953A KR 1019950032954 A KR1019950032954 A KR 1019950032954A KR 19950032954 A KR19950032954 A KR 19950032954A KR 970017953 A KR970017953 A KR 970017953A
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KR
South Korea
Prior art keywords
alignment key
cmp
key pattern
alignment
forming
Prior art date
Application number
KR1019950032954A
Other languages
Korean (ko)
Inventor
김창규
김정엽
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950032954A priority Critical patent/KR970017953A/en
Publication of KR970017953A publication Critical patent/KR970017953A/en

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)

Abstract

반도체 장치의 얼라인 키(ALIGN KEY)패턴 형성 방법에 관한 것으로, 특히 CMP(Chemical Mechanical Polishing) 평탄화 공정과 단차를 이용하여 사진식각 공정의 정렬(alignment)에 잇점이 있는 얼라인 키(ALIGN KEY)패턴을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming an alignment key pattern of a semiconductor device, and in particular, an alignment key having an advantage in alignment of a photolithography process using a chemical mechanical polishing (CMP) planarization process and a step. A method of forming a pattern.

포토(PHOTO)공정을 진행하지 않고 CVD(chemical vapor deposition)막의 증착 특성과 CMP의 특성을 이용하여 얼라인 키 영역의 하부막에 선택적 노출 및 선택적 식각을 실시하여 얼라인 키를 형성하면 얼라인 키 영역에 단차가 형성되어 게이트 물질 증착시 쉽게 게이트 라인을 형성할 수 있다.If the alignment key is formed by performing selective exposure and selective etching on the lower layer of the alignment key region using the deposition characteristics of the CVD (chemical vapor deposition) film and the CMP characteristics without performing the photo process, the alignment key is formed. A step is formed in the region to easily form the gate line during the deposition of the gate material.

Description

얼라인 키(ALIGN KEY)패턴 형성 방법How to form ALIGN KEY pattern

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제7도는 본 발명에 의한 반도체 제조방법을 설명하기 도시한 단면도이다.1 to 7 are cross-sectional views illustrating a semiconductor manufacturing method according to the present invention.

Claims (2)

하드 마스크를 이용하여 트렌치를 형성하고 상기 트렌치를 매립하기 위해 화학적 기상 증착(CVD:Chemical Vapor Deposition)으로 절연막을 형성하고 화학적 기계적 연마(CMP:Chemical Mechanical Polishing)를 이용하여 상기 절연막을 평탄화하고 얼라인 키 영역의 하부막을 선택적 노출 및 선택적 식각공정하여 단차를 가지도록 하는 것을 특징으로 하는 반도체 장치의 얼라인 키(ALIGN KEY)패턴 형성 방법.A trench is formed using a hard mask and an insulating film is formed by chemical vapor deposition (CVD) to fill the trench, and the insulating film is planarized and aligned using chemical mechanical polishing (CMP). A method of forming an alignment key pattern of a semiconductor device, characterized in that the lower layer of the key region is selectively exposed and selectively etched to have a step. 상기 하드 마스크는 SiN, SiN/OXIDE 또는 OXIDE/SiN/OXIDE 등으로 형성하는 것을 특징으로 하는 반도체 장치의 얼라인 키(ALIGN KEY)패턴 형성 방법.And the hard mask is formed of SiN, SiN / OXIDE, OXIDE / SiN / OXIDE, or the like. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950032954A 1995-09-29 1995-09-29 How to form ALIGN KEY pattern KR970017953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950032954A KR970017953A (en) 1995-09-29 1995-09-29 How to form ALIGN KEY pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950032954A KR970017953A (en) 1995-09-29 1995-09-29 How to form ALIGN KEY pattern

Publications (1)

Publication Number Publication Date
KR970017953A true KR970017953A (en) 1997-04-30

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KR1019950032954A KR970017953A (en) 1995-09-29 1995-09-29 How to form ALIGN KEY pattern

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KR (1) KR970017953A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100398576B1 (en) * 2001-08-07 2003-09-19 주식회사 하이닉스반도체 A method for improving alignment accuracy

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100398576B1 (en) * 2001-08-07 2003-09-19 주식회사 하이닉스반도체 A method for improving alignment accuracy

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