KR960043118A - Bit line formation method of semiconductor device - Google Patents

Bit line formation method of semiconductor device Download PDF

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Publication number
KR960043118A
KR960043118A KR1019950012468A KR19950012468A KR960043118A KR 960043118 A KR960043118 A KR 960043118A KR 1019950012468 A KR1019950012468 A KR 1019950012468A KR 19950012468 A KR19950012468 A KR 19950012468A KR 960043118 A KR960043118 A KR 960043118A
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KR
South Korea
Prior art keywords
forming
conductive layer
transistor
bit line
photoresist pattern
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KR1019950012468A
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Korean (ko)
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KR0151047B1 (en
Inventor
남인호
이원성
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김광호
삼성전자 주식회사
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Priority to KR1019950012468A priority Critical patent/KR0151047B1/en
Publication of KR960043118A publication Critical patent/KR960043118A/en
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Publication of KR0151047B1 publication Critical patent/KR0151047B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 제1 도전층의 평탄화된 면상에 반도체 장치의 비트라인을 형성하는 방법에 관해 개시한다. 본 발명의 비트라인 형성방법은 반도체기판상에 트랜지스터를 형성하는 단계, 상기 트랜지스터가 형성된 반도체기판상에 제1 절연막을 형성하는 단계, 상기 제1 절연막 전면에 제1 도전층을 형성하는 단계, 상기 제1 도전층을 소정의 깊이까지 식각하고 평탄화하는단계, 상기 트랜지스터의 드레인상에 콘택홀을 형성하는 단계, 상기 결과물전면에 콘택홀을 매립하면서 제2 도전층을 형성하는 단계, 상기 제2 도전층 전면에 제3 도전층을 형성하는 단계 및 상기 제3, 제2 및 제1 도전층을 패터닝하여 비트라인을 형성하는 단계를 포함한다.The present invention discloses a method of forming a bit line of a semiconductor device on a planarized surface of a first conductive layer. A bit line forming method of the present invention comprises the steps of: forming a transistor on a semiconductor substrate, forming a first insulating film on the semiconductor substrate on which the transistor is formed, forming a first conductive layer on the entire surface of the first insulating film, Etching and planarizing a first conductive layer to a predetermined depth, forming a contact hole on the drain of the transistor, forming a second conductive layer while filling the contact hole in the entire surface of the resultant, and forming the second conductive layer. Forming a third conductive layer on the entire surface of the layer and patterning the third, second and first conductive layers to form a bit line.

본 발명에 의하면 비트라인의 패터닝이 쉽고 또한 평탄화과정에서 열을 받지 않으므로 트랜지스터의 펀치쓰루(punchthrough) 특성을 개선할 수 있다. 그리고 층간산화막을 한번만 형성함으로써 후속공정에서 콘택형성시 양호한 에스펙트 비(Aspect ratio)를 갖는다.According to the present invention, the bit line is easily patterned and heat is not received during the planarization process, thereby improving punchthrough characteristics of the transistor. In addition, since the interlayer oxide film is formed only once, it has a good aspect ratio during contact formation in a subsequent process.

Description

반도체 장치의 비트라인 형성방법Bit line formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2e도 내지 제2f도는 본 발명의 제1 실시예에 의한 반도체 장치의 비트라인 형성방법을 단개별로 나타낸 도면들이다.2E to 2F are diagrams illustrating a bit line forming method of a semiconductor device in accordance with a first embodiment of the present invention.

Claims (4)

반도체기판상에 트랜지스터를 형성하는 단계; 상기 트랜지스터가 형성된 반도체기판 전면에 제1 절연막을 형성하는 단계 ; 상기 제1 절연막 전면에 제1 도전층을 형성하는 단계 ; 상기 제1 도전층을 소정의 깊이까지 식각하고 평탄화하는 단계 ; 상기 트랜지스터의 드레인영역에 콘택홀을 형성하는 단계 ; 상기 결과물전면에 콘택홀을 매립하면서 제2도전층을 형성하는 단계 ; 상기 제2 도전층전면에 제3 도전층을 형성하는 단계 ; 및 상기 제3, 제2 및 제1 도전층을 패터닝하여 비트라인을 형성하는 단계를 포함하는 것을 특징으로 하는 비트라인 형성방법.Forming a transistor on the semiconductor substrate; Forming a first insulating film on an entire surface of the semiconductor substrate on which the transistor is formed; Forming a first conductive layer over the entire first insulating film; Etching and planarizing the first conductive layer to a predetermined depth; Forming a contact hole in the drain region of the transistor; Forming a second conductive layer by filling a contact hole in the entire surface of the resultant material; Forming a third conductive layer on the entire surface of the second conductive layer; And patterning the third, second and first conductive layers to form a bit line. 제1항에 있어서, 상기 제1 도전층을 소정의 깊이까지 식각하고 평탄화하는 단계는, 상기 제1 도전층을 상기 게이트상부에 있는 제1 절연막이 노출될 때 까지 실시하는 단계 또는 상기 제1 절연막상의 일정높이까지만 실시하는단계중 어느 하나를 포함하는 것을 특징으로 하는 반도체 장치의 비트라인 형성방법.The method of claim 1, wherein etching and planarizing the first conductive layer to a predetermined depth comprises: performing the first conductive layer until the first insulating layer on the gate is exposed or the first insulating layer. And forming one of the steps up to a predetermined height of the image. 제1항에 있어서, 상기 콘택홀을 형성하는 단계는 상기 제1 도전층상에 포토레지스트 패턴을 형성하는 단계와 상기 포토레지스트 패턴을 이용하여 트랜지스터의 드레인영역에 형성된 상기 제1 도전층 및 제1 절연막을 한번에 식각하여 형성하는 단계 또는 상기 제1 도전층상에 포토레지스트 패턴을 형성하는 단계와 상기 포토레지스트 패턴을 이용하여제1 도전층을 식각한 다음 포토레지스트 패턴을 제거하는 단계와 상기 제1 도전층을 마스크로 하여 상기 드레인영역에 형성된 제1 절연막을 제거하는 단계중 어느 한 단계를 더 포함하고 있는 것을 특징으로 하는 반도체 장치의 비트라인 형성방법.The method of claim 1, wherein forming the contact hole comprises forming a photoresist pattern on the first conductive layer and using the photoresist pattern in the drain region of the transistor. Etching to form at one time or forming a photoresist pattern on the first conductive layer, etching the first conductive layer using the photoresist pattern, and then removing the photoresist pattern and the first conductive layer And removing any of the first insulating films formed in the drain region using the mask as a mask. 제3항에 있어서, 상기 콘택홀의 직경은 상기 포토레지스트 패턴에 열을 가하여 패턴의 가장자리를 확장시킴으로써 또는 포토레지스트 패턴의 측벽에 스페이서를 형성함으로써 작게 형성하는 것을 특징으로 하는 반도체 장치의 비트라인 형성방법.The method of claim 3, wherein the diameter of the contact hole is reduced by applying heat to the photoresist pattern to extend an edge of the pattern or by forming a spacer on a sidewall of the photoresist pattern. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950012468A 1995-05-18 1995-05-18 Bit line manufacturing method for semiconductor device KR0151047B1 (en)

Priority Applications (1)

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KR1019950012468A KR0151047B1 (en) 1995-05-18 1995-05-18 Bit line manufacturing method for semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950012468A KR0151047B1 (en) 1995-05-18 1995-05-18 Bit line manufacturing method for semiconductor device

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KR960043118A true KR960043118A (en) 1996-12-23
KR0151047B1 KR0151047B1 (en) 1998-10-01

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KR100465789B1 (en) 2002-01-25 2005-01-13 삼성전자주식회사 Combining Device for Electric Apparatuses including Display Apparatus

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