KR20070064092A - Method for fabricating metal line of semiconductor device - Google Patents

Method for fabricating metal line of semiconductor device Download PDF

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Publication number
KR20070064092A
KR20070064092A KR1020050124643A KR20050124643A KR20070064092A KR 20070064092 A KR20070064092 A KR 20070064092A KR 1020050124643 A KR1020050124643 A KR 1020050124643A KR 20050124643 A KR20050124643 A KR 20050124643A KR 20070064092 A KR20070064092 A KR 20070064092A
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South Korea
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trench
metal wiring
semiconductor device
forming
film
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KR1020050124643A
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Korean (ko)
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황상일
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동부일렉트로닉스 주식회사
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Priority to KR1020050124643A priority Critical patent/KR20070064092A/en
Publication of KR20070064092A publication Critical patent/KR20070064092A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Abstract

A method for forming a metal wiring in a semiconductor device is provided to prevent formation of a micro trench around a corner of a trench by forming the trench, in which the metal wiring is formed, through negative photosensitive film exposure and development. A photosensitive film is formed on a lower structure(21), and then is selectively patterned to form a trench. A metal wiring material is formed on the entire surface of the substrate until the trench is filled. The metal wiring material is planarized to form a metal wiring buried in the trench, and the photosensitive film is selectively removed. An interlayer dielectric(25) is formed on the entire surface of the substrate, and then is planarized until the metal wiring is exposed.

Description

반도체소자의 금속 배선 제조 방법{METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE}METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE

도 1은 종래 기술에 따른 듀얼다마신 공정을 이용한 금속배선 제조 방법을 간략히 도시한 도면, 1 is a view briefly showing a metal wire manufacturing method using a dual damascene process according to the prior art,

도 2는 종래 기술에 따른 마이크로 트렌치를 나타낸 도면,2 is a view showing a micro trench according to the prior art,

도 3a 내지 도 3d는 본 발명의 실시 예에 따른 금속배선의 형성 방법을 도시한 도면.3A to 3D are views illustrating a method of forming a metal wire according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 하부 구조물 22 : 네가티브 감광막21: substructure 22: negative photosensitive film

22b : 트렌치 23 : 트렌치 마스크22b: trench 23: trench mask

24 : 구리배선 25 : 층간 절연막24 copper wiring 25 interlayer insulating film

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체소자의 금속배선 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing metal wiring of a semiconductor device.

도 1은 종래 기술에 따른 듀얼다마신 공정을 이용한 금속배선 제조 방법을 간략히 도시한 도면이고, 도 2는 종래 기술에 따른 마이크로 트렌치를 나타낸 도면이다.1 is a view briefly showing a method for manufacturing a metal wiring using a dual damascene process according to the prior art, Figure 2 is a view showing a micro trench according to the prior art.

도 1을 참조하면, 하부 구조물(11)을 형성한 후, 하부 구조물(11) 상에 식각 저지막(12)을 형성한다. Referring to FIG. 1, after forming the lower structure 11, an etch stop layer 12 is formed on the lower structure 11.

이어서, 식각 저지막(12) 상에 층간 절연막(ILD, 13)을 형성한다.Subsequently, interlayer insulating films ILD and 13 are formed on the etch stop layer 12.

이어서, 층간 절연막(13)을 선택적으로 식각하여 트렌치 형태의 듀얼다마신 패턴(14)을 형성한다.Subsequently, the interlayer insulating layer 13 is selectively etched to form a trench-type dual damascene pattern 14.

이어서, 듀얼다마신 패턴(14)에 매립되는 금속배선(15)을 형성한다.Subsequently, the metal wiring 15 embedded in the dual damascene pattern 14 is formed.

종래 기술의 듀얼다마신 공정에 있어서, 식각 저지막(12)으로 SiC, SiN 등이 사용된다. 하지만, 이들 물질은 유전율이 높다는 단점이 있다.In the dual damascene process of the prior art, SiC, SiN, or the like is used as the etch stop film 12. However, these materials have a disadvantage of high dielectric constant.

이를 해결하기 위해 식각 저지막(12)을 사용하지 않을 경우에는, 도 2에 도시된 것처럼, 듀얼다마신 패턴, 특히 트렌치의 모서리가 식각이 더 되는 마이크로 트렌치(Micro trench)가 형성되는 문제가 있다. In order to solve this problem, when the etch stop layer 12 is not used, as shown in FIG. 2, a dual damascene pattern, in particular, a micro trench in which the corners of the trench are etched is formed. .

이러한 마이크로 트렌치는 금속배선의 신뢰성을 저하시킨다.Such micro trenches reduce the reliability of the metallization.

본 발명은 상기 종래 기술의 문제점을 해결하기 위한 것으로, 듀얼다마신 공정시 트렌치의 모서리에 마이크로 트렌치가 형성되는 것을 방지할 수 있는 반도체소자의 금속배선 제조 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for manufacturing a metal wiring of a semiconductor device that can prevent the formation of micro trenches at the corners of the trench during the dual damascene process.

상기 목적을 달성하기 위한 본 발명의 금속배선 제조 방법은 하부 구조물 상 부에 감광막을 형성하는 단계와, 상기 감광막을 선택적으로 패터닝하여 트렌치를 형성하는 단계와, 상기 트렌치를 채울 때까지 전면에 금속 배선용 물질을 형성하는 단계와, 상기 금속 배선용 물질을 평탄화하여 상기 트렌치 내부에 매립되는 금속배선을 형성하는 단계와, 상기 감광막을 선택적으로 제거하는 단계와, 상기 금속배선을 포함한 전면에 층간 절연막을 형성하는 단계와, 상기 금속배선의 표면이 노출될 때까지 상기 층간 절연막을 평탄화시키는 단계를 포함하는 것을 특징으로 한다.Metal wire manufacturing method of the present invention for achieving the above object is a step of forming a photoresist film on the lower structure, the step of selectively patterning the photosensitive film to form a trench, and for the metal wiring on the front until filling the trench Forming a material, planarizing the metallization material to form a metal wiring embedded in the trench, selectively removing the photosensitive film, and forming an interlayer insulating film on the entire surface including the metal wiring And planarizing the interlayer insulating film until the surface of the metal wiring is exposed.

바람직하게, 상기 감광막은 네가티브 감광막으로 형성하는 것을 특징으로 하며, 상기 트렌치를 형성하는 단계는 상기 네가티브 감광막을 역으로 크롬 처리된 트렌치 마스크를 이용하여 노광하는 단계와, 상기 노광 부분을 잔류시키고 나머지 부분을 제거하는 현상을 통해 상기 트렌치를 형성하는 단계를 포함하는 것을 특징으로 한다.Preferably, the photoresist film is formed as a negative photoresist film, and the forming of the trench may include exposing the negative photoresist film using a reversely chromed trench mask, and leaving the exposed portion and the remaining portion. Forming the trench through the phenomenon of removing the.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시 예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

후술하는 실시 예는 듀얼다마신 공정시 식각 저지막을 사용하지 않으면서도 마이크로 트렌치의 형성을 방지할 수 있는 방법을 제안한다.An embodiment to be described later proposes a method for preventing the formation of micro trenches without using an etch stop layer during the dual damascene process.

도 3a 내지 도 3d는 본 발명의 실시 예에 따른 금속배선의 형성 방법을 도시한 도면이다.3A to 3D are views illustrating a method of forming metal wirings according to an embodiment of the present invention.

도 3a에 도시된 바와 같이, 하부 구조물(21) 상에 네가티브 감광막(Negative PR, 22)을 도포한다. As shown in FIG. 3A, a negative PR 22 is applied onto the lower structure 21.

여기서, 네가티브 감광막(22)의 두께는 후속 금속배선이 형성될 트렌치의 깊이 타겟보다 300∼500Å 더 크게 한다.Here, the thickness of the negative photoresist film 22 is made 300 to 500 kPa larger than the depth target of the trench where subsequent metallization will be formed.

이어서, 트렌치 마스크(23)를 이용한 노광 공정을 진행한 후 현상하여 도 3b에 도시된 바와 같이, 네가티브 감광막 패턴(22a)을 형성한다. 여기서, 트렌치 마스크(23)는 역으로(reverse) 크롬(chrome) 처리된 마스크이다.Subsequently, the exposure process using the trench mask 23 is performed and then developed to form a negative photosensitive film pattern 22a as shown in FIG. 3B. Here, the trench mask 23 is a reversed chrome mask.

잘 알려진 것처럼, 네가티브 감광막(22)의 특성상 빛에 노출된 부분이 현상에 의해 제거되지 않으므로, 네가티브 감광막 패턴(22a)에 형성되는 트렌치(Trench, 22b)는 금속배선이 형성될 영역으로서, 라인 형태의 트렌치이다.As is well known, since the exposed portion of the negative photoresist film 22 is not removed by the development, the trench 22b formed in the negative photoresist pattern 22a is a region in which metal wiring is to be formed, and is in the form of a line. Is a trench.

위와 같이, 금속배선이 형성될 트렌치(22b)를 네가티브 감광막 도포, 노광 및 현상을 통해 형성하므로, 트렌치(22b)의 모서리에서 마이크로 트렌치가 발생되지 않는다.As described above, since the trench 22b in which the metal wiring is to be formed is formed through negative photosensitive film coating, exposure, and development, micro trenches are not generated at the corners of the trench 22b.

도 3c에 도시된 바와 같이, 네가티브 감광막 패턴(22a)의 트렌치(22b)를 채울 때까지 전면에 구리막(24)을 증착한 후, 네가티브 감광막 패턴(22a)의 표면이 드러날 때까지 구리막(24)을 평탄화한다. 이로써, 트렌치(22b) 내부에 라인 형태의 구리막(24)이 매립되고, 이하 구리막(24)을 '구리배선(24)'이라고 한다.As shown in FIG. 3C, after the copper film 24 is deposited on the entire surface until the trench 22b of the negative photoresist pattern 22a is filled, the copper film 24 is exposed until the surface of the negative photoresist pattern 22a is exposed. Flatten 24). Thereby, the copper film 24 of a line form is embedded in the trench 22b, and the copper film 24 is called "copper wiring 24" hereafter.

상기 구리배선(24)을 형성하기 위한 구리막의 평탄화는 CMP(Chemical Mechanical Polishing) 공정을 이용한다.The planarization of the copper film for forming the copper wiring 24 uses a chemical mechanical polishing (CMP) process.

도 3d에 도시된 바와 같이, 현상을 통해 네가티브 감광막 패턴(22a)을 스트립한 후 세정을 진행한다. 이를 통해, 구리배선(24)이 노출되게 된다.As shown in FIG. 3D, the negative photosensitive film pattern 22a is stripped through development and then cleaned. Through this, the copper wiring 24 is exposed.

상기 네가티브 감광막 패턴(22a)의 스트립은 애셔(asher)를 이용하며, 네가 티브 감광막(22a)은 금속배선간 절연물질로 사용하기 어려우므로 스트립을 통해 제거해주는 것이다.The strip of the negative photoresist pattern 22a uses an asher, and since the negative photoresist 22a is difficult to use as an insulating material between metal lines, the strip is removed through the strip.

이후, 구리배선(24)을 포함한 전면에 층간 절연막(25)을 증착한 후 CMP를 통해 평탄화함으로써, 반도체소자의 금속배선을 완성한다.Thereafter, the interlayer insulating film 25 is deposited on the entire surface including the copper wiring 24, and then planarized through CMP, thereby completing the metal wiring of the semiconductor device.

본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었으나, 상기한 실시 예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 네가티브 감광막 노광 및 현상을 통해 금속배선이 형성될 트렌치를 형성하므로 마이크로 트렌치가 근본적으로 발생하지 않아 금속배선의 신뢰성을 향상시킬 수 있는 효과가 있다.The present invention described above forms a trench in which metal wiring is to be formed through exposure and development of negative photoresist, so that micro trenches are not fundamentally generated, thereby improving reliability of metal wiring.

Claims (7)

하부 구조물 상부에 감광막을 형성하는 단계와,Forming a photoresist film on the lower structure; 상기 감광막을 선택적으로 패터닝하여 트렌치를 형성하는 단계와,Selectively patterning the photoresist to form a trench; 상기 트렌치를 채울 때까지 전면에 금속 배선용 물질을 형성하는 단계와,Forming a metal wiring material on the front surface until the trench is filled; 상기 금속 배선용 물질을 평탄화하여 상기 트렌치 내부에 매립되는 금속배선을 형성하는 단계와,Planarizing the metal wiring material to form a metal wiring embedded in the trench; 상기 감광막을 선택적으로 제거하는 단계와,Selectively removing the photoresist; 상기 금속배선을 포함한 전면에 층간 절연막을 형성하는 단계와,Forming an interlayer insulating film on the entire surface including the metal wiring; 상기 금속배선의 표면이 노출될 때까지 상기 층간 절연막을 평탄화시키는 단계Planarizing the interlayer insulating film until the surface of the metal wiring is exposed; 를 포함하는 반도체소자의 금속배선 제조 방법.Metal wire manufacturing method of a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 감광막은, 네가티브 감광막으로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.The photosensitive film is a metal wiring manufacturing method of a semiconductor device, characterized in that formed as a negative photosensitive film. 제 2 항에 있어서,The method of claim 2, 상기 트렌치를 형성하는 단계는,Forming the trench, 상기 네가티브 감광막을 역으로 크롬 처리된 트렌치 마스크를 이용하여 노광 하는 단계와,Exposing the negative photoresist with a reversely chromed trench mask; 상기 노광 부분을 잔류시키고 나머지 부분을 제거하는 현상을 통해 상기 트렌치를 형성하는 단계Forming the trench through the phenomenon of remaining the exposed portion and removing the remaining portion 를 포함하는 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.Metal wire manufacturing method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 감광막은, The photosensitive film, 상기 트렌치의 깊이 타겟보다 300∼500Å 더 큰 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.The metal wiring manufacturing method of a semiconductor device, characterized in that formed in a thickness 300 to 500 Å greater than the depth target of the trench. 제 1 항에 있어서,The method of claim 1, 상기 금속배선용 물질을 평탄화하여 상기 트렌치 내부에 매립되는 금속 배선을 형성하는 단계는, CMP 공정으로 진행하는 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.Forming a metal line embedded in the trench by planarizing the metal wiring material, wherein the metal wire manufacturing method of the semiconductor device is performed. 제 1 항에 있어서,The method of claim 1, 상기 감광막을 선택적으로 제거하는 단계는, 애셔를 이용하는 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.In the step of selectively removing the photosensitive film, a metal wire manufacturing method of a semiconductor device, characterized in that using an asher. 제 1 항 내지 제 6 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 6, 상기 금속배선은 구리막으로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.The metal wiring is a metal wiring manufacturing method of a semiconductor device, characterized in that formed by a copper film.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100972888B1 (en) * 2008-09-18 2010-07-28 주식회사 동부하이텍 Planarization method of intermetal dielectric for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100972888B1 (en) * 2008-09-18 2010-07-28 주식회사 동부하이텍 Planarization method of intermetal dielectric for semiconductor device

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