JP2006344815A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which suppresses the variation of a pattern dimension and forms dual damascene wiring at a high yield. <P>SOLUTION: The method comprises a step of forming an insulation film on a semiconductor substrate, a step of forming at least upper and lower layer hard masks on the insulation film, a step of forming a lower layer mask and a stopper layer on the upper layer hard mask in this order, a step of forming a wiring trench pattern on the stopper layer and the lower layer mask, a step of transferring the wiring trench pattern to the upper layer hard mask with the stopper layer left on the lower layer mask, a step of forming a burying organic film on the entire surface, a step of exposing the stopper layer by CMP with the burying organic film left in the wiring trench pattern, a step of removing the stopper layer to expose the lower layer mask, a step of forming an intermediate layer and a resist film on the lower layer mask and the burying organic film in this order, and a step of pattern-exposing the resist film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a multilayer resist process.

  In recent years, with the miniaturization of semiconductor devices, an ArF excimer laser is used as a light source in order to expose a fine pattern with high resolution, resulting in a problem that the depth of focus is lowered. In order to cope with this, it is essential to planarize the base using a chemical mechanical polishing (CMP) technique. This requirement is becoming more severe as miniaturization progresses.

  For example, when manufacturing a dual damascene structure wiring using a grooved hard mask method, the resist film thickness varies due to the step of the wiring groove pattern during exposure of the connection hole pattern, and the dimensions Variations are caused. In order to solve this problem, it has been proposed to pattern the connection holes using a multilayer resist method comprising a three-layer or two-layer laminated film.

  However, if the lower resist film thickness is increased in the multilayer resist method, an increase in dimensional variation and an increase in throughput occur during pattern exposure. For this reason, the lower resist film cannot be formed excessively thick, and it is difficult to completely eliminate the step. In order to eliminate the step, a method of forming a mask layer on the step and planarizing the mask layer by CMP has been proposed (see, for example, Patent Document 1).

When the lower resist film is planarized by CMP, it is difficult to control the remaining resist film after CMP. In CMP, a difference occurs in the in-plane polishing rate, resulting in variations in film thickness after polishing. Although it is necessary to make the polishing amount constant in order to obtain a desired resist film thickness after CMP, when controlled by the polishing time, the resist residual film varies from wafer to wafer due to the change in polishing rate over time. (For example, refer to Patent Document 2). Since the film thickness variation of the lower layer resist leads to dimensional variation during pattern transfer, it is required to reduce it as much as possible.
JP 2004-152997 A JP 2002-26122 A

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a dual damascene wiring with a high yield while suppressing variations in pattern dimensions.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming an insulating film over a semiconductor substrate;
Sequentially forming at least a lower layer and an upper layer hard mask on the insulating film;
A step of sequentially forming a lower layer mask and a stopper layer on the upper layer hard mask;
Forming a wiring groove pattern in the stopper layer and the lower layer mask to expose the upper layer hard mask;
Transferring the wiring groove pattern to the upper hard mask while leaving the stopper layer on the lower mask;
A step of forming a buried organic film in the wiring groove pattern and on the stopper layer after transferring the wiring groove pattern to the upper hard mask;
Performing CMP to remove the embedded organic film on the stopper layer, leaving the embedded organic film in the wiring trench pattern, and exposing the stopper layer;
Removing the exposed stopper layer to expose the underlying mask;
Forming an intermediate layer on the lower layer mask and the embedded organic film;
Forming a resist film on the intermediate layer;
And a step of pattern exposing the resist film.

  According to one embodiment of the present invention, there is provided a method of manufacturing a semiconductor device capable of forming dual damascene wiring with high yield while suppressing variation in pattern dimensions.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 14 show a method for manufacturing a semiconductor device according to the embodiment.
First, a barrier layer 11 for preventing diffusion of Cu, a first insulating film 12 as an interlayer insulating film, and a second insulating film 13 on a semiconductor substrate 10 in which a lower layer wiring 40 is embedded in an insulating film 41. Were sequentially formed. The barrier layer 11 was formed by depositing a silicon nitride film with a thickness of 35 nm by a plasma enhancement chemical vapor deposition (PE-CVD) method. As the first insulating film 12, a SiOC film was deposited with a thickness of 145 nm by a PE-CVD method, and the second insulating film 13 was formed by forming an organic film with a thickness of 100 nm by a coating method. .

  Examples of the material of the SiOC film used for the first insulating film 12 include black diamond (manufactured by Applied Materials), coral (manufactured by Novellus), and aurora (manufactured by ASM). . The first insulating film can also be formed by applying methylsiloxane. Examples of the material of the second insulating film 13 include SiLK (manufactured by Dow Chemical Co.) and FLARE (manufactured by Allied Signal). The film thickness of the first insulating film 12 can be changed within a range of 50 to 200 nm, and the film thickness of the second insulating film 13 can be changed within a range of 50 to 200 nm.

  On the second insulating film 13, a silicon oxide film is formed as a first hard mask 14 in a thickness of 150 nm, a silicon nitride film as a second hard mask 15 is formed in a thickness of 50 nm, and a silicon oxide film is formed as a third hard mask 16 in a thickness of 50 nm. did. The film thicknesses of the first, second, and third hard masks can be determined as appropriate and are not limited thereto. For example, the film thickness of the first hard mask 14 as the lower hard mask can be changed within a range of 100 to 200 nm, and the film thickness of the second hard mask 15 as the intermediate hard mask is 50 to 100 nm. It can be changed within the range. The film thickness of the third hard mask 15 as the upper hard mask can be changed within a range of 50 to 100 nm. Since the first hard mask becomes a Cu-CMP stopper film when forming the Cu wiring, the material of these hard masks can be appropriately selected as long as the following conditions are satisfied. That is, the second hard mask has a selection ratio as an etching mask when forming a wiring pattern on the first hard mask, and the third hard mask forms a wiring pattern on the second hard mask. In doing so, it has a selection ratio as an etching mask.

  In the illustrated example, the triple hard mask is applied, but a dual hard mask can also be applied. In this case, the same process as in the case of the triple hard mask may be performed except that the third hard mask 16 is omitted. That is, the first hard mask 14 as the lower layer hard mask and the second hard mask 15 as the upper layer hard mask are formed by the method as described above. Thereafter, using the second hard mask 15 as an upper layer hard mask, the same processing as in the case of applying the following triple hard mask is performed.

On the third hard mask 16, a lower layer mask 25 and a stopper layer 26 were sequentially formed, and a resist pattern 27 was provided as shown in FIG.
As the lower layer mask 25, for example, an organic film such as a novolac resin, polyarylene, or polycyclic aromatic compound can be applied and formed. Further, a carbon film formed by plasma CVD may be used as the lower layer mask 25. The film thickness of the lower layer mask 25 is required to be sufficient to function as a mask when transferring the connection hole pattern to the second hard mask 15 and the first hard mask 14 in a later step. For example, when the total film thickness of the first hard mask 14 and the second hard mask 15 is 100 to 300 nm, the film thickness of the lower layer mask 25 is desirably 100 nm or more. If the lower layer mask 25 is too thick, the lower layer mask 25 remains after the connection hole is formed in the second insulating film 13. The remaining lower layer mask must be removed by overetching or the like. Therefore, in addition to the film thickness consumed by processing the second insulating film 13, the total film thickness consumed when processing the first hard mask 14 and the second hard mask 15 is the lower layer mask 25. This is the upper limit of the film thickness. Therefore, the film thickness of the lower layer mask 25 is desirably 100 to 300 nm.

  Here, IX370G (manufactured by JSR) was applied by spin coating, and prebaked at 180 ° C. for 60 seconds. Further, post-baking was performed at 300 ° C. for 60 seconds to form a lower layer mask 25 having a thickness of 200 nm.

The stopper layer 26 on the lower layer mask 25 can be formed by, for example, spin on glass (SOG). This stopper layer 26 is required to remain with a predetermined film thickness after the third hard mask 16 is etched in a later step. For this purpose, the film thickness of the stopper layer 26 is set in consideration of the film thickness of the third hard mask 16 and the etching selection ratio with the third hard mask 16. In the etching, overetching corresponding to 30 to 50% is usually performed with respect to the film thickness to be processed in consideration of film thickness variation and etching rate variation. Assuming that the thickness of the third hard mask 16 is (T ₁ ), an etching with a thickness equivalent to (1.5T ₁ ) is required when 50% overetching is assumed. Furthermore, if the etching selectivity of the stopper layer 26 with respect to the third hard mask 16 is S, the etched film thickness of the stopper layer 26 is (1.5T ₁ × S).

That is, in order for the stopper layer 26 to remain after the etching of the third hard mask 16, the film thickness (T ₂ ) of the stopper layer 26 satisfies the condition that T ₂ > (1.5T ₁ × S). It is required to satisfy. When the thickness of the stopper layer 26 remaining after the etching of the third hard mask 16 is thicker than 50 nm, an organic film is embedded in a later process and used as a stopper for planarization by CMP, and then the stopper When removing the film, there may be a disadvantage that a step corresponding to the remaining film thickness occurs. In order to avoid this, it is desirable to keep the film thickness (T ₂ ) of the stopper layer 26 at about 200 nm at the maximum.

  Here, SOG was formed by a resist coating method, and baking was performed at 300 ° C. for 60 seconds to form a stopper layer 26 having a thickness of 110 nm. The selection ratio between the third hard mask 16 made of a silicon oxide film and the stopper layer 26 made of SOG is approximately 1. Since the SOG film thickness of the stopper layer 26 is 110 nm, after etching the silicon oxide film of the third hard mask 16 by 50 nm, the stopper layer 26 (SOG film) has a film thickness of about 35 nm on the lower layer mask 25. Will remain.

  On the stopper layer 26, a chemically amplified resist for ArF excimer laser (ArF series manufactured by JSR) was applied as a photoresist to form a resist film having a thickness of 150 nm. As shown in FIG. 1, a wiring groove pattern 17a is provided on the resist film by lithography to form a resist pattern 27. The width of the wiring groove pattern 17a was set to two types of 90 nm and 3 μm.

The stopper layer 26 was etched using the resist pattern 27 as a mask, and the wiring groove pattern 17 a was transferred to the stopper layer 26. Here, etching was performed using a magnetron RIE apparatus under the conditions of CHF ₃ / O ₂ = 60/10 sccm, 50 mTorr, and 500 W. In the subsequent processes, a magnetron RIE apparatus is used for etching. Further, etching is performed under the conditions of N ₂ / O ₂ = 90/10 sccm, 30 mTorr, 400 W, and the wiring groove pattern 17 a is transferred to the lower layer mask 25 as shown in FIG. 2, and third wiring is formed on the bottom of the wiring groove pattern 17 a. The hard mask 16 was exposed. The resist pattern 27 provided on the stopper layer 26 is made of an organic material like the lower layer mask 25 and has a selectivity of about 1. For this reason, the resist pattern 27 is removed during the etching of the lower layer mask 25, and a multilayer mask 31 composed of the patterned lower layer mask 25 and the patterned stopper layer 26 is obtained.

Using this multilayer mask 31, the wiring groove pattern 17a is transferred to the third hard mask 16 as shown in FIG. 3, and the second hard mask 15 is exposed at the bottom of the wiring groove pattern 17a. Here, etching was performed under the conditions of 20 ° C., C ₄ F ₈ / O ₂ / Ar = 16/20/200 sccm, 40 mTorr, 1500 W. As already described, since the stopper layer 26 is formed with a sufficient film thickness, it remains on the lower layer mask 25 with a film thickness of about 35 nm after the third hard mask 16 is etched.

  Next, as shown in FIG. 4, a buried organic film 28 was formed on the entire surface including the inside of the wiring groove pattern 17a. As a material of the embedded organic film 28, a coating material having excellent embeddability is desirable. In the present embodiment, the embedded organic film 28 is formed using a resist mainly composed of novolak resin, IX370G (manufactured by JSR). The embedded organic film 28 may be formed of an organic compound containing polyarylene as a main component. The embedded organic film 28 is required to completely fill the concave portion formed of the wiring groove pattern 17a. The film thickness of the embedded organic film 28 only needs to exceed the sum of the remaining film thickness of the stopper layer 26, the film thickness of the lower layer mask 25, and the film thickness of the third hard mask 16.

  The embedded organic film 28 was subjected to CMP to expose the stopper layer 26 as shown in FIG. Polishing was performed using EPO-222 manufactured by Ebara Seisakusho while supplying a slurry in which alumina was dispersed in pure water at a concentration of 1 wt% as abrasive particles. When the polishing is finished when the stopper layer 26 is exposed, the embedded organic film 28 is embedded in the wiring groove pattern 17a to flatten the surface. At this time, it is preferable that the stopper layer 26 is overpolished to some extent to completely remove the embedded organic film 28 on the stopper 26 layer. Since the stopper layer 26 is made of SOG, its polishing rate is slower than that of the resist constituting the embedded organic film 28. Therefore, the remaining film can be controlled to some extent by the polishing time. Here, over-polishing of 20 nm was performed. As a result, as shown in FIG. 5, the thickness of the stopper layer 26 decreased to about 15 nm.

Subsequently, the remaining stopper layer 26 was removed by etching, and the lower layer mask 25 was exposed as shown in FIG. By using etching conditions having a high selectivity with respect to the organic films such as the lower layer mask 25 and the embedded organic film 28, the stopper layer 26 can be removed without substantially etching these organic films. Specifically, there is a method of performing wet etching with a diluted HF aqueous solution, washing with water and then spin drying. Alternatively, by using a dry etching technique, the stopper layer 26 can be removed by etching without substantially etching the organic film such as the lower layer mask 25. For example, this can be achieved by performing etching under the conditions of C ₄ F ₈ / CO / Ar = 16/150/200 sccm, 40 mTorr, 500 W. Since the etching selectivity between the silicon oxide film of the stopper layer 26 and the resist which is an organic film is 40 or more, the stopper layer 26 can be removed without etching the organic film such as the lower layer mask 25 or the like.

  After the stopper layer 26 is removed by etching, the embedded organic film 28 embedded in the wiring groove pattern 17a and the lower layer mask 25 below the stopper layer 26 remain, and the boundary between the embedded organic film 28 and the lower layer mask 25 remains. As a result, a step of about 15 nm corresponding to the remaining film thickness of the stopper layer 26 occurs. If it is about 20 nm or less, even if a step is generated, there is substantially no influence, but it is desirable that the step is small.

When dry etching of the stopper layer 26 under the above-described conditions, if the etching selectivity is reduced to 10 or less by adding a small amount of O ₂ , the lower layer mask 25 is slightly etched, but the embedded organic film 28 and The level difference generated at the boundary with the lower layer mask 25 can be reduced. For example, when the etching selectivity is 5, the embedded organic film 28 in the wiring groove pattern 17a is etched by 3 nm while the remaining 15 nm stopper layer 26 is etched. After the stopper layer 26 is removed by etching, the lower layer mask 25 is exposed. Since the lower layer mask 25 has a selection ratio of about 1 with respect to the buried organic film 28, it is etched back almost uniformly. Even when 100% over-etching is performed, the amount of over-etching of the embedded organic film 28 is 3 nm, which is in a range that does not affect. When such a method is adopted, the step difference at the boundary between the embedded organic film 28 and the lower layer mask 25 is reduced to 12 nm, and the flatness can be further improved.

  On the lower mask 25 and the embedded organic film 28, a silicon oxide film having a thickness of 45 nm was provided as shown in FIG. Furthermore, a chemically amplified resist for ArF excimer laser (ArF series manufactured by JSR) was applied as a photoresist to form a resist film with a thickness of 200 nm. A resist pattern 30 was formed on the resist film by providing a connection hole pattern 24a of 90 nmφ by lithography using an ArF excimer laser as a light source. At this time, the loss of the focal depth between the wiring groove pattern with a width of 3 μm and the wiring groove pattern with a width of 90 nm was 10 nm or less. If it is 10 nm or less, the loss of depth of focus has no substantial effect, and it can be considered that there is no variation in resist pattern dimensions.

Subsequently, etching is performed under the conditions of CHF ₃ / O ₂ = 60/10 sccm, 50 mTorr, 500 W to transfer the connection hole pattern 24 a to the intermediate layer 29. Further, N ₂ / O ₂ = 90/10 sccm, 30 mTorr, 400 W Etching was performed under the conditions described above to transfer the connection hole pattern 24 a to the embedded organic film 28. As a result, as shown in FIG. 8, the second hard mask 15 was exposed at the bottom of the connection hole pattern 24a, and the resist pattern 30 on the intermediate layer 29 was removed. The resist pattern 30 is made of the same organic material as that of the embedded organic film 28 and has a selection ratio of about 1. Therefore, the resist pattern 30 is removed during the etching of the embedded organic film 28.

Thereafter, etching is performed under the conditions of C ₄ F ₈ / O ₂ / Ar = 16/20/200 sccm, 40 mTorr, 1500 W, and connected to the second hard mask 15 and the first hard mask 14 as shown in FIG. The hole pattern 24a was transferred. In this etching, the intermediate layer 29 was also removed at the same time under the condition that the etching selection ratio between the intermediate layer 29 and the second hard mask 15 and the first hard mask 14 was about 1. By performing overetching, the lower layer mask 25 and the embedded organic film 28 are etched back, and the film thickness of the lower layer mask 25 is reduced to about 150 nm.

Further, etching was performed under the conditions of NH ₃ = 200 sccm, 10 mTorr, 500 W, 0 ° C., the second insulating film 13 was processed as shown in FIG. 10, and the connection hole pattern 24 a was transferred. Similar to the second insulating film 13, the lower layer mask 25 and the embedded organic film 28 made of an organic material are removed during this etching.

When the organic film such as the lower layer mask 25 and the embedded organic film 28 remains, the organic film cannot be processed by O ₂ plasma ashing which is a resist stripping technique usually used for removing the organic film. This is because the second insulating film 13, which is also an organic film, is exposed on the side surface of the connection hole pattern 24 a and is etched by O radicals. When the film thickness of the organic film such as the lower layer mask 25 and the embedded organic film 28 is significantly thicker than that of the second insulating film 13, such organic film is removed even after the etching of the second insulating film 13 is completed. Over-etching is required. Although the damage in the second insulating film 13 in this case is not as great as that in the above-described plasma ashing, the diameter of the connection hole pattern 24a increases as the etching time increases. As a result, there arises a problem that the embedding characteristic at the time of subsequent wiring formation deteriorates. Therefore, it is desirable that the film thickness of the lower layer mask 25 and the embedded organic film 28 is reduced to about 1.5 times or less the film thickness of the second insulating film 13 before this process is performed.

Subsequently, etching is performed under the conditions of CH ₂ F ₂ / Ar / O ₂ = 45/500/30 sccm, 30 mTorr, 400 W, and 20 ° C., and the wiring groove pattern 17a is formed on the second hard mask 15 as shown in FIG. Then, the first hard mask 14 was exposed at the bottom of the wiring groove pattern 17a. The second hard mask 15 is made of a silicon nitride film, and the third hard mask 16 thereon is made of a silicon oxide film. Since the selection ratio between the silicon nitride film and the silicon oxide film is about 3, overetching is required to completely etch the second hard mask 15. As a result, the film thickness of the third hard mask 16 is reduced to about 30 nm.

Next, etching is performed under the conditions of C ₄ F ₈ / O ₂ / Ar = 16/20/200 sccm, 40 mTorr, 1500 W, and the wiring groove 17 is transferred to the first hard mask 14 as shown in FIG. The second insulating film 13 was exposed at the bottom of the wiring trench 17. As a result, a connection hole 24 is formed in the first insulating film 12 as shown, and the third hard mask 16 on the second hard mask 15 is removed by etching.

Further, etching is performed using the first hard mask 14 as a mask under the conditions of CH ₂ F ₂ / Ar / O ₂ = 45/500/30 sccm, 30 mTorr, 400 W, and 20 ° C. As shown in FIG. The barrier layer 11 at the bottom of was removed. By this etching, the second hard mask 15 on the first hard mask 14 is simultaneously removed. Finally, etching is performed under the conditions of NH ₃ = 200 sccm, 10 mTorr, 500 W, 0 ° C. to form a wiring groove 17 in the second insulating film 13 as shown in FIG.

  Through the above steps, a wiring groove structure having the connection hole 24 is formed. According to the method of this embodiment, a fine resist pattern can be formed on the wiring groove pattern having a step without reducing the resolution. As a result, it is possible to eliminate the influence of the step in the wiring groove pattern and form the connection hole pattern with a high depth of focus.

  Thereafter, a barrier layer is formed on the inner surface of the recess such as the connection hole 24 and the wiring groove 17 and Cu is embedded in the recess, and then an excess Cu film and barrier layer on the silicon oxide film as the first hard mask 14 are formed. Is removed by CMP. Thus, a Cu damascene wiring can be formed in the recess to form a dual damascene wiring.

  In this embodiment, a buried organic film is formed on the wiring groove pattern, and this buried organic film is planarized by CMP. Therefore, the loss of the depth of focus at the time of pattern exposure of the connection hole can be suppressed to 10 nm or less, and the dimensional variation of the pattern and the yield are remarkably improved.

For comparison, an attempt was made to form dual damascene wiring by a conventional method.
FIG. 15 is a cross-sectional view showing the steps of the method for manufacturing the semiconductor device of the comparative example, and has the same configuration as FIG. 7 except that the embedded organic film 28 is not provided. At the time of pattern exposure for forming the resist pattern 30 shown in FIG. 15, the loss of the focal depth between the wiring groove pattern having a width of 3 μm and the wiring groove pattern having a width of 90 nm has reached 40 nm. This is due to a step on the surface of the lower layer mask 25. Since the embedded organic film 28 does not exist, a step of the thickness of the third hard mask 16 is generated on the surface of the lower layer mask 25. When the depth of focus exceeded 40 nm, the resist pattern dimensions also varied significantly.

  In the conventional method, when the connection hole pattern 24a is formed on the opening of the wiring groove pattern 17a by lithography, there is a limit to flattening the step by forming a lower layer mask using a multilayer resist process. For this reason, the level | step difference of the wiring groove pattern 17a cannot fully be eliminated, and the fall of a focal depth is unavoidable. As a result, pattern dimensions vary, and dual damascene wiring cannot be formed with a high yield. Such a problem can be avoided by the method according to the embodiment of the present invention.

Process sectional drawing showing the manufacturing method of the semiconductor device concerning embodiment of this invention. Sectional drawing showing the process of following FIG. Sectional drawing showing the process of following FIG. Sectional drawing showing the process of following FIG. Sectional drawing showing the process of following FIG. Sectional drawing showing the process of following FIG. Sectional drawing showing the process of following FIG. Sectional drawing showing the process of following FIG. FIG. 9 is a cross-sectional view illustrating a process following FIG. 8. Sectional drawing showing the process of following FIG. FIG. 11 is a cross-sectional view illustrating a process following FIG. 10. FIG. 12 is a cross-sectional view illustrating a process following FIG. 11. Sectional drawing showing the process of following FIG. FIG. 14 is a cross-sectional view illustrating a process following FIG. 13. Sectional drawing showing the process of the manufacturing method of the semiconductor device of a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate; 11 ... Barrier layer; 12 ... 1st insulating film; 13 ... 2nd insulating film 14 ... 1st hard mask; 15 ... 2nd hard mask 16 ... 3rd hard mask; 17 ... Wiring groove pattern 24a ... Connection hole pattern; 24 ... Connection hole; 25 ... Lower layer mask 26 ... Stopper layer; 27 ... Resist pattern; 28 ... Embedded organic film 29 ... Intermediate layer; 30 ... Resist pattern; Multilayer mask; 40 ... lower layer wiring 41 ... insulating film.

Claims (5)

Forming an insulating film on the semiconductor substrate;
Sequentially forming at least a lower layer and an upper layer hard mask on the insulating film;
A step of sequentially forming a lower layer mask and a stopper layer on the upper layer hard mask;
Forming a wiring groove pattern in the stopper layer and the lower layer mask to expose the upper layer hard mask;
Transferring the wiring groove pattern to the upper hard mask while leaving the stopper layer on the lower mask;
A step of forming a buried organic film in the wiring groove pattern and on the stopper layer after transferring the wiring groove pattern to the upper hard mask;
Performing CMP to remove the embedded organic film on the stopper layer, leaving the embedded organic film in the wiring trench pattern, and exposing the stopper layer;
Removing the exposed stopper layer to expose the underlying mask;
Forming an intermediate layer on the lower layer mask and the embedded organic film;
Forming a resist film on the intermediate layer;
And a step of pattern exposing the resist film. The method for manufacturing a semiconductor device according to claim 1, wherein the stopper layer is formed with a film thickness that satisfies the following conditions.
T ₂ > 1.5T ₁ × S
(Here, T ₂ is the thickness of the stopper layer, T ₁ is the thickness of the upper hard mask, and S is the etching selectivity of the stopper layer to the upper hard mask.)   The method for manufacturing a semiconductor device according to claim 1, wherein the stopper layer is formed with a film thickness of 200 nm or less.   The method for manufacturing a semiconductor device according to claim 1, wherein the stopper layer is removed by dry etching.   5. The method of manufacturing a semiconductor device according to claim 4, wherein when the stopper layer is removed, the lower layer mask and the embedded organic film are etched back.

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