KR100523656B1 - Method for forming metal line in a semiconductor device - Google Patents
Method for forming metal line in a semiconductor device Download PDFInfo
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- KR100523656B1 KR100523656B1 KR10-2003-0061062A KR20030061062A KR100523656B1 KR 100523656 B1 KR100523656 B1 KR 100523656B1 KR 20030061062 A KR20030061062 A KR 20030061062A KR 100523656 B1 KR100523656 B1 KR 100523656B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
반도체 소자의 신뢰성을 향상시킬 수 있는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 반도체 기판 상에 제 1, 2 절연막을 순차적으로 증착하는 단계와, 제 3 절연막에 제 1 반사 방지막을 형성하고, 제 1 반사 방지막의 상부에 포토레지스트 패턴을 마스크로 하여 제 1 반사방지막 및 제 2 절연막을 식각한 후, 제 1 반사 방지막과 제 1 포토레지스트 패턴을 제거하는 단계와, 식각된 제 2 절연막의 상부에 제 3 절연막 및 제 2 반사 방지막을 형성하고, 제 2 반사 방지막의 상부에 포토레지스트 패턴을 마스크로 하여 제 2 반사방지막과 제 3 절연막을 식각하여 트렌치를 형성하는 단계와, 트렌치가 형성된 제 3 절연막 제 2 절연막 및 제 1 절연막을 식각하여 비아홀을 형성하는 단계와, 포토레지스트 패턴과 제 2 반사 방지막을 제거하여 트렌치와 비아홀로 이루어진 듀얼 다마신 패턴을 형성하는 단계와, 듀얼 다마신 패턴에서 비아홀의 측벽에 스페이서를 형성하는 단계와, 스페이서가 형성된 듀얼 다마신 패턴에 전도성 물질을 매립시켜 금속 배선을 형성하는 단계를 포함한다.In the method of forming a metal wire of a semiconductor device according to the present invention which can improve the reliability of a semiconductor device, the method may include sequentially depositing first and second insulating films on a semiconductor substrate, and forming a first antireflection film on a third insulating film. Etching the first antireflection film and the second insulating film using the photoresist pattern as a mask on the first antireflection film, and then removing the first antireflection film and the first photoresist pattern; Forming a trench by forming a third insulating film and a second anti-reflection film, etching the second anti-reflection film and the third insulating film using a photoresist pattern as a mask on the second anti-reflection film, and forming a trench with a trench Forming a via hole by etching the second insulating film and the first insulating film, and removing the photoresist pattern and the second anti-reflection film to form the trench and the via hole. Forming a dual damascene pattern comprising: forming a spacer on a sidewall of the via hole in the dual damascene pattern; and embedding a conductive material in the dual damascene pattern having the spacer to form a metal wiring; .
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 반도체 소자의 전기적 특성을 개선함과 더불어 공정 마진을 확보할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of improving process characteristics and securing process margins.
이하, 도 1a 내지 도 1e를 참조하여 종래 기술에 따른 반도체 소자의 듀얼 다마신 패턴 형성 과정을 설명한다.Hereinafter, a process of forming a dual damascene pattern of a semiconductor device according to the related art will be described with reference to FIGS. 1A to 1E.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 가지 요소(기판 또는 하부 메탈)가 형성된 반도체 기판(1) 상에 제 1 질화막(3), 제 1 산화막(5), 제 2 질화막(7) 및 제 2 산화막(9)을 차려 증착시킨 후에 제 1 마스크를 이용하여 제 1 포토레지스트 패턴(30)을 형성한다.Referring to FIG. 1A, a first nitride film 3, a first oxide film 5, and a second nitride film 7 are formed on a semiconductor substrate 1 on which various elements (substrate or lower metal) for forming a semiconductor device are formed. And after depositing the second oxide film 9, the first photoresist pattern 30 is formed using the first mask.
도 1b를 참조하면, 트렌치를 형성하기 위해 제 1 포토레지스트 패턴(30)에 맞추어서 제 2 산화막(9)을 습식 식각으로 패터닝하여 패터닝된 제 2 산화막(9)을 형성한 다음 제 1 포토레지스트 패턴(30)을 제거함으로써, 제 2 산화막(9)에 트렌치(11a)를 형성한다.Referring to FIG. 1B, the second oxide layer 9 is wet-patterned with the first photoresist pattern 30 to form a trench to form a patterned second oxide layer 9, followed by a first photoresist pattern. By removing the 30, the trench 11a is formed in the second oxide film 9.
도 1c를 참조하면, 도 2의 결과물 상에 유기적(Organic) 제 2 반사 방지막(13)을 형성한 다음 제 2 마스크를 이용하여 제 2 포토레지스트 패턴(40)을 형성한다.Referring to FIG. 1C, an organic second anti-reflection film 13 is formed on the resultant of FIG. 2, and then a second photoresist pattern 40 is formed using a second mask.
이후, 도 1d를 참조하면, 제 2 포토레지스트 패턴(40)에 맞추어서 반도체 기판(1)이 드러나도록 제 2 반사 방지막(13), 제 2 질화막(7), 제 1 산화막(5) 및 제 1 질화막(3)을 식각하여 비아홀(11b)을 형성한다.1D, the second anti-reflection film 13, the second nitride film 7, the first oxide film 5, and the first oxide film 1 may be exposed so that the semiconductor substrate 1 is exposed in accordance with the second photoresist pattern 40. The nitride film 3 is etched to form the via hole 11b.
이후, 제 2 포토레지스트 패턴(40)과 제 2 반사 방지막(13)을 제거함으로써, 트렌치(11a) 및 비아홀(11b)로 이루어진 듀얼 다마신 패턴(11)을 형성한다.Thereafter, the second photoresist pattern 40 and the second anti-reflection film 13 are removed to form the dual damascene pattern 11 formed of the trench 11a and the via hole 11b.
도 1e를 참조하면, 듀얼 다마신 패턴(11)이 완전히 매립되도록 전도성 물질을 형성한 다음 제 2 산화막(9)이 드러나도록 화학적 기계적 연마 공정을 실시하여 평탄화시킨 다음 금속 배선(13)을 형성한다.Referring to FIG. 1E, a conductive material is formed to completely fill the dual damascene pattern 11, and then a chemical mechanical polishing process is performed to expose the second oxide layer 9 to be flattened, thereby forming a metal wiring 13. .
여기서, 제 2 반사 방지막(13)은 트렌치(11a)의 프로 파일을 그대로 따라가면서 트렌치(11a)가 형성된 제 2 산화막(9) 상에 형성되기 때문에 제 2 반사 방지막(13)을 제거 시 제대로 제거되지 않고 찌꺼기가 남게 되며, 제거되지 않고 남은 찌꺼기는 소자의 전기적인 특성을 나쁘게 하는 요인이 된다.Here, since the second anti-reflection film 13 is formed on the second oxide film 9 having the trench 11a formed while following the profile of the trench 11a, the second anti-reflection film 13 is properly removed when the second anti-reflection film 13 is removed. Leftovers are left unattended, and leftovers left unattended are a factor in the electrical properties of the device.
또한, 듀얼 다마신 패턴은 포토레지스트를 이용하여 형성하는데, 이때 포토레지스트 패턴의 선폭에 한계가 있기 때문에 미세 선폭을 갖는 듀얼 다마신 패턴 형성이 어려워 후속되는 금속 배선 형성 공정에서 공정 마진 확보가 어려운 문제점이 있다.In addition, the dual damascene pattern is formed by using a photoresist. At this time, since the line width of the photoresist pattern is limited, it is difficult to form a dual damascene pattern having a fine line width, thereby making it difficult to secure process margin in a subsequent metal wiring formation process. There is this.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 듀얼 다마신 패턴 제조 공정에서 평탄한 반사 방지막을 형성하여 제거를 용이하게 하고 비아홀의 측벽에 스페이서를 형성함으로써, 비아홀 식각시 과다식각으로 인한 비아홀의 바텀 에지(bottom edge)에서 발생하는 언더컷(under cut) 현상을 개선하여, 반도체 소자의 전기적 특성을 개선시킬 수 있을 뿐만 아니라 공정 마진을 확보할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하고자 한다.An object of the present invention is to solve the problems of the prior art, by forming a flat anti-reflection film in the dual damascene pattern manufacturing process to facilitate the removal and by forming a spacer on the sidewall of the via hole, over etching during via hole etching By improving the undercut phenomenon occurring at the bottom edge of the via hole, the electrical characteristics of the semiconductor device can be improved as well as a method of forming a metal wiring of the semiconductor device which can secure a process margin. I would like to.
상기와 같은 목적을 달성하기 위하여 본 발명은, 반도체 기판 상에 제 1, 2 절연막을 순차적으로 형성하는 단계와, 상기 제 2 절연막 상부에 제 1 반사 방지막을 형성하는 단계와, 상기 제 1 반사 방지막의 상부에 포토레지스트 패턴을 마스크로 하여 상기 제 1 반사 방지막 및 상기 제 2 절연막을 식각하는 단계와, 상기 제 1 반사 방지막과 상기 포토레지스트 패턴을 제거하는 단계와, 상기 식각된 제 2 절연막의 상부에 제 3 절연막 및 제 2 반사 방지막을 형성하는 단계와, 상기 제 2 반사 방지막의 상부에 포토레지스트 패턴을 마스크로 하여 상기 제 2 반사방지막 및 상기 제 3 절연막을 식각하여 트렌치를 형성하는 단계와, 상기 식각된 제 2 절연막을 식각 마스크로 제 1 절연막을 식각하여 비아홀을 형성하는 단계와, 상기 포토레지스트 패턴과 상기 제 2 반사 방지막을 제거함으로써, 상기 트렌치와 비아홀로 이루어진 듀얼 다마신 패턴을 형성하는 단계와, 상기 듀얼 다마신 패턴에서 비아홀의 측벽에 스페이서를 형성하는 단계와, 상기 스페이서가 형성된 상기 듀얼 다마신 패턴에 전도성 물질을 매립시켜 금속 배선을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention comprises the steps of sequentially forming a first, second insulating film on the semiconductor substrate, forming a first anti-reflection film on the second insulating film, and the first anti-reflection film Etching the first antireflection film and the second insulating film using a photoresist pattern as a mask on the top of the substrate; removing the first antireflection film and the photoresist pattern; and an upper portion of the etched second insulating film. Forming a third insulating film and a second anti-reflection film on the substrate; forming a trench by etching the second anti-reflection film and the third insulating film using a photoresist pattern as a mask on the second anti-reflection film; Forming a via hole by etching the first insulating layer using the etched second insulating layer using an etch mask, the photoresist pattern and the second half Removing the barrier layer to form a dual damascene pattern comprising the trench and the via hole; forming a spacer on the sidewall of the via hole in the dual damascene pattern; and a conductive material on the dual damascene pattern on which the spacer is formed. Embedding the metal wires to form metal wires.
이하에서 첨부한 도면을 참조하여 바람직한 실시 예에 대하여 상세히 설명하기로 한다. Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명의 바람직한 실시 예에 따른 반도체 소자의 금속 배선 형성 과정을 도시한 공정도이다.2A to 2H are process diagrams illustrating a metal wiring formation process of a semiconductor device according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(100) 상에 제 1, 2, 3 절연막(102, 104, 106)을 순차적으로 증착한다. 이때 제 1 절연막(102)은 질화막, 탄탈륨계 옥사이드 및 알루미늄계 옥사이드들 중 어느 하나를 이용하여 형성시키고, 제 3 절연막(106)은 질화막 또는 SiC를 이용하여 형성시킨다.As shown in FIG. 2A, first, second, and third insulating films 102, 104, and 106 are sequentially deposited on the semiconductor substrate 100 on which various elements for forming a semiconductor device are formed. In this case, the first insulating film 102 is formed using any one of a nitride film, tantalum oxide and aluminum oxide, and the third insulating film 106 is formed using a nitride film or SiC.
이후, 도 2b에 도시된 바와 같이, 제 3 절연막(106)에 제 1 반사 방지막(108)을 형성하고, 제 1 반사 방지막(108)의 상부에 포토레지스트를 도포한 후 제 1 마스크로 사진 및 현상 공정을 실시하여 비아홀 영역을 정의하기 위한 제 1 포토레지스트 패턴(110)을 형성한다. 그 다음으로, 제 1 포토레지스트 패턴(110)에 맞추어서 제 1 반사 방지막(108) 및 제 3 절연막(106)을 식각한 후에 제 1 반사 방지막(108)과 제 1 포토레지스트 패턴(110)을 제거하여 비아홀 영역이 정의된, 즉 식각된 제 3 절연막(106a)을 형성한다.Thereafter, as shown in FIG. 2B, the first anti-reflection film 108 is formed on the third insulating film 106, the photoresist is applied on the first anti-reflection film 108, and then a photo and a first mask are used. The development process is performed to form the first photoresist pattern 110 for defining the via hole region. Next, after etching the first antireflection film 108 and the third insulating film 106 in accordance with the first photoresist pattern 110, the first antireflection film 108 and the first photoresist pattern 110 are removed. As a result, the third insulating layer 106a in which the via hole region is defined, that is, is etched is formed.
이때, 제 3 절연막(106)에 비아홀 영역을 정의하는 공정은 제 1 포토레지스트 패턴(110)에 맞추어 건식 식각으로 제 1 반사 방지막(108)을 식각함과 더불어 인-시츄(in-situ) 공정으로 제 3 절연막(106)을 식각함으로써, 비아홀 영역이 정의된 제 3 절연막(106a)을 형성할 수 있다.In this case, the process of defining the via hole region in the third insulating layer 106 is performed by etching the first anti-reflection film 108 by dry etching in accordance with the first photoresist pattern 110 and in-situ process. By etching the third insulating film 106, the third insulating film 106a in which the via hole region is defined can be formed.
도 2c에 도시된 바와 같이, 식각된 제 3 절연막(106a)의 상부에 제 4 절연막(112) 및 제 2 반사 방지막(114)을 형성하고, 제 2 반사 방지막(114)의 상부에 포토레지스트를 도포한 후 제 1 마스크로 사진 및 현상 공정을 실시하여 제 2 포토레지스트 패턴(116)을 형성한다.As shown in FIG. 2C, a fourth insulating film 112 and a second anti-reflection film 114 are formed on the etched third insulating film 106a, and a photoresist is formed on the second anti-reflection film 114. After coating, the photomask and the developing process are performed with the first mask to form the second photoresist pattern 116.
도 2d에 도시된 바와 같이, 제 2 포토레지스트 패턴(116)을 식각 마스크로 제 4 절연막(112)을 식각하여 제 4 절연막(112)에 트렌치(118a)를 형성한다. 이때 제 4 절연막(112)을 제 2 포토레지스트 패턴(116)에 맞추어서 습식 식각으로 식각하거나 제 2 포토레지스트 패턴(116)에 맞추어서 등방성 건식 식각으로 식각함으로써 완만한 경사를 갖는 트렌치(118a)를 형성할 수 있다. 여기서, 제 4 절연막(112)을 등방성 건식 식각 또는 습식 식각으로 식각할 때 식각 엔드포인트(endpoint)는 패터닝된 제 3 절연막(106a)이다.As illustrated in FIG. 2D, the fourth insulating layer 112 is etched using the second photoresist pattern 116 as an etching mask to form the trench 118a in the fourth insulating layer 112. At this time, the trench 118a having a gentle inclination is formed by etching the fourth insulating layer 112 by wet etching in accordance with the second photoresist pattern 116 or by isotropic dry etching in accordance with the second photoresist pattern 116. can do. Here, when the fourth insulating layer 112 is etched by isotropic dry etching or wet etching, the etching endpoint is the patterned third insulating layer 106a.
도 2e에 도시된 바와 같이, 제 2 포토레지스트 패턴(116)에 맞추어서 비아홀 영역에 매립된 제 4 절연막(112'), 제 2 절연막(104) 및 제 1 절연막(102)을 식각하여 비아홀(118b)을 형성함으로써, 트렌치(118a) 및 비아홀(118b)로 이루어진 듀얼 다마신 패턴(118)을 형성한다. 이때 비아홀(118b)은 제 3 절연막에 형성된 패턴을 식각 마스크로 하여 건식 식각으로 제 2 절연막(104) 및 제 1 절연막(102)을 식각하여 형성된다.As illustrated in FIG. 2E, the fourth insulating layer 112 ′, the second insulating layer 104, and the first insulating layer 102 embedded in the via hole region are etched in accordance with the second photoresist pattern 116 to etch the via holes 118b. ), A dual damascene pattern 118 consisting of a trench 118a and a via hole 118b is formed. In this case, the via hole 118b is formed by etching the second insulating film 104 and the first insulating film 102 by dry etching using the pattern formed in the third insulating film as an etching mask.
이후, 도 2f 내지 도 2g에 도시된 바와 같이, 제 2 포토레지스트 패턴(116)과 식각된 제 2 반사 방지막(114a)을 제거한 다음 듀얼 다마신 패턴(118)이 매립되도록 스페이서막을 증착하며, 이후 전면 식각 방법으로 비아홀(118b)의 측벽에 스페이서(120)를 형성한다. 이때 듀얼 다마신 패턴(118)에 매립되는 스페이서막으로는 질화막을 이용한다.After that, as shown in FIGS. 2F to 2G, the second photoresist pattern 116 and the etched second anti-reflection film 114a are removed, and then a spacer film is deposited so that the dual damascene pattern 118 is embedded. The spacer 120 is formed on the sidewall of the via hole 118b by a front etching method. In this case, a nitride film is used as the spacer film embedded in the dual damascene pattern 118.
이와 같이 금속 배선 공정 전에 비아홀(118b)의 측벽에 스페이서(120)를 형성함으로써, 공정 마진을 확보할 수 있을 뿐만 아니라 미세 선폭을 갖는 반도체 소자를 형성할 수 있다.As such, by forming the spacers 120 on the sidewalls of the via holes 118b before the metal wiring process, not only a process margin can be secured but also a semiconductor device having a fine line width can be formed.
그 다음으로, 도 2h에 도시된 바와 같이, 스페이서(120)가 형성된 비아홀(118b)을 포함하는 듀얼 다마신 패턴(118)에 전도성 물질을 매립시키고, CMP와 같은 평탄화 과정을 통해 금속 배선(122)을 형성시킨다.Subsequently, as shown in FIG. 2H, the conductive material is embedded in the dual damascene pattern 118 including the via hole 118b having the spacer 120 formed thereon, and the metal wiring 122 is made through a planarization process such as CMP. ).
금속 배선 형성 시 평탄화 공정, 즉 CMP 공정에서 CMP 정지막으로는 금속 배선(122) 형성 공정에서 전도성 물질이 증착되기 전에 인-시츄 공정으로 증착되는 배리어 금속막(도시 생략됨)을 이용한다.In the planarization process, that is, the CMP process in forming the metal lines, a barrier metal film (not shown) deposited in an in-situ process before the conductive material is deposited in the process of forming the metal lines 122 is used as the CMP stop layer.
이상 설명한 바와 같이, 본 발명은 듀얼 다마신 패턴 제조 공정에서 평탄한 반사 방지막을 형성하여 제거를 용이하게 하고 비아홀의 측벽에 스페이서를 형성함으로써, 반도체 소자의 신뢰성을 향상시킴과 더불어 공정 마진을 확보할 수 있다.As described above, the present invention facilitates removal by forming a flat anti-reflection film in the dual damascene pattern manufacturing process and forms spacers on the sidewalls of the via holes, thereby improving reliability of the semiconductor device and securing process margins. have.
도 1a 내지 도 1e는 종래 기술에 의한 반도체 소자의 금속 배선 형성 과정을 도시한 공정 단면도이고,1A to 1E are cross-sectional views illustrating a process of forming metal wirings of a semiconductor device according to the prior art;
도 2a 내지 도 2h는 본 발명의 바람직한 실시 예에 따른 반도체 소자의 금속 배선 형성 과정을 도시한 공정 단면도이다.2A to 2H are cross-sectional views illustrating a process of forming metal wirings in a semiconductor device according to an exemplary embodiment of the present invention.
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