KR100835413B1 - Method for forming a small via hole of the semiconductor device - Google Patents

Method for forming a small via hole of the semiconductor device Download PDF

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KR100835413B1
KR100835413B1 KR1020060122202A KR20060122202A KR100835413B1 KR 100835413 B1 KR100835413 B1 KR 100835413B1 KR 1020060122202 A KR1020060122202 A KR 1020060122202A KR 20060122202 A KR20060122202 A KR 20060122202A KR 100835413 B1 KR100835413 B1 KR 100835413B1
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forming
via hole
etching
photoresist pattern
fine via
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KR1020060122202A
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Korean (ko)
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정성희
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method for forming a small via hole of a semiconductor device is provided to form a fine via-hole by performing an isotropic wet-etch process and an anisotropic dry-etch process. A photoresist pattern(310) having an opening(310a) is formed on a semiconductor substrate(300) having an interlayer dielectric(300b) formed on a first metal line layer(300a). A wet-etch process is performed to form a circular depression part(320) at an upper part of the semiconductor substrate corresponding to the opening of the photoresist pattern. The photoresist pattern is removed. An etch-back process is performed to form a V-shaped depression part(330) by removing a predetermined part corresponding to a terrace part(320a) protruded from an edge of an entrance of the circular depression part. A dry etch process is performed to form a fine via-hole(340) by removing selectively the inside of the V-shaped depression part.

Description

반도체 소자의 미세 비아홀 형성방법{METHOD FOR FORMING A SMALL VIA HOLE OF THE SEMICONDUCTOR DEVICE}METHOD FOR FORMING A SMALL VIA HOLE OF THE SEMICONDUCTOR DEVICE

도 1은 종래의 미세 비아홀 형성방법중 선택비가 우수한 감광액과 함께 한번의 건식 식각을 이용하는 방법을 보여주는 공정 단면도, 1 is a cross-sectional view illustrating a method of using a single dry etching process with a photoresist having a good selection ratio in a conventional method for forming fine via holes;

도 2는 도 1의 방법에 따라 형성되는 미세 비아홀이 불량한 프로파일을 갖게 되는 것을 보여주는 평면도, FIG. 2 is a plan view showing that fine via holes formed according to the method of FIG. 1 have a poor profile; FIG.

도 3은 종래의 미세 비아홀 형성방법중 측벽 스페이서(spacer)를 이용하는 방법을 순차적으로 보여주는 공정 단면도, 3 is a cross-sectional view sequentially illustrating a method of using a sidewall spacer in a conventional method of forming a fine via hole;

도 4는 본 발명에 따른 미세 비아홀 형성방법을 순차적으로 보여주는 공정 단면도이다. 4 is a process cross-sectional view sequentially showing a method of forming a fine via hole according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100, 200, 300 : 반도체 기판 100a, 200a, 300a : 제1금속배선층100, 200, 300: semiconductor substrate 100a, 200a, 300a: first metal wiring layer

100b, 200b, 300b : 층간절연막 110, 210, 310 : 감광막 패턴100b, 200b, 300b: interlayer insulating film 110, 210, 310: photosensitive film pattern

120, 220a, 340 : 미세 비아홀 220 : 초기비아홀120, 220a, 340: fine via hole 220: initial via hole

230 : 산화물막 230a : 측벽 스페이서230 oxide film 230a sidewall spacer

310a : 개방구 320 : 원형함몰부310a: opening 320: circular depression

320a : 테라스부 330 : V자형함몰부320a: terrace portion 330: V-shaped depression

본 발명은 반도체 소자의 미세 비아홀(via hole) 형성방법에 관한 것으로서, 더욱 상세하게는 등방성(isotropic)의 습식 식각(wet etching)을 이용하여 미리 작은 크기의 원형함몰부를 형성해 놓은 다음 이어서 에치백(etch back)을 통해 해당 원형함몰부의 입구측 테라스부를 제거하고 그 후 이방성(anisotropic)의 건식 식각(dry etching)을 이용하여 마무리 수직화 식각함으로써 우수한 프로파일(profile)을 갖는 미세 비아홀을 원활하게 형성할 수 있게 되는 반도체 소자의 미세 비아홀 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming fine via holes in a semiconductor device, and more particularly, to form circular depressions of a small size in advance by using isotropic wet etching, and then to etch back ( The inlet-side terrace portion of the circular depression portion is removed through the etch back, and then the final vertical etching is performed using anisotropic dry etching to smoothly form fine via holes having an excellent profile. The present invention relates to a method for forming fine via holes in a semiconductor device.

일반적으로, 최근 들어 반도체 소자의 집적도가 대폭 증가됨에 따라 회로의 전기적 연결을 위한 금속 배선(metal line) 또한 다층 구조화되어 가고 있으며, 이에 따라 하부 금속막과 상부 금속막을 수직되도록 연결하기 위한 비아 컨택(via contact)이 채택되고 있는데, 이러한 비아 컨택은 먼저 상하방향으로 관통되도록 비아홀(via hole)을 형성한 다음 해당 비아홀내에 갭필(gap fill) 특성이 우수한 텅스텐(W)막과 같은 금속막을 충진하는 것에 의해 제조되게 된다. In general, with the recent increase in the degree of integration of semiconductor devices, metal lines for electrical connection of circuits have also been multi-layered. Accordingly, via contacts for vertically connecting the lower metal layer and the upper metal layer may be formed. A via contact is adopted. The via contact is formed by first forming a via hole so as to penetrate in the vertical direction, and then filling a metal film such as a tungsten (W) film having a good gap fill property in the via hole. To be prepared.

그리고, 근래의 고집적화 추세에 따라 비아 컨택은 극미세화되어 가고 있으므로, 우선은 극히 미세한(예컨대, 65nm 이하) 비아홀을 양호하게 형성할 수 있어야 한다. In addition, since the via contact is becoming very fine according to the recent trend of high integration, first, it is necessary to be able to form an extremely fine via hole (for example, 65 nm or less).

비아홀은 기본적으로 포토 리소그래피(photo lithography) 공정을 통해 감광 막 패턴을 형성하고 해당 감광막 패턴을 식각 마스크로 이용하여 식각(etching)하는 것에 의해 감광막 패턴상의 개방된 구멍에 대응되도록 형성하게 된다. The via hole is basically formed to correspond to the open hole on the photoresist pattern by forming a photoresist pattern through a photo lithography process and etching using the photoresist pattern as an etching mask.

현재 시점에서 미세 비아홀을 형성하는 방법으로는 이하의 두가지 방법이 널리 이용되고 있다. At the present time, the following two methods are widely used to form fine via holes.

첫번째 방법은 단순하게 선택비가 매우 우수한 감광액(PR : Photo Resist)과 함께 이방성(anisotropic) 식각이 가능한 건식 식각(dry etching)을 이용하여 한번에 형성하는 방법으로, 도 1을 참조하면, 제1금속배선층(100a)상에 층간절연막(100b)이 형성되어 있는 반도체 기판(100)상에 선택비가 양호한 감광액을 도포하여 감광막 패턴(110)을 형성한 다음 바로 건식 식각하는 것에 의해 층간절연막(100b) 및 제1금속배선층(100a)이 개방되도록 미세 비아홀(120)을 형성하게 되며, 이 방법에 의하면, 식각에 따라 감광막 패턴(110)의 개방된 구멍의 측면부가 일부 손상되게 되면서 결국 도 2의 평면도를 통해 나타낸 바와 같이, 미세 비아홀(120)이 매우 불량한 프로파일(profile)을 갖도록 형성되게 되고, 특히 비아홀(120)의 측면상에 줄무늬(striation) 구조가 형성되게 되며, 또한 이용하는 식각가스의 에천트(etchant)에 따라 그 결과가 매우 상이하게 나타난다는 문제점이 있었다. The first method is a method of forming at once by using dry etching, which is capable of anisotropic etching together with a photoresist (PR) having a very good selection ratio. Referring to FIG. 1, a first metal wiring layer The interlayer insulating film 100b and the first layer are formed by applying a photoresist having a good selectivity on the semiconductor substrate 100 on which the interlayer insulating film 100b is formed on (100a) to form a photosensitive film pattern 110, and then dry etching immediately. 1 to form a fine via hole 120 to open the metal wiring layer (100a), according to this method, the side of the open hole of the photosensitive film pattern 110 is partially damaged by etching, and eventually through the plan view of FIG. As shown, the fine via hole 120 is formed to have a very poor profile, in particular a stripe structure is formed on the side of the via hole 120, According to the etchant (etchant) of the etching gas has a problem that the results appear very different.

두번째 방법은 측벽 스페이서(spacer)를 이용하는 방법으로, 도 3을 참조하면, 제1금속배선층(200a)상에 층간절연막(200b)이 형성되어 있는 반도체 기판(200)상에 감광막 패턴(210)을 형성한 다음, 건식 식각하여 우선 다소 크기가 큰 초기비아홀(220)을 형성해 놓은 후, 애싱(ashing) 처리하여 이용하였던 감광막 패턴(210) 을 제거하고, 초기비아홀(220)에 대해 산화물(oxide)막(230)을 증착(deposition)하여 내부에 일부 충진되도록 한 다음, 최종적으로 충진된 산화물막(230)에 대해 에치백(etch back)을 실시하여 일부 제거함으로써 잔류되는 산화물막(230)이 측벽 스페이서(230a)로 되어 해당 측벽 스페이서(230a)에 의해 초기비아홀(220)의 내경이 축소되도록 함으로써 미세 비아홀(220a)이 형성되도록 하게 된다. The second method uses a sidewall spacer. Referring to FIG. 3, a photoresist pattern 210 is formed on a semiconductor substrate 200 on which an interlayer insulating film 200b is formed on a first metal wiring layer 200a. After forming, dry etching first to form a somewhat larger initial via hole 220, and then remove the photoresist pattern 210 used by ashing, and the oxide to the initial via hole 220 After depositing the film 230 to partially fill the inside, the oxide film 230 remaining as a sidewall is removed by etching back the finally filled oxide film 230. As the spacer 230a, the inner diameter of the initial via hole 220 is reduced by the sidewall spacer 230a so that the fine via hole 220a is formed.

그러나, 이 두번째 방법에 의하면, 모든 과정을 식각 모듈에서 처리할 수 없고, 도중에 별도의 증착 모듈을 거쳐야만 하므로, 생산성이 저하되는 문제점이 있었다. However, according to this second method, since all processes cannot be processed in the etching module and have to go through a separate deposition module in the middle, there is a problem that productivity is lowered.

본 발명은 상기와 같은 제반 문제점을 해결하기 위하여 창안된 것으로서, 모든 과정을 식각 모듈에서 실시할 수 있어 생산성을 향상시킬 수 있으며, 프로파일이 매우 양호하게 미세 비아홀을 형성할 수 있게 되는 반도체 소자의 미세 비아홀 형성방법을 제공하는데 그 목적이 있다. The present invention has been made to solve the above problems, all processes can be carried out in the etching module to improve the productivity, the fine structure of the semiconductor device to be able to form a fine via hole with a very good profile It is an object of the present invention to provide a method for forming a via hole.

본 발명의 상기 목적과 여러가지 장점은 이 기술분야에 숙련된 사람들에 의해 첨부된 도면을 참조하여 아래에 기술되는 발명의 바람직한 실시예로부터 더욱 명확하게 될 것이다. The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

상술한 목적을 달성하기 위한 본 발명의 반도체 소자의 미세 비아홀 형성방법은, 나노급의 미세한 비아홀을 형성하는 방법으로, 제1금속배선층상에 층간절연막이 형성된 반도체 기판상에 개방구를 갖는 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴의 상기 개방구에 상응하는 상기 반도체 기판의 상부측에 원형 형태의 원형함몰부를 형성하기 위해 습식 식각하는 단계와, 상기 감광막 패턴을 제거하는 단계와, 상기 원형함몰부의 개구된 입구측 가장자리부에 돌출되도록 형성되어 있는 테라스(terrace)부에 해당하는 두께 부분을 제거하여 상부측이 수직되는 형태의 V자형함몰부를 형성하기 위해 에치백하는 단계와, 상기 V자형함몰부 내부를 선택적으로 제거하여 전체적으로 수직되는 상기 미세 비아홀을 형성하기 위해 건식 식각하는 단계를 포함하는 것을 특징으로 한다. The method of forming a fine via hole of a semiconductor device of the present invention for achieving the above object is a method of forming a nano-grade fine via hole, a photosensitive film pattern having an opening on a semiconductor substrate in which an interlayer insulating film is formed on the first metal wiring layer. Forming a circular recess on the upper side of the semiconductor substrate corresponding to the opening of the photoresist pattern, wet etching to remove the photoresist pattern, and removing the circular recess. Removing the thickness portion corresponding to the terrace portion formed to protrude from the opened inlet side edge of the portion to etch back to form a V-shaped depression in which the upper side is vertical; Selectively removing the inside of the portion to dry etch to form the micro via holes that are generally vertical And that is characterized.

이하, 첨부된 도면을 참조로 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 4는 본 발명에 따른 미세 비아홀 형성방법을 순차적으로 보여주는 공정 단면도이다. 4 is a process cross-sectional view sequentially showing a method of forming a fine via hole according to the present invention.

먼저, 도 4의 (a)와 같이, 제1금속배선층(300a)상에 층간절연막(300b)이 형성된 반도체 기판(300)상에 포토 리소그래피 과정을 통해 감광막 패턴(310)을 형성하되, 그 개방구(310a)가 목적하는 비아홀(340)의 내경보다 조금 작도록 형성하게 된다. First, as shown in FIG. 4A, the photoresist pattern 310 is formed on the semiconductor substrate 300 on which the interlayer insulating film 300b is formed on the first metal wiring layer 300a through a photolithography process. The vent 310a is formed to be slightly smaller than the inner diameter of the desired via hole 340.

이어서, 도 4의 (b)와 같이, 습식 식각(wet etching)을 매우 짧은 시간만 실시하여 감광막 패턴(310)의 개방구(310a)에 상응되는 위치의 반도체 기판(300)의 상부측이 미세하게 제거되도록 하게 되며, 이때 습식 식각은 등방성(isotropic) 식각이므로 식각액이 표면에 공급되어 화학반응이 진행됨에 따라 결과적으로 상부측 가장자리 부분이 일부 개구되는 함몰된 원형 형태로 원형함몰부(320)가 형성되게 되고, 이때 해당 원형함몰부(320)의 내경이 목적하는 비아홀(340)의 내경에 거의 상응되도록 형성하게 된다. Subsequently, as shown in FIG. 4B, wet etching is performed only for a very short time so that the upper side of the semiconductor substrate 300 at the position corresponding to the opening 310a of the photoresist pattern 310 is fine. In this case, since the wet etching is isotropic etching, the etching solution is supplied to the surface, and as the chemical reaction proceeds, the circular recess 320 is formed in a recessed circular shape in which the upper edge portion is partially opened. In this case, the inner diameter of the circular depression 320 is formed to substantially correspond to the inner diameter of the desired via hole 340.

이어서, 도 4의 (c)와 같이, 애싱을 실시하여 지금까지 이용하였던 감광막 패턴(310)을 제거하게 된다. Subsequently, as illustrated in FIG. 4C, ashing is performed to remove the photoresist pattern 310 used so far.

그 후, 도 4의 (d)와 같이, 에치백을 실시하여 원형함몰부(320)의 개구된 입구측 가장자리부에 돌출되도록 형성되어 있던 테라스(terrace)부(320a)를 제거하게 되며, 에치백은 잘 알려진 바와 같이, 선택비 보다는 평탄화(planarization) 목적으로 실시하는 건식 식각의 일종이므로, 그 실시에 따라 테라스부(320a)에 해당하는 두께 부분이 제거되게 되고, 물론 원형함몰부(320) 내측도 일부 제거되게 되어, 결과적으로 상부측이 수직된 형태의 V자형함몰부(330)가 형성되게 된다. Thereafter, as illustrated in FIG. 4 (d), the terrace portion 320a which is formed to protrude to the opened inlet side edge portion of the circular recess portion 320 is removed. As it is well known, since the back is a kind of dry etching performed for the purpose of planarization rather than the selection ratio, the thickness portion corresponding to the terrace portion 320a is removed according to the implementation, and the circular depression 320 is, of course. Part of the inner side is also removed, and as a result, the V-shaped depression 330 having a vertical shape is formed.

그리고, 이때의 에치백은 반응성 이온 식각(Reactive Ion Etch : RIE)을 이용하여 실시될 수 있다. In this case, the etch back may be performed by using reactive ion etching (RIE).

이어서, 도 4의 (e)와 같이, 최종적으로 선택적인 방향성을 갖는 이방성 식각인 건식 식각을 실시하여 V자형함몰부(330) 내부를 선택적으로 나머지 제거하여 수직화되도록 함으로써, 결과적으로 수직화된 미세 비아홀(340)이 형성되도록 하게 된다. Subsequently, as shown in FIG. 4E, dry etching, which is finally anisotropic etching having a selective directionality, is performed to selectively vertically remove the remaining portions of the V-shaped depression 330, thereby resulting in verticalization. The fine via hole 340 is formed.

이때의 건식 식각도 반응성 이온 식각을 이용할 수 있으며, 전술한 에치백을 위해 실시할 때와는 다른 공정조건으로 설정하여 실시하게 된다. In this case, the dry etching may also use reactive ion etching, and may be performed by setting process conditions different from those for the above-described etch back.

이로써, 본 발명에 의하면, 우선 습식 식각을 통해 원형함몰부(320)를 형성해 놓은 다음 이어서 건식 식각으로 마무리 식각하여 수직화하게 되므로, 기존에 한번의 건식 식각을 이용하던 것에 비해 우수한 프로파일의 비아홀(340)을 형성할 수 있게 되고, 또한 모든 과정을 식각 모듈에서 진행할 수 있게 되어 생산성도 향상시킬 수 있게 된다. As a result, according to the present invention, since the circular depression 320 is first formed through wet etching, and then the final etching is performed by dry etching, it is verticalized, so that the via hole having an excellent profile compared to the conventional dry etching is used. 340 can be formed, and also all processes can be performed in the etching module, thereby improving productivity.

이상, 상기 내용은 본 발명의 바람직한 일 실시예를 단지 예시한 것으로 본 발명의 당업자는 본 발명의 요지를 변경시킴이 없이 본 발명에 대한 수정과 변경을 가할 수 있음을 인지해야 한다.In the foregoing description, it should be understood that those skilled in the art can make modifications and changes to the present invention without changing the gist of the present invention as merely illustrative of a preferred embodiment of the present invention.

본 발명에 따르면, 등방성의 습식 식각을 이용하여 미리 작게 원형함몰부를 형성해 놓은 다음 이어서 이방성의 건식 식각을 이용하여 완전하게 수직화하여 미세 비아홀을 형성하게 되므로, 기존에 한번의 건식 식각을 통해 형성하던 것에 비해 우수한 프로파일을 갖는 비아홀을 형성할 수 있게 됨과 아울러, 또한 모든 과정을 식각 모듈에서 진행할 수 있어 생산성도 향상시킬 수 있는 효과가 달성될 수 있다. According to the present invention, since a small circular depression is formed in advance using an isotropic wet etching, and then completely vertically formed using anisotropic dry etching, fine via holes are formed. In addition to being able to form a via hole having an excellent profile compared to the above, the whole process can also be carried out in the etching module can be achieved the effect of improving the productivity.

Claims (4)

나노급의 미세한 비아홀을 형성하는 방법으로, As a method of forming nano-grade fine via holes, 제1금속배선층(300a)상에 층간절연막(300b)이 형성된 반도체 기판(300)상에 개방구(310a)를 갖는 감광막 패턴(310)을 형성하는 단계와, Forming a photosensitive film pattern 310 having an opening 310a on the semiconductor substrate 300 on which the interlayer insulating film 300b is formed on the first metal wiring layer 300a; 상기 감광막 패턴(310)의 상기 개방구(310a)에 상응하는 상기 반도체 기판(300)의 상부측에 원형 형태의 원형함몰부(320)를 형성하기 위해 습식 식각하는 단계와, Wet etching to form a circular recessed portion 320 having a circular shape on an upper side of the semiconductor substrate 300 corresponding to the opening 310a of the photoresist pattern 310; 상기 감광막 패턴(310)을 제거하는 단계와, Removing the photoresist pattern 310; 상기 원형함몰부(320)의 개구된 입구측 가장자리부에 돌출되도록 형성되어 있는 테라스(terrace)부(320a)에 해당하는 두께 부분을 제거하여 상부측이 수직되는 형태의 V자형함몰부(330)를 형성하기 위해 에치백하는 단계와, The V-shaped recess 330 of which the upper side is vertical is removed by removing a thickness portion corresponding to the terrace portion 320a which is formed to protrude from the opened inlet side edge portion of the circular recess 320. Etching back to form a 상기 V자형함몰부(330) 내부를 선택적으로 제거하여 전체적으로 수직되는 상기 미세 비아홀(340)을 형성하기 위해 건식 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 미세 비아홀 형성방법.And selectively etching the V-shaped recess 330 to form the fine via hole 340 which is generally vertical. 제 1 항에 있어서, The method of claim 1, 상기 에치백 및 상기 건식 식각은, The etch back and the dry etching, 반응성 이온 식각(Reactive Ion Etch : RIE)을 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 미세 비아홀 형성방법.A method of forming fine via holes in a semiconductor device, characterized by using reactive ion etching (RIE). 제 1 항에 있어서, The method of claim 1, 상기 감광막 패턴(310)을 형성하는 단계는, Forming the photoresist pattern 310 is, 상기 개방구(310a)의 내경이 목적하는 상기 비아홀(340)의 내경보다 작게 형성하는 것을 특징으로 하는 반도체 소자의 미세 비아홀 형성방법.The inner diameter of the opening (310a) is smaller than the inner diameter of the via hole (340) to form a fine via hole forming method of the semiconductor device characterized in that formed. 삭제delete
KR1020060122202A 2006-12-05 2006-12-05 Method for forming a small via hole of the semiconductor device KR100835413B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03259529A (en) * 1990-03-08 1991-11-19 Mitsubishi Electric Corp Forming method of through-hole
JP2003347402A (en) 2002-05-30 2003-12-05 Mitsubishi Electric Corp Method of manufacturing semiconductor device
KR20050013248A (en) * 2002-06-25 2005-02-03 어드밴스드 마이크로 디바이시즈, 인코포레이티드 A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
KR20050022527A (en) * 2003-09-02 2005-03-08 동부전자 주식회사 Method for forming metal line in a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03259529A (en) * 1990-03-08 1991-11-19 Mitsubishi Electric Corp Forming method of through-hole
JP2003347402A (en) 2002-05-30 2003-12-05 Mitsubishi Electric Corp Method of manufacturing semiconductor device
KR20050013248A (en) * 2002-06-25 2005-02-03 어드밴스드 마이크로 디바이시즈, 인코포레이티드 A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
KR20050022527A (en) * 2003-09-02 2005-03-08 동부전자 주식회사 Method for forming metal line in a semiconductor device

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