JP2003347402A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a method of manufacturing a semiconductor device having a multilayer wiring structure reducing and inhibiting the indentation of a via hole and having no improper contacts. <P>SOLUTION: A semiconductor-device manufacturing method includes a process opening a via hole comprising: a first process opening a hole halfway of an interlayer film 7 that is flattened by dry etching with a photo resist film 8 as a mask; a second process removing the photo resist film 8 by ashing; a third process removing the polymer residue generated by dry etching and ashing by remover; a fourth process performing wet etching after the third process; a fifth process forming a via hole 10 penetrating through an AL wiring 1 at a first layer by dry etch back; and a sixth process removing the polymer residue generated by dry etch back by the remover. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a via (vi) in a multilayer wiring process.
a) It relates to the formation of holes.

[0002]

2. Description of the Related Art In recent years, miniaturization in a multilayer wiring process is indispensable as semiconductor devices become more highly integrated, and it is required that via holes be formed as minute holes having a high aspect ratio. A conventional method for manufacturing a semiconductor device, which is a method for forming a via hole, which meets such a requirement, will be described with reference to FIG. First, after the first-layer AL wiring 1 is formed, the HDP
(High DensityPlasma: High Density Plasma) Plasma CVD (Chemical Vapor)
After forming an interlayer oxide film by Deposition (Chemical Vapor Deposition) method, CMP (Chemical Mecha)
Then, the interlayer film 2 is formed by flattening by chemical polishing (chemical polishing). Next, a resist is applied, and photolithography is used to form a resist mask 3 for a via hole.
To form When photolithography is performed on a fine hole having a hole diameter of about 0.22 μm, the resist is desirably KrF (krypton fluoride) and the film thickness is preferably 600 nm or less. After forming the resist mask, a via hole 4 is formed by dry etching (FIG. 3A). Hole diameter 0.22 μm,
When forming a via hole with an interlayer thickness of about 700 nm,
Etching using plasma of a fluorocarbon gas having a high C / F ratio such as C ₅ F ₈ or C ₄ F ₈ is required.

After opening the via hole by dry etching, the resist mask 3 is removed by ashing, and the polymer residue is removed by a stripping solution such as EKC (registered trademark) 265. Then, a barrier metal such as TiN is formed by a sputtering method or the like, and W or the like is formed by a CVD method or the like. Then, W on the interlayer film 2 is formed by the CMP method.
The TiN is removed to form a plug 5 (FIG. 3B).
A second-layer AL wiring 6 is formed thereon to form a multilayer wiring structure (FIG. 3C).

As another conventional method for manufacturing a semiconductor device, for example, Japanese Patent Application Laid-Open No.
No. 2,43,133. Here, the manufacturing method disclosed in Japanese Patent Application Laid-Open No. 2-213129 will be briefly described with reference to FIG.

After forming the resist mask 3 for the via hole,
A hole is opened halfway through the interlayer film 2 by anisotropic dry etching (FIG. 4A). Next, an intermediate portion of the via hole is formed in a hemispherical shape by wet etching (FIG. 4B). Thereafter, etching is performed again by anisotropic dry etching until reaching the AL wiring 1 (FIG. 4C).

[0006]

However, in the above-described conventional method for manufacturing a semiconductor device, a plug is formed by W-CMP because the hole shape is notched at the time of via hole etching and the formation of a barrier metal is incomplete. Sometimes hydrofluoric acid used for slurry removal is the first layer of AL
It erodes the wiring and causes contact failure. Hereinafter, the mechanism of the occurrence of the defect will be briefly described with reference to FIG.

FIG. 5 is a cross-sectional view showing how a problem occurs when a via hole is formed using a conventional manufacturing method. 5, the same reference numerals as those in FIG. 3 denote the same parts.

In the conventional manufacturing method, it is assumed that a via hole having a hole bottom diameter of 0.22 μm and a depth of 700 nm is formed. When forming a via hole of this dimension, a KrF resist is used as the resist, and the resist film thickness needs to be 600 nm or less. Next, C ₅ F ₈ + O
Dry etching is performed by plasma using a gas of ₂ + Ar or C ₄ F ₈ + O ₂ + Ar to form the via hole 4 having the desired shape. During the dry etching, the KrF resist 3 is not uniformly etched but proceeds in a columnar manner. In particular, at the shoulder near the hole opening, the tendency is remarkable, and a portion where the resist film is reduced rapidly and a portion where the resist film is reduced appear at random (FIG. 5).
(A)).

Therefore, the upper portion of the via hole 4 has a notched shape (FIG. 5B). On the other hand, the lower portion of the via hole 4 also has a jagged shape during the overetching, using the non-uniform deposition from the first layer AL wiring 1 as a mask. Then, when the etching is completed, a via hole 4 is formed in which some of the ridges at the top and bottom of the hole are connected. Thereafter, the resist is removed by ashing, and EKC (registered trademark) 265 is used.
A residue such as a polymer film formed during the ashing or a deposition film formed during the etching by a stripping solution such as a liquid (hereinafter, these are collectively referred to as a polymer residue) is removed.

Thereafter, the T of the barrier metal is formed by sputtering.
Although iN is deposited, a portion where the film is not deposited occurs due to hole burrs. Next, W of the plug material is formed by the CVD method, and W and TiN on the interlayer film are removed by the CMP method. In this W-CMP, hydrofluoric acid cleaning is performed after polishing to remove the slurry. However, this hydrofluoric acid permeates the first layer AL wiring 1 through the portion where TiN is partially not formed due to the above-mentioned hole jaggedness, and near the plug. In the via hole 4 and the first-layer AL wiring 1 (FIG. 5C).

In the case of the manufacturing method described in JP-A-2-213129 or the manufacturing method described in JP-A-63-43133, the jaggedness caused by the first anisotropic dry etching Although it is reduced, the indentation generated in the resist mask remains as it is, so that in the second dry etching, the indented shape is etched, and
The indentation is transferred again to the portion opened by the second anisotropic etching. In addition, if a sufficient undercut is generated by wet etching so that the burrs are not transferred again to the portion opened by the first anisotropic etching, the hole top diameter becomes large, and the AL wiring of the next second layer is formed. Or a short-circuit with a via hole.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has been made to reduce or suppress the burrs of a hole in forming a via hole and to manufacture a semiconductor device having a multilayer wiring structure free from contact failure. It is intended to provide a method.

[0013]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first-layer metal wiring on an insulating film provided on a semiconductor substrate; Depositing an interlayer oxide film on the substrate, planarizing the interlayer oxide film to form an interlayer film, providing a photoresist film having via holes patterned on the planarized interlayer film, and masking the photoresist film. Forming a via hole by dry-etching the planarized interlayer film, forming a plug in the via hole, and forming a second-layer metal wiring on the planarized interlayer film. Wherein the step of forming the via hole includes the step of forming a part of the planarized interlayer film by dry etching using the photoresist film as a mask. A second step of removing the photoresist film by ashing, a third step of removing a polymer residue generated by the dry etching and the ashing by a stripping solution, and a wet etching after the third step. A fourth step of performing, a fifth step of forming a via hole penetrating to the first-layer metal wiring by dry etchback, and a sixth step of removing a polymer residue generated by the dry etchback with a stripping solution. It consists of

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, in the fourth step, wet etch-back is performed to reduce the interlayer film by a predetermined amount with hydrofluoric acid.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the step of forming a plug in the via hole includes the steps of:
The barrier metal TiN and the W are deposited on the planarized interlayer film by the CVD method and the barrier metal TiN and the W on the interlayer film are removed by the CMP method to form a W plug in the via hole. Is formed.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first-layer metal wiring on an insulating film provided on a semiconductor substrate; After depositing an interlayer oxide film, a first step of flattening the interlayer oxide film to form a first interlayer film;
A second step of forming a first-layer via hole on the first-layer interlayer film using a photoresist film in which a first-layer via hole is patterned as a mask, and forming the first-layer via hole in the planarized first-layer interlayer film A third step of forming a first-layer plug in the first-layer via hole thus formed, and a second-layer interlayer film on the first-layer interlayer film on which the plug is formed. And forming a second-layer via hole on the second-layer interlayer film using a photoresist film obtained by patterning a hole having a diameter slightly larger than that of the first-layer via hole as a mask. A fifth step of forming a second-layer plug in the second-layer via hole formed in the second-layer interlayer film, and a sixth step of forming the second-layer plug in the second-layer interlayer film. A seventh step of forming a third interlayer film on the second interlayer film The third layer is formed by using a photoresist film in which a hole slightly smaller than the second layer via hole and having the same diameter as the first layer via hole is patterned as a mask on the third layer interlayer film. The method includes an eighth step of forming a via hole and a ninth step of forming a third-layer plug in the third-layer via hole formed in the third-layer interlayer film.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, the second, fifth, and eighth steps correspond to the first steps by dry etching, respectively, corresponding to the respective steps.
A via hole of the layer, a via hole of the second layer, and a via hole of the third layer are opened, and the photoresist is removed by ashing, and the polymer residue generated by the dry etching and ashing is removed by a stripping solution. Things.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the first layer and the second layer correspond to the first layer, the second layer and the third layer via holes, respectively. And in the step of forming a plug of the third layer, TiN of a barrier metal is deposited on the interlayer film by a sputtering method and W is deposited on the interlayer film by a CVD method, and Ti of the barrier metal on the interlayer film is deposited on the interlayer film.
The N plug and the W are removed by a CMP method to form a W plug in the via hole.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
Description will be made based on the drawings. Embodiment 1 FIG. FIG. 1 is a sectional view and a top view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes A as a first-layer metal wiring.
L wiring, 2 is an interlayer film, 5 is a plug, 6 is an AL wiring as a second layer metal wiring, 7 is an interlayer film, 8 is a resist mask, 9 is a hole, and 10 is a via hole.

Next, a method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. First,
A first-layer AL wiring 1 is formed on a plasma oxide film formed on a semiconductor substrate (not shown) having an element structure. H
CM after forming interlayer oxide film by plasma CVD method such as DP
The surface is planarized by P to form an interlayer film 7 having a thickness of 1000 nm.

Next, after applying a KrF resist to a film thickness of 550 nm, a photoresist film in which a via hole having a hole diameter of 0.20 μm is patterned by photolithography, that is, a resist mask 8 is formed. After forming the resist mask 8, a hole 9 having a depth of about 800 nm is formed by dry etching (FIG. 1A).

This dry etching is performed by using C ₅ F ₈ / O ₂ /
It is performed anisotropically by plasma using a mixed gas of Ar / CO. Next, the resist mask 8 is removed by ashing using O ₂ gas plasma, and a polymer residue generated during dry etching and ashing is removed using EKC (registered trademark) 265 solution. At this time, the shape of the hole 9 becomes jagged at the top because the resist is etched into a columnar shape (FIG. 1B).

However, a smooth circular shape is maintained below the hole 9 because it has not yet reached the first-layer AL wiring 1 and there is no deposit from the AL wiring 1. Next, wet etching back of about 100 nm is performed on the interlayer film 7 with hydrofluoric acid (FIGS. 1C and 1D). Since the wet etching is isotropic, the burrs at the upper part of the hole 9 become smooth. Further, since the inside of the hole 9 is also isotropically etched, the hole diameter increases to 0.22 μm, and the hole depth maintains about 800 nm.

Next, after performing dry etching back of about 200 nm on the interlayer film 7, EKC (registered trademark) 26
The polymer residue generated at the time of dry etch back is removed by the five liquids. Dry etch back is CHF ₃ / CF
_The anisotropy is performed by plasma using a mixed gas of ₄ / Ar. As a result, the interlayer film 2 having a thickness of 700 nm and the depth of 700
A via hole 10 having a diameter of 0.22 μm is formed (FIG. 1E). Note that the state shown by the broken line in FIGS. 1C and 1E shows the state before the wet etching is performed.

An overetch of 100 nm is performed, and the lower portion of the via hole 10 is notched due to the deposition from the first-layer AL wiring 1, but the upper portion of the hole is kept smooth. Then, the Ti
W via hole 10 by N barrier metal and CVD method
Are sequentially formed on the inside and on the interlayer film 2. And C
The plug 5 is formed by removing W and TiN on the interlayer film 2 by the MP method. At this time, since the upper portion of the via hole 10 is smooth, the TiN is uniformly formed on the inner wall of the upper portion of the via hole 10, so that hydrofluoric acid is reduced to 1 even during hydrofluoric acid cleaning for removing slurry after W-CMP polishing. There is no penetration into the AL wiring 1 of the layer. A second-layer AL wiring 6 is formed thereon (FIG. 1F).

As described above, in this embodiment, the dry etching of the via hole is stopped by using a resist mask, and the wet etching back step after removing the resist mask is added. To reduce the jaggedness that occurs at the time, and then to suppress the loss of AL due to the penetration of hydrofluoric acid during hydrofluoric acid cleaning of W-CMP by dry etch back, and to form a multilayer wiring structure with reduced contact failure of via holes and jaggedness. Becomes possible.

Embodiment 2 FIG. FIG. 2 is a sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. In FIG. 2, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 2, reference numeral 11 denotes an interlayer film as a first-layer interlayer film, 12 denotes a via hole as a first-layer via hole, and 13 denotes a first-layer via hole.
A plug as a layer plug, 14 an interlayer film as a second layer interlayer film, 15 a via hole as a second layer via hole, 16 a plug as a second layer plug,
Reference numeral 17 denotes an interlayer film as a third-layer interlayer film, reference numeral 18 denotes a via hole as a third-layer via hole, and reference numeral 19 denotes a plug as a third-layer plug.

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. In the present embodiment, a first-layer AL wiring 1 is formed on a plasma oxide film formed on a semiconductor substrate (not shown) configured as in the first embodiment. An interlayer oxide film is formed by a plasma CVD method such as HDP and then planarized by CMP to form an interlayer film 11 having a thickness of 300 nm. Next, K
After applying an rF resist to a thickness of 500 nm, a via hole resist mask having a hole diameter of 0.22 μm is formed by photolithography, and a via hole 12 penetrating to the first-layer AL wiring 1 is formed by dry etching.

This dry etching is performed by C ₅ F ₈ / O ₂ /
It is performed anisotropically by plasma using a mixed gas of Ar / CO. Next, the resist mask is removed by ashing using O ₂ gas plasma, and EKC (registered trademark) is further removed.
The Bolimer residue generated during dry etching and ashing is removed with the 265 solution (FIG. 2A).
At this time, the shape of the via hole 12 is such that although the resist is etched in a columnar shape, the etching amount is small, so that the upper portion of the hole is not jagged. In addition, the lower part of the hole becomes jagged due to the deposit from the first layer AL wiring 1,
Since the amount of over-etching in dry etching can be reduced, the degree of burrs is small.

Thereafter, a barrier metal of TiN is formed by sputtering, and W is sequentially formed inside the via hole 12 and on the interlayer film 11 by CVD. Then, W and TiN on the interlayer film 11 are removed by the CMP method to form the plug 13 (FIG. 2B). At this time, since the upper portion of the via hole 12 is smooth, TiN is uniformly formed on the inner wall of the upper portion of the via hole 12, so that one layer of hydrofluoric acid can be formed even in hydrofluoric acid cleaning for removing slurry after W-CMP polishing. It does not soak into the AL wiring 1 of the eyes. Next, a thickness of 200 nm is formed on the interlayer film 11 by a plasma CVD method.
The second interlayer film 14 is formed.

Next, after applying a KrF resist to a thickness of 500 nm, a via hole resist mask having a hole diameter of 0.24 μm slightly larger than the via hole 12 is formed by photolithography, and the via hole 15 penetrating to the plug 13 is opened by dry etching. Make a hole. Dry etching is performed under the same conditions as when the via hole 12 is formed. Then plug 13
The plug 16 is formed in the same manner as the method of forming the plug (FIG. 2).
(C)).

Further, a third interlayer film 17 is formed thereon with a thickness of 200 nm by a plasma CVD method, and then a hole diameter of 0.2 is formed by the same method as the formation of the via hole 13.
A via hole 18 of 2 μm is formed, and a plug 13 or 1
The plug 19 is formed in the same manner as the method of forming the plug 5 (FIG. 2D). Thereafter, the upper layer AL wiring is formed by the same steps as in the first embodiment.

As described above, according to the present embodiment, it is possible to obtain a via-hole shape without jaggedness, and to reduce the thickness of the resist mask by dividing the opening of the via-hole into three times, thereby reducing the accuracy of the hole diameter. Can be improved, and a multilayer wiring structure with less defects can be obtained.

[0034]

As described above, according to the first aspect of the present invention, the step of forming the first-layer metal wiring on the insulating film provided on the semiconductor substrate and the step of forming the interlayer oxide film on the metal wiring Depositing and planarizing the interlayer oxide film to form an interlayer film; providing a photoresist film having via holes patterned on the planarized interlayer film; and performing the planarization using the photoresist film as a mask. Forming a via hole by dry-etching the formed interlayer film, forming a plug in the via hole, and forming a second-layer metal wiring on the planarized interlayer film. Wherein the step of forming the via hole comprises: a first step of forming a part of the planarized interlayer film by dry etching using the photoresist film as a mask; and ashing. A second step of removing the photoresist film, a third step of removing a polymer residue generated by the dry etching and the ashing by a stripping solution, and a fourth step of performing a wet etching after the third step. And a fifth step of forming a via hole penetrating to the first-layer metal wiring by dry etch-back and a sixth step of removing a polymer residue generated by the dry etch-back with a stripper. Reduces and suppresses via hole burrs,
There is an effect that a semiconductor device having a multilayer wiring structure without contact failure can be manufactured.

According to the second aspect of the present invention, the fourth
In step (3), wet etching back is performed to reduce the thickness of the interlayer film by a predetermined amount using hydrofluoric acid, so that there is an effect that the burrs of the via holes can be efficiently reduced.

According to the third aspect of the present invention, in the step of forming a plug in the via hole, TiN of a barrier metal and W by a CVD method are deposited on the planarized interlayer film by a sputtering method. Since the TiN and the W of the barrier metal on the interlayer film are removed by the CMP method to form a W plug in the via hole, even during the hydrofluoric acid cleaning for removing the slurry after the W-CMP polishing, Is prevented from penetrating into the first-layer metal wiring, and there is an effect that disappearance of the metal wiring can be suppressed.

According to the fourth aspect of the present invention, a step of forming a first-layer metal wiring on an insulating film provided on a semiconductor substrate, and a step of forming an interlayer oxide film on the first-layer metal wiring A first step of planarizing the interlayer oxide film to form a first interlayer film, and patterning a first layer via hole on the planarized first interlayer film. A second step of forming a first-layer via hole using the formed photoresist film as a mask, and a first-layer via hole in the first-layer via hole formed in the planarized first-layer interlayer film. And a fourth step of forming a second interlayer film on the first interlayer film on which the plug is formed.
And a fifth step of forming a second-layer via hole on the second-layer interlayer film using a photoresist film obtained by patterning a hole having a diameter slightly larger than that of the first-layer via hole as a mask. A sixth step of forming a second-layer plug in the second-layer via hole formed in the second-layer interlayer film, and the second-layer plug in which the plug is formed. Forming a third interlayer film on the interlayer film;
And a third layer using a photoresist film in which a hole slightly smaller than the second-layer via hole and having the same diameter as the first-layer via hole is patterned as a mask on the third-layer interlayer film. And a ninth step of forming a third-layer plug in the third-layer via hole formed in the third-layer interlayer film. It is possible to obtain a via hole shape without jaggedness, improve the accuracy of the hole diameter, and obtain a multilayer wiring structure with less defects.

According to the fifth aspect of the present invention, in the second, fifth and eighth steps, the first-layer via hole and the second-layer The via hole of the third layer and the via hole of the third layer are opened, and the removal of the photoresist by ashing and the removal of the polymer residue generated by the dry etching and the ashing with the stripping solution are performed, thereby improving the precision of the formation of the via hole. There is an effect that can be.

According to the sixth aspect of the present invention, the first
In the step of forming the first-layer, second-layer, and third-layer plugs corresponding to the insides of the first, second, and third-layer via holes, respectively, the barrier metal TiN is formed by sputtering. Then, W is deposited on the interlayer film by CVD and the barrier metal TiN and W on the interlayer film are removed by CMP to form a W plug in the via hole. Even during the hydrofluoric acid cleaning for removing the slurry later, the hydrofluoric acid does not penetrate to the first-layer metal wiring, and thus the effect of suppressing the disappearance of the metal wiring can be obtained.

[Brief description of the drawings]

1A and 1B are a cross-sectional view and a top view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing another conventional semiconductor device.

5A and 5B are a cross-sectional view and a top view illustrating a state of occurrence of a problem caused by another conventional method for manufacturing a semiconductor device.

[Explanation of Signs] 1,6 AL wiring, 2, 7, 11, 14, 17 interlayer film, 8 resist mask, 9 hole, 10, 1
2,15,18 via holes, 5,13,16,19
plug.

   ────────────────────────────────────────────────── ─── Continuation of front page    F-term (reference) 4M104 BB02 BB30 CC01 DD08 DD09                       DD10 DD16 DD22 DD23 DD37                       DD43 DD75 FF18 FF22 HH12                       HH14 HH20                 5F004 BD01 DA00 DA01 DA16 DA23                       DA26 DB03 DB26 EA10 EA27                       EA28 EB01 EB03 FA08                 5F033 HH08 JJ19 JJ33 KK08 NN06                       NN07 NN37 PP06 PP15 QQ08                       QQ09 QQ11 QQ16 QQ18 QQ19                       QQ31 QQ37 QQ48 QQ94 QQ96                       RR04 SS15 XX01 XX03 XX18                       XX21

Claims (6)

[Claims] A step of forming a first-layer metal wiring on an insulating film provided on a semiconductor substrate; depositing an interlayer oxide film on the metal wiring; planarizing the interlayer oxide film to form an interlayer film; Forming, forming a via hole patterned photoresist film on the planarized interlayer film, and dry etching the planarized interlayer film using the photoresist film as a mask to form a via hole. Forming a plug in the via hole; and forming a second-layer metal wiring on the planarized interlayer film, wherein the via hole is formed. A first step of forming a hole in the flattened interlayer film by dry etching using the photoresist film as a mask, and a step of removing the photoresist film by ashing. 2
A third step of removing a polymer residue generated by the dry etching and the ashing with a stripping solution; a fourth step of performing a wet etching after the third step; and a first step of performing a dry etch back. A method of manufacturing a semiconductor device, comprising: a fifth step of forming a via hole penetrating to a metal wiring of a layer; and a sixth step of removing a polymer residue generated by the dry etch back with a stripping solution. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the fourth step, wet etch-back is performed by using hydrofluoric acid to reduce the interlayer film by a predetermined amount. 3. The step of forming a plug in the via hole, wherein TiN and CV of a barrier metal are formed by a sputtering method.
W is deposited on the flattened interlayer film by the D method, and TiN of the barrier metal and W on the interlayer film are CM
3. The method of manufacturing a semiconductor device according to claim 1, wherein a W plug is formed in the via hole by removing by a P method. 4. A step of forming a first-layer metal wiring on an insulating film provided on a semiconductor substrate; and depositing an interlayer oxide film on the first-layer metal wiring, and then forming the interlayer oxide film. A first step of flattening the first layer to form a first layer interlayer film, and a first step of using a photoresist film in which a first layer via hole is patterned on the flattened first layer interlayer film as a mask. A second step of forming a via hole of the first layer, and the first step formed in the planarized first interlayer film.
Forming a first-layer plug in a first-layer via hole;
And a second step on the first interlayer film on which the plug is formed.
A fourth step of forming an interlayer film of a second layer, and a second layer using a photoresist film in which a hole having a diameter slightly larger than the via hole of the first layer is patterned on the interlayer film of the second layer as a mask. A fifth step of forming a second-layer via hole, a sixth step of forming a second-layer plug in the second-layer via hole formed in the second-layer interlayer film, A third layer is formed on the second interlayer film on which the
A seventh step of forming an interlayer film of the layer, and a hole having a diameter slightly smaller than the via hole of the second layer and having the same diameter as the via hole of the first layer is patterned on the interlayer film of the third layer. An eighth step of forming a third-layer via hole using the photoresist film as a mask, and forming a third-layer plug in the third-layer via hole formed in the third-layer interlayer film 9. A method of manufacturing a semiconductor device, comprising: 5. In the second, fifth and eighth steps,
The first-layer via hole, the second-layer via hole, and the third-layer via hole are opened corresponding to the respective steps by dry etching, and the photoresist is removed by ashing and the stripping solution is removed. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the polymer residue generated by the dry etching and the ashing is removed. 6. The first layer, the second layer, and the second layer corresponding to the via holes of the first layer, the second layer, and the third layer, respectively.
In the step of forming the plugs of the third layer and the third layer, TiN of a barrier metal is formed by sputtering and W is formed by CVD.
6. A W plug is formed in the via hole by depositing Ti on the interlayer film and removing TiN and the W of the barrier metal on the interlayer film by a CMP method. A method for manufacturing a semiconductor device.