JP3282607B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dual damascene (Dual damascene) for simultaneously forming a connection hole and a wiring groove in an insulating film.
The present invention relates to a method for manufacturing a semiconductor device using a damascene process.

[0002]

2. Description of the Related Art Along with the miniaturization of semiconductor devices, there is an increasing demand for multilayer and fine wiring. As a means to meet the demand, development of a damascene process is being promoted.

In the damascene process, a wiring groove is formed in advance by etching, and the wiring groove is formed by sputtering or CVD.
A metal of W, Al alloy, or Cu is buried in the wiring groove, and then, the CMP (C
chemical Mechanical Polish
ing) to form a wiring groove.

[0004] Further, the connection hole and the groove wiring are etched in advance, and thereafter, metal embedding and metal CM are performed.
Dual damascene (Dual Damascene) in which a connection hole and a wiring groove are simultaneously formed by performing P
A process has been proposed and is under active development.

[0005] This dual damascene process has attracted great expectations in terms of cost because the number of steps can be simplified.

In this dual damascene process,
An etching method for connecting holes and trench wiring has been proposed. The method will be described with reference to the drawings.

As shown in FIG. 5, first, a first interlayer insulating film 2, an etching stopper film 3, and a second interlayer insulating film 4 are sequentially deposited. After the first interlayer insulating film 2 is deposited, C
Generally, planarization is performed using MP or an etch-back method.

Next, after a resist pattern for forming a connection hole is formed by lithography, the second interlayer insulating film 4 and the etching stopper film 3 are sequentially etched using the resist pattern as a mask to open a connection hole 7.

Next, a resist pattern 6 for forming a wiring groove is formed on the second interlayer insulating film 4 by lithography.

Subsequently, as shown in FIG. 6, using the resist pattern 6 as a mask, the first interlayer insulating film 2 as the second interlayer insulating film 4 and the connection hole 7 is etched.

[0011] Etching stopper film 3 and lower wiring 1
Serves as an etching stopper, so that the connection hole 7 and the wiring groove 8 are formed at the same time. Finally, the resist pattern 6 is removed. Reference numeral 1 denotes a lower wiring.

[0012]

However, the method shown in FIGS. 5 and 6 has a problem that it is difficult to control the etching.

Since the etching gas is hardly supplied to the inside of the connection hole 7, the etching amount of the connection hole 7 is smaller than the etching amount of the wiring groove 8. If the etching is not performed excessively, the connection hole 7 is opened. Can not do it.

If the etching is performed excessively, the corners are sputtered and etched, so that the etching stopper film 3 near the upper portion of the connection hole 7 and the first interlayer insulating film 2 in the lower layer are also etched. Therefore, there is a problem that a target dual damascene shape cannot be obtained.

In the method shown in FIGS. 8 and 9, the first
After sequentially depositing the interlayer insulating film 2 and the etching stopper film 3, a resist pattern for forming the connection hole 7 is formed by lithography.

Using this resist pattern as a mask, the etching stopper film 3 and the first interlayer insulating film 2 are etched to form a connection hole 7 as shown in FIG. 8, and a second interlayer insulating film 4 is deposited.

Next, as shown in FIG. 9, a resist pattern 6 for forming a wiring groove is formed on the second interlayer insulating film 4 by lithography.

Using this resist pattern 6 as a mask, the second interlayer insulating film 4 is etched, and a connection hole 7 and a groove wiring 8 are simultaneously formed as shown in FIG.

However, the second method shown in FIGS. 8 and 9 has a problem in the controllability of etching for simultaneously forming the connection hole 7 and the wiring groove 8 as in the first method. As described above, there is a problem that the corner portion of the opening edge of the connection hole 7 is largely etched into a tapered shape .

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming good connection holes and wiring grooves with high controllability in a dual damascene process.

[0021]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device in which a connection hole and a wiring groove are simultaneously formed in an insulating film using a dual damascene process. And on the lower wiring
, A first interlayer insulating film, a first etching stopper
After sequentially forming a film and a second interlayer insulating film, a second interlayer insulating film is formed.
Insulating the insulating film and the first etching stopper film sequentially
To form a connection hole, and then a second etching strike is performed.
Depositing a stopper film on the inner surface of the connection hole and on the second interlayer insulating film;
After that, the second etching stopper film is formed on the side wall of the connection hole.
Etching so that only the portion remains, and then the second interlayer
Form a resist pattern for forming wiring grooves on the insulating film
And forming the second interlayer insulating film into a first etching stopper film.
At the same time as forming the wiring groove by etching to the depth
Then, the first interlayer insulating film is etched to a depth to reach the lower wiring.
To form a connection hole, then a resist pattern,
First etching stopper film and second etching stopper
This is to remove the topper film .

[0022]

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

1 to 4 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

First, as shown in FIG.
For example, by using a plasma CVD method or the like, the SiO ₂ film 2 having a thickness of, for example, 800 nm as the first interlayer insulating film 2 is formed.
An Si ₃ N ₄ film 3 having a thickness of, for example, 100 nm as the first etching stopper film 3 and a SiO ₂ film 4 having a thickness of, for example, 800 nm as the second interlayer insulating film 4 are sequentially formed.

Next, after a resist pattern (not shown) for forming a connection hole is formed on the SiO ₂ film 4 by lithography, the resist pattern is used as a mask to form Si.
The O ₂ film 4 and the Si ₃ N ₄ film 3 are sequentially etched to open a connection hole 7.

Subsequently, after removing the resist pattern, an Si ₃ N ₄ film 5 having a thickness of, for example, 20 nm as the second etching stopper film 5 is replaced with a SiO ₂ film including the connection hole 7.
₂ Deposited on the film 4.

Next, as shown in FIG. 2, the Si ₃ N ₄ film 5 is
For example, etching is performed using an anisotropic etching method using a mixed gas of CHF ₃ and O ₂ to leave the Si ₃ N ₄ film 5 only on the side wall of the connection hole 7.

Next, a resist pattern 6 for forming a wiring groove is formed on the SiO ₂ film 4.

Next, as shown in FIG. 3, the SiO ₂ film 4 is etched using the resist pattern 6 as a mask.

[0031] etching the SiO ₂ film 4, wiring groove 8 as shown in FIG. 3, and a depth of the Si ₃ N ₄ film 3 as an etching stopper layer, there is no the Si ₃ N ₄ film 3 The connection hole 7 is formed by etching to the depth of the lower wiring 1.

In this case, the diameter of the connection hole 7 to be formed is determined by the diameter of the connection hole 7 formed in the second interlayer insulating film 4 and the thickness of the second etching stopper film 5 remaining on the side wall of the connection hole 7. The value is obtained by subtracting twice the thickness.

Therefore, the diameter of the opening pattern for forming the connection hole provided in the resist pattern 6 is set to the target diameter of the connection hole 7 and the thickness of the second etching stopper film 5 remaining on the side wall of the connection hole 7. Is set as a value obtained by adding twice the value of.

Next, as shown in FIG.
After removing 6, a first etching stopper film is formed.
Si_ThreeN_FourA film 3 and a second etching stopper film
Si _ThreeN_FourThe film 5 is made of, for example, SF mainly containing a radical component.₆When
An isotropic drive using a plasma method using a gas mixture of He.
Etch and remove.

As described above, in the embodiment of the present invention, when the connection hole 7 and the wiring groove 8 are simultaneously formed, the etching is
The process is performed until the connection hole 7 reaches the lower wiring 1. that time,
A second etching stopper film and in part by even the sputter the Si ₃ N ₄ film 5 remaining on the side wall of the connection hole 7 is etched, until the end of etching, Si ₃ remaining on the side wall of the connection hole 7 N _{Since the fourth} film 5 rises above the first etching stopper film 3, the corner of the opening edge of the connection hole 7 provided in the first etching stopper film 3 is prevented from being excessively etched. As a result, the connection holes 7 can be opened with substantially the same diameter, and the connection holes 7 and the wiring grooves 8 having good shapes can be obtained.

Although one embodiment of the present invention has been specifically described, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. For example, in the embodiment described above, Si ₃ N ₄ after removing the resist pattern 6 as shown in FIGS. 3 and 4
Although the film 3 and the Si ₃ N ₄ film 5 are removed, the wiring groove forming resist pattern 6 may be removed after the Si ₃ N ₄ film 3 and the Si ₃ N ₄ film 5 are removed.

Although the SiO ₂ film is used as the first interlayer insulating film 2 and the second interlayer insulating film 4, SiO _x (x ≠
2) A film, a SiOF film, or a film obtained by adding B, P, or the like to these films may be used. In addition, HSQ (hydroge
nsilsesquioxane) membrane or PTFE (po
An organic film such as a ly-tetrafluoroethylene film may be used.

For removing the Si ₃ N ₄ film, SF ₆ and H
Although an isotropic dry etching method using a mixed gas of e is used, an anisotropic dry etching method using a mixed gas of CHF ₃ and O ₂ or the like may be used.

Further, Si as an etching stopper layer
₃ N ₄ The film was used, so long as it has an etching resistance during the etching of the insulating film may also be any of those may be an organic film such as a polymer.

[0040]

As described above, according to the present invention, when a connection hole and a wiring groove are simultaneously formed in an insulating film using a dual damascene (Dual Damascene) process, the connection hole formed in the insulating film is removed. In order to suppress an increase in the etching amount due to sputtering on the corners of the opening edge,
Deterioration of the shape of the connection hole and the wiring groove can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example in the order of manufacturing steps.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example in the order of manufacturing steps.

FIG. 7 is a cross-sectional view illustrating a problem in a method of manufacturing a semiconductor device according to a conventional example.

FIG. 8 is a cross-sectional view showing a method of manufacturing a semiconductor device according to another conventional example in the order of manufacturing steps.

FIG. 9 is a cross-sectional view showing a method of manufacturing a semiconductor device according to another conventional example in the order of manufacturing steps.

FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device according to another conventional example in the order of manufacturing steps.

[Description of Signs] 1 Lower layer wiring 2 First interlayer insulating film 3 First etching stopper film 4 Second interlayer insulating film 5 Second etching stopper film 6 Resist pattern 7 Connection hole 8 Wiring groove

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device, wherein a connection hole and a wiring groove are simultaneously formed in an insulating film by using a dual damascene process, wherein a first interlayer insulating film and a first etching
After sequentially forming a topper film and a second interlayer insulating film,
The second interlayer insulating film and the first etching stopper film
Next, a contact hole is opened by etching, and then a second etch is performed.
The stopper film on the inner surface of the connection hole and on the second interlayer insulating film.
After deposition on the second etching stopper film is connected
Etch to remain only on the side wall of the hole, then
A resist pattern for forming a wiring groove is formed on the second interlayer insulating film.
And forming a second interlayer insulating film on the first etching stop.
When the wiring groove is formed by etching to the depth to the par film
At the same time, extend the first interlayer insulating film to the depth to reach the lower wiring.
Etch to form contact holes, then resist pattern
, A first etching stopper film and a second etchant
A method for manufacturing a semiconductor device, comprising: removing a stopper film .