KR100835414B1 - Method for manufacturing in semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent a via open fail effect by forming a via and trench without using a novolac process before a trench etching process. An IMD(403) is deposited on a semiconductor substrate(401). A photoresist pattern is formed on the IMD in order to define a via region. The via region is defined by etching the photoresist pattern. A spacer is formed by depositing SiN on the via region and the IMD and performing an etch process. A photoresist pattern for defining a trench region is formed on the spacer and the IMD. A via and the trench region are formed by performing simultaneously a first trench and via etch process and a second trench and via etch process. A barrier metal is deposited on the via and trench region and the IMD. A via and trench(417) are formed by planarizing the barrier metal.

Description

Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING IN SEMICONDUCTOR DEVICE}

1A to 1J illustrate a method of manufacturing a conventional semiconductor device,

2A and 2B are diagrams illustrating a via open fail caused by a manufacturing process of a conventional semiconductor device;

3 is a view in which an abnormal profile of a shape of a fence is formed by a process of manufacturing a conventional semiconductor device

4A to 4I are diagrams illustrating processes of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

5A through 5I are diagrams illustrating processes for manufacturing a semiconductor device according to another exemplary embodiment of the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in a copper manufacturing process, vias and trenches can be formed without performing a no-block process performed before trench etching, which is a process after via formation. It's about how.

As noted, in the copper manufacturing process, the process for forming vias and trenches is as shown in FIG.

First, in order to form vias and trenches in a copper manufacturing process, interlayer material (IMD) in multiple layers, for example, IMD1 (103), IMD2 (105), and IMD1 (107) on top of silicon nitride (SiN) 101 is formed. ), The lower metal (Cu) 109 is formed on the IMD2 105 and the IMD1 107 as shown in FIG. 1A, and the entire surface of the SiN 111 is deposited thereon. By sequentially depositing IMD1 113, IMD2 115, and IMD1 117 on the SiN 111, and then performing a photo lithography process to selectively remove a portion of the front deposited PR, As an example, as shown in FIG. 1A, a PR pattern 119 is formed on the IMD1 117 to define a via region.

Next, the PR pattern 119 formed as described above is etched using a mask to remove the sequentially deposited IMD1 113, IMD2 115, and IMD1 117, as shown in FIG. 1B. As described above, the via 121 is formed on the SiN 111 by performing the SiN 111 as a stop layer.

Subsequently, a Novolac PR 123 is entirely deposited on the via 121 and the IMD1 117 formed on the SiN 111, for example, as illustrated in FIG. 1C.

Next, a stripping process is performed on the front-deposited noblock PR 123 to remove the PR 123 so as to remain partially inside the via 121 as illustrated in FIG. 1D.

Next, with the PR 123 partially remaining inside the via 121, a photolithography process is performed to selectively remove a portion of the front deposited PR, as an example, as shown in FIG. 1E, by using IMD1. A PR pattern 125 for defining a trench region is formed on the upper portion 117.

The trench 127 is formed as shown in FIG. 1F by performing the etching process using the PR pattern 125 formed as described above with a mask to remove the sequentially deposited IMD2 115 and IMD1 117. . Thereafter, a stripping process is performed to remove some of the remaining PR 123a in the via 121 and some of the remaining PR 125a on the IMD 117 as shown in FIG. 1G.

Next, the SiN 111 on the lower metal 109 is etched using the IMD having the trench 127 and the via 121 as a barrier, for example, the via and trench regions 129 as shown in FIG. 1H. ).

Subsequently, a barrier metal (Ta / TaN) 131 is deposited on the via, trench region 129, and IMD1 117, for example, as illustrated in FIG. 1I.

Finally, the via and trenches 133 are formed by planarization of the barrier metal (Ta / TaN) 131 deposited through CMP (Chemical Mechanical Polishing), which is a planarization process, as shown in FIG. 1J.

As described above, when the process is performed in the manner of FIGS. 1A to 1J in which trenches and vias are formed in the copper manufacturing process, the noblock PR 123 filled on the via portion before the trench RIE after via formation is not completely removed. It can cause Via Open fail as shown in 2a and 2b.

In addition, when the trench etching is performed while the noblock PR 123 is filled, the IMD angle is disturbed at the noblock boundary, for example, as shown in FIG. It has a problem that can cause serious adverse effects.

Accordingly, the present invention has been made to solve the above-described problems, the object is to form vias and trenches in the copper manufacturing process, without performing the no-block process before the trench etching, which is the next process after the via formation (Via) The present invention provides a method for manufacturing a semiconductor device.

In a consistent aspect of the present invention for achieving the above object, a method of manufacturing a semiconductor device includes (a) depositing an IMD on a semiconductor substrate and forming a PR pattern to define a via region on the deposited IMD. And via (b) etching the PR pattern formed in step (a) with a mask to define a via region, depositing SiN on the defined via region and the IMD, and then performing an etching process to form a spacer. Forming a PR pattern to define a trench region on the spacer formed in the step (b) and the IMD, and (d) the PR pattern formed in the step (c). Forming a via and a trench region by first etching and via etching the second via at the same time as the mask, and then performing second etching, and (e) the via and trench regions formed in step (d). And on top of IMD Depositing a barrier metal and planarizing the deposited barrier metal to form vias and trenches.

In addition, in another aspect of the present invention for achieving the above object, a method of manufacturing a semiconductor device includes (a1) depositing an IMD on a semiconductor substrate, and forming a PR pattern to define a via region on the deposited IMD. And forming a via region by (b1) etching the PR pattern formed in step (a1) with a mask, defining a via region, depositing SiN on the defined via region and the IMD, and then performing an etching process. Forming a spacer, (c1) forming a PR pattern to define a trench region on the spacer formed in the step (b1) and the IMD, and (d1) forming the step (c1). Forming a via and a trench region by performing a first trench and a via etch with a PR pattern as a mask, and performing a second etch at the same time, and (e1) a via formed in the step (d1). And trench area And depositing a barrier metal on the IMD and planarizing the deposited barrier metal to form vias and trenches.

Hereinafter, a plurality of embodiments of the present invention may exist, and a preferred embodiment will be described in detail with reference to the accompanying drawings. Those skilled in the art will appreciate the objects, features and advantages of the present invention through this embodiment.

4A to 4I are diagrams illustrating processes of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

That is, referring to FIG. 4A, an IMD 403 is deposited on a semiconductor substrate (P-Substrate) (eg, a silicon substrate, a ceramic substrate, a polymer substrate, etc.) 401 by performing a coating process such as spin coating.

Next, a photolithography process, which is an exposure process using a reticle designed in an arbitrary pattern of interest, and a photolithography process, which are developed, are selectively performed to remove a part of the front surface deposited PR, as an example illustrated in FIG. 4B. As described above, a PR pattern 405 is formed on the IMD 403 to define a via region.

Next, the via pattern 405 formed as described above is etched with a mask to remove the deposited IMD 403, thereby defining the via region 407 as shown in FIG. 4C. In this case, the via area 407 is defined to be larger than the drawn size (design rule size).

Subsequently, an SiN 409 is deposited on the IMD 403 in which the via region 407 is defined as an example, as shown in FIG. 4D, followed by an etching (eg, dry etching) process. As shown in FIG. 4E, a SiN spacer 409a is formed.

Next, a photolithography process is performed on the formed SiN spacer 409a and the IMD 403 to selectively remove a portion of the front deposited PR, for example, as shown in FIG. 4F, as shown in FIG. 4F. A PR pattern 411 for defining a trench region is formed in the trench.

Next, the first trench and the via etching process are performed using the PR pattern 411 formed as described above as a mask. In this case, the etching ratio of SiN is twice as fast as the etching ratio of oxide, that is, the etching ratio of SiN and the etching ratio of oxide are 2: 1, and the size of the upper portion of the via as shown in FIG. 4G is etched. Is largely formed 413, and second etching is performed to simultaneously form vias and trench regions 415, as shown in FIG. 4H. Thereafter, a stripping process is performed to remove some of the remaining PR patterns 411 on the IMD 403.

Lastly, barrier metal (Ta / TaN) is deposited on the via, trench region 415 and IMD 403 over the entire surface, and CMP, which is a planarization process for the barrier metal (Ta / TaN) deposited on the front surface, is one example. As shown in FIG. 4I, it is planarized to form vias and trenches 417.

5A to 5I are diagrams illustrating processes for manufacturing a semiconductor device according to another exemplary embodiment of the present invention.

That is, referring to FIG. 5A, an IMD 503 is deposited on a semiconductor substrate (P-Substrate) (eg, a silicon substrate, a ceramic substrate, a polymer substrate, etc.) 501 by performing a coating process such as spin coating.

Next, a photolithography process, which is an exposure process and a development process using a reticle designed in an arbitrary pattern of interest, is performed to selectively remove a portion of the front-deposited PR, as an example illustrated in FIG. 5B. As described above, a PR pattern 505 for defining a via region is formed on the IMD 503.

Next, the via pattern 505 formed as described above is etched with a mask to remove the deposited IMD 503, thereby defining the via region 507 as shown in FIG. 5C. In this case, the via area 507 is defined to be larger than the drawn size (design rule size).

Subsequently, SiN 509 is deposited on the IMD 503 in which the via region 507 is defined as an example, as shown in FIG. 5D, followed by an etching (eg, dry etching) process. As shown in FIG. 5E, a SiN spacer 509a is formed.

Next, a photolithography process is performed on the formed SiN spacer 509a and the IMD 503 to selectively remove a portion of the front deposited PR, for example, as shown in FIG. 5F, as shown in FIG. 5F. A PR pattern 511 is formed in the trench to define the trench region.

Next, the first trench and the via etching process are performed using the PR pattern 511 formed as described above as a mask. At this time, the etching ratio of the SiN and the etching ratio of the oxide (oxide) is etched under a condition of 1: 1, and the size of the upper portion of the via is constantly formed as shown in FIG. 5G (513), and the second etching is performed. As shown in FIG. 5H, the via and the trench region 515 are simultaneously formed. Thereafter, a stripping process is performed to remove some of the remaining PR patterns 511 on the IMD 503.

Finally, barrier metal (Ta / TaN) is deposited on the via, trench region 515 and IMD 503 over the entire surface, and CMP, which is a planarization process for the barrier metal (Ta / TaN) deposited on the front surface, is one example. Planarization as shown in FIG. 5I forms vias and trenches 517.

Therefore, according to the present invention, in the copper manufacturing process, vias and trenches are formed without performing the no-block process performed before the trench etching, which is the next process after the via formation. Via open fail, and also the formation of a fence-shaped abnormal profile can solve the problem that can seriously affect the reliability.

In addition, since the present invention is disclosed as a right within the spirit and claims of the present invention, the present invention may include any modification, use and / or adaptation using general principles, and the present invention as a matter deviating from the description of the present specification. It includes everything that falls within the scope of known or customary practice in the art to which it belongs and falls within the scope of the appended claims.

As described above, in the copper manufacturing process, by forming the via and the trench without performing the no-block process performed before the trench etching, which is the next process after the via formation, the no-block process is performed by the no-block process. Via open fail and the occurrence of an abnormal profile of a shape of a fence are formed to solve a problem that may seriously affect reliability, thereby improving yield and reliability of a semiconductor device.

Claims (6)

As a manufacturing method of a semiconductor device, (a) depositing an IMD on a semiconductor substrate, and forming a PR pattern to define a via region on the deposited IMD; (b) defining a via region by performing an etching process using a PR pattern formed in step (a) as a mask, depositing SiN on the defined via region and the IMD, and then performing an etching process to form a spacer. To do that, (c) forming a PR pattern for defining a trench region on the spacer and the IMD formed in the step (b); (d) forming vias and trench regions by performing primary trench and via etching with the PR pattern formed in step (c) as a mask larger than the via region, and performing secondary etching simultaneously. Wow, (e) depositing a barrier metal on the via and trench regions formed in step (d) and an IMD, and planarizing the deposited barrier metal to form vias and trenches Method for manufacturing a semiconductor device comprising a. The method of claim 1, The via region defined in step (a) is larger than the drawn size (design rule size). The method of claim 1, The first trench and the via etching in the step (d), the etching ratio of the SiN and the etching ratio of the oxide (oxide) in the manufacturing method of the semiconductor device, characterized in that 2: 1. As a manufacturing method of a semiconductor device, (a1) depositing an IMD on a semiconductor substrate, and forming a PR pattern to define a via region on the deposited IMD; (b1) defining a via region by performing an etching process using a PR pattern formed in step (a1) as a mask, depositing SiN on the defined via region and the IMD, and then performing an etching process to form a spacer To do that, (c1) forming a PR pattern on the spacer formed in the step (b1) and the IMD, and defining a trench region; (d1) forming a via and a trench region by performing a first trench and a via etching with the PR pattern formed in the step (c1) as a mask and performing a second etching at the same time; (e1) depositing a barrier metal on the vias and trench regions formed in the step (d1) and an IMD, and planarizing the deposited barrier metal to form vias and trenches Method for manufacturing a semiconductor device comprising a. The method of claim 4, wherein The via region defined in step (a1) is larger than the drawn size (design rule size). The method of claim 4, wherein The first trench and the via etching in the step (d1), the etching ratio of the SiN and the etching ratio of the oxide (oxide) of the semiconductor device manufacturing method, characterized in that for performing 1: 1.

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