JP2000208620A - Production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form satisfactory Cu wiring with high reproducibility, while using a dual damascene process. SOLUTION: A hole for connection hole is formed by etching through a second wiring correspondent inter-layer insulating film 11, a second wiring stopper film 10 and a wiring inter-layer insulating film 9. The entire surface is coated with an organic coating film 20, such as resist by rotary coating and inside the hole for connection hole, the organic coating film 20 is left by a method such as full etch back, so that the surface of the organic coating film 20 can be higher than the lower surface of the second wiring correspondent inter-layer insulating film. Afterwards, an antireflection film 21 is formed over the entire surface about from 500 to 1,000 angstroms, and a groove 15 for second wiring layer is formed by etching the second wiring corresponding inter-layer insulating film 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a multilayer wiring.

[0002]

2. Description of the Related Art With the generation of semiconductor integrated circuits, the speed and performance of devices are being promoted. The signal delay that determines the speed of the device is divided into a gate delay component and a wiring delay component. The gate delay component tends to decrease with miniaturization of the transistor, while the wiring delay component tends to increase with miniaturization of the wiring layer. Since the wiring delay is determined by the product CR of the wiring capacitance C and the wiring resistance R, application of low-resistance Cu to the wiring material is being studied as a measure to suppress the wiring delay.

When a Cu wiring is applied, it is difficult to perform processing by a conventional etching process. Therefore, a damascene process, which is an embedded process, has been proposed. Above all, after digging a groove corresponding to a connection hole or a wiring in the interlayer insulating film in advance, burying Cu, and performing Cu polishing by CMP polishing.
A dual damascene process in which wiring is formed by flattening layers is being studied.

FIGS. 22 to 25 are sectional views showing the steps of a method for forming a Cu wiring by a conventional dual damascene process. The description will be made sequentially according to the drawings. First, as shown in FIG. 22, a first wiring stopper film 2 and a first wiring corresponding interlayer insulating film 3 are sequentially formed on a base interlayer insulating film 1, and a barrier metal 5 and a first wiring stopper film 2 are formed on the first wiring corresponding interlayer insulating film 3. The first wiring layer 7 is formed by embedding the metal film 6. Further, a connection hole stopper film 8, a wiring interlayer insulating film 9, a second wiring stopper film 10, and a second wiring corresponding interlayer insulating film 11 are sequentially formed.

[0005] Next, as shown in FIG. 23, a resist pattern 12 is formed on the second wiring-corresponding interlayer insulating film 11, and a hole 13 for a connection hole is formed on the first wiring layer 7 using the resist pattern 12 as a mask. Perform formation. In this case, the second wiring-corresponding interlayer insulating film 11, the second wiring stopper film 10, and the wiring interlayer insulating film 9 are sequentially etched using the connection hole stopper film 8 as an etching stopper.

Next, as shown in FIG. 24, the resist pattern 12 is removed to complete a hole 13 for a connection hole. After that, a resist pattern 14 is formed on the second wiring corresponding interlayer insulating film 11. Next, as shown in FIG. 25, the second wiring stopper film 10 is formed using the resist pattern 14 as a mask.
Is used as an etching stopper to etch the second wiring-corresponding interlayer insulating film 11 to form a groove 15 for the second wiring layer.

Thereafter, a barrier metal such as TaN or TiN and a metal film such as Cu are formed on the entire surface including the groove 15 for the second wiring layer and the hole 13 for the connection hole. CMP polishing is performed to form a barrier metal such as TaN or TiN and C on the second wiring-corresponding interlayer insulating film 11 and the wiring interlayer insulating film 9.
A second wiring layer made of a metal film such as u and a connection hole are formed.

[0008]

The method of forming a Cu wiring by the conventional dual damascene process is as described above. As shown in FIG. 26, (a) is a plan view and (b) is a sectional view. In order to form a groove 15 for a second wiring layer, a resist pattern 14 is formed on the second wiring-corresponding interlayer insulating film 11.
In the step of forming (1), reflection (halation) from Cu forming the first wiring layer 7 causes a deformation 14a of the shape of the resist pattern 14. Further, there is a problem that the shape of the groove 15 for the second wiring layer, which is an etching pattern formed by using the resist pattern 14a as a mask, is broken.

As shown in FIG. 24, the connection hole stopper film 8 serving as an etching stopper when forming the hole 13 for the connection hole is used for etching when forming the groove 15 for the second wiring layer. It is exposed on the bottom surface of the connection hole 13. Therefore, the connection hole stopper film 8 is directly attacked by the etching gas when forming the groove 15 for the second wiring layer and disappears. Further, as shown in FIG. 27, Cu as the first wiring layer 7 is exposed and etched. This is because not only the shape of the wiring layer changes but also Cu is exposed in the hole 13 for the connection hole, so that in the subsequent step of removing the resist pattern 14 using oxygen, Cu oxidization occurs and There is a problem that the resistance value is increased.

[0010] As shown in FIG. 24, an exposed surface of the second wiring stopper film 10 also exists in the hole 13 for the connection hole at the time of etching when forming the groove 15 for the second wiring layer. Therefore, as shown in FIG. 27, the exposed surface of the second wiring stopper film 10 is also directly attacked by the etching gas when forming the groove 15 for the second wiring layer, and a part of the second wiring stopper film 10 is lost. And holes 13 for connection holes
Is formed in an expanded shape. As a result, there is a problem that the resistance value of the connection hole varies.

As a solution to these problems, for example, Japanese Patent Application Laid-Open No. Hei 10-223755 discloses a method in which an organic antireflection film (hereinafter, referred to as an organic ARC film) is embedded in a connection hole by a coating method. . However, as shown in FIG. 28, there has been a problem that the embedding failure of the organic ARC film 19 occurs as the aspect ratio of the connection hole 13 increases.

The present invention has been made to solve the above problems, and has as its object to provide a manufacturing method capable of forming a good Cu wiring with good reproducibility using a dual damascene process. And

[0013]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a connection hole stopper film and a wiring interlayer insulating film on a first wiring corresponding interlayer insulating film including a first wiring layer. And a step of sequentially laminating a second wiring-corresponding interlayer insulating film, and forming the second wiring-corresponding interlayer insulating film and the wiring interlayer insulating film by using the resist pattern for connection holes as a mask and using the connection hole stopper film as an etching stopper. Forming a hole for the connection hole by etching in order, forming an organic coating film on the entire surface including the hole for the connection hole and the second wiring-corresponding interlayer insulating film; A step of performing etch back on the entire surface of the film;
A step of forming an anti-reflection film on the entire surface and a step of forming the groove for the second wiring layer by etching the second wiring-corresponding interlayer insulating film using the resist pattern for the second wiring layer as a mask Removing the resist pattern and the organic coating film for the second wiring layer; removing the connection hole stopper film; forming a barrier between the hole for the connection hole and the groove for the second wiring layer. Forming a connection hole and a second wiring layer by burying a metal and a metal film.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: removing all of the organic coating film on the second wiring-corresponding interlayer insulating film in the step of etching back the entire surface of the organic coating film. The organic coating film is left only in the connection hole.

According to a third aspect of the present invention, in the method of fabricating a semiconductor device, in the step of performing etch back on the entire surface of the organic coating film, the thin film of the organic coating film is left on the second wiring interlayer insulating film. It was done.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, the upper surface of the organic coating film in the connection hole when the entire surface of the organic coating film is etched back is the second interlayer insulating film corresponding to the wiring. It is located above the lower surface.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, a contact hole stopper film, a wiring interlayer insulating film, and a second wiring stopper are formed on the first wiring corresponding interlayer insulating film including the first wiring layer. A step of sequentially laminating a film and a second wiring-corresponding interlayer insulating film, and etching the second wiring-corresponding interlayer insulating film and the second wiring stopper film by using a resist pattern for a connection hole as a mask to form the connection. Forming an upper portion of the hole for the hole, forming an antireflection film on the entire surface including the upper portion of the hole for the connection hole and the second wiring-corresponding interlayer insulating film, and forming a second wiring The second wiring is formed by etching the antireflection film and the second wiring-corresponding interlayer insulating film using the second wiring stopper film as an etching stopper using the layer resist pattern as a mask. At the same time as forming the groove for the connection hole, the lower part of the hole for the connection hole is formed by etching the wiring interlayer insulating film from the bottom of the upper part of the hole for the connection hole using the connection hole stopper film as an etching stopper. Removing the resist pattern for the second wiring layer, removing the connection hole stopper film, and removing the lower portion of the connection hole and the groove for the second wiring layer. Forming a connection hole and a second wiring layer by embedding a barrier metal and a metal film.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 1 to 14 are sectional views showing steps of a method for forming a Cu wiring by a dual damascene process according to the first embodiment of the present invention. The description will be made sequentially according to the drawings. First, as shown in FIG. 1, after forming various elements on a silicon substrate, a first wiring layer is formed on a base interlayer insulating film 1 made of a silicon oxide film of about 1 μm. A silicon nitride film serving as the wiring stopper film 2 is formed in a thickness of about 500 to 2000 Å. Next, a silicon oxide film corresponding to the first wiring layer is formed to a thickness of about 0.1 to 2 μm to form the first wiring corresponding interlayer insulating film 3.

Next, as shown in FIG. 2, the first wiring-corresponding interlayer insulating film 3 is etched using the resist pattern 4 as a mask and the first wiring stopper film 2 as an etching stopper to form a first wiring layer. Form a groove. Next, FIG.
As shown in FIG. 2, the entire surface including the groove for the first wiring layer is covered with TaN.
A metal film 6 such as a barrier metal 5 and Cu is formed. Next, as shown in FIG. 4, CMP polishing is performed to form a barrier metal 5 on the first wiring-corresponding interlayer insulating film 3.
And a first wiring layer 7 made of a metal film 6 is formed.

Next, as shown in FIG.
A connection hole stopper film 8 made of a silicon nitride film of about 2000 Å is formed. This is to be an etching stopper when a connection hole is formed later. Further, after forming a wiring interlayer insulating film 9 made of a silicon oxide film of about 0.5 to 2 μm, a silicon nitride film of about 500 to 2000 Å is formed. (2) a second wiring stopper film 10, a second wiring corresponding interlayer insulating film 1 made of a silicon oxide film having a thickness of about 0.1 to 2 μm corresponding to a second wiring layer;
1 are sequentially formed. At this time, without forming the second wiring stopper film 10, the second wiring stopper film 10
The wiring corresponding interlayer insulating film 11 may be formed. Next, FIG.
As shown in FIG. 7, a resist pattern 12 for a connection hole is formed on the second wiring-corresponding interlayer insulating film 11.

Next, as shown in FIG. 7, holes 1 for connection holes are formed on the first wiring layer 7 using the resist pattern 12 as a mask.
3 is formed. This is because the connection hole stopper film 8 is used as an etching stopper, and
Etching is performed so as to penetrate the second wiring stopper film 10 and the wiring interlayer insulating film 9. For this etching, for example, using an ECR type dry etching apparatus, C ₄ F ₈ /
First, in the gas O _2, the second wiring corresponding interlayer insulating film 11 is etched, followed by CF ₄ / O ₂ gas and the second wiring stopper film 10 is etched, further gas C ₄ F ₈ / O ₂ Then, the wiring interlayer insulating film 9 is etched. After that, the resist pattern 12 is removed to complete the hole 13 for the connection hole.

Next, as shown in FIG. 8, an organic coating film 20 such as a resist is coated on the entire surface by a spin coating method with a sufficient thickness. At this time, the organic coating film 20 is connected to the connection hole 13.
The organic coating film 20 is applied not only on the inside but also on the second wiring-corresponding interlayer insulating film 11, and the thickness of the organic coating film 20 formed by the spin coating method varies.

Next, as shown in FIG. 9, the organic coating film 20 is removed by a method such as etch back on the entire surface, and the organic coating film 20 is left only in the holes 13 for connection holes. At this time, ideally, the surface of the organic coating film 20 is
Although it is the same surface as one surface, it is necessary to set the entire etch back to be over-etching in order to completely remove the organic coating film 20 outside the connection hole 13. At this time, the surface of the organic coating film 20 after the entire surface is etched back may be formed to be recessed from the surface of the second wiring-corresponding interlayer insulating film 11, but the second wiring stopper film 10, that is, the second wiring-corresponding interlayer insulating film may be formed. The film 11 is controlled so as not to be formed below the lower surface. Connection hole stopper film 8
The second wiring stopper film 10 is covered with the organic coating film 20 and is not exposed.

Next, as shown in FIG. 10, an antireflection film 21 is formed on the entire surface to a thickness of about 500 to 1000 angstroms. This antireflection film 21 is an organic ARC which is a coating film.
A film, a SiN film formed by sputtering or CVD, or the like. At this time, halation from the first wiring layer 7 can be prevented by the anti-reflection film 21, and the anti-reflection film 21 is further superimposed on the organic coating film 20.
Is formed, the filling in the hole 13 for the connection hole can be sufficiently performed. When the anti-reflection film 21 is an organic ARC film as a coating film, it is formed by a spin coating method. However, since the anti-reflection film 21 is thinner than the organic coating film 20, the variation in the film thickness can be ignored. It is about.

Next, as shown in FIG. 11, using the resist pattern 14 as a mask and the second wiring stopper film 10 as an etching stopper, the second wiring-corresponding interlayer insulating film 11 is used.
Is etched to form a groove 15 for the second wiring layer.
If the second wiring stopper film 10 is not formed, the second wiring-corresponding interlayer insulating film 11 is controlled by controlling the etching time.
Is etched. With this configuration, the exposed surfaces of the connection hole stopper film 8 and the second wiring stopper film 10 are
At the time of forming the groove 15 for the wiring layer, direct attack by the etching gas can be prevented.
Therefore, the first wiring layer 7 is not exposed, and a part of the second wiring stopper film 10 disappears, so that the shape of the connection hole 13 does not change, and the resistance value of the connection hole varies. There is no.

Next, as shown in FIG. 12, the organic coating film 20 in the connection hole 13 is removed together with the resist pattern 14, and the connection hole exposed at the bottom of the connection hole 13 is removed. The stopper film 8 is removed to remove the groove 1 for the second wiring layer.
5 and holes 13 for connection holes are formed.

Next, as shown in FIG. 13, the entire surface including the groove 15 for the second wiring layer and the hole 13 for the connection hole is covered with TaN.
A barrier metal 16 such as TiN or TiN and a metal film 17 such as Cu are formed. Finally, as shown in FIG.
P polishing is performed to form a barrier metal 16 such as TaN or TiN on the second wiring interlayer insulating film 11 and the wiring interlayer insulating film 9.
Then, a second wiring layer 18 made of a metal film 17 such as Cu and a connection hole 22 are formed.

In this way, halation from the first wiring layer 7 can be prevented by the antireflection film 21. When forming the groove 15 for the second wiring layer, the connection hole stopper film 8 and the second wiring stopper film 10 are covered with the organic coating film 20 and are directly attacked by the etching gas without being exposed. There is no. Furthermore, while being able to be sufficiently embedded in the hole 13 for the connection hole,
Since the organic coating film 20 outside the holes 13 for the connection holes is completely removed, it is possible to suppress a variation in the film thickness from the base when the resist pattern 14 is formed, and to provide a groove for the second wiring layer. Etching for the formation of No. 15 can be performed well, and a good Cu wiring can be formed with good reproducibility. Further, when the second wiring stopper film 10 is not formed, the process is simplified and the capacitance between the wiring layers can be reduced.

Embodiment 2 15 to 18 are sectional views showing steps of a method for forming a Cu wiring by a dual damascene process according to the second embodiment of the present invention. The description will be made sequentially according to the drawings. First, after performing the steps up to the opening of the connection hole 13 in the same manner as in FIGS. 1 to 7 of the first embodiment,
As shown in FIG. 15, an organic coating film 20 such as a resist is buried in the connection hole 13 by a spin coating method. At this time, the organic coating film 20 is applied not only in the hole 13 for the connection hole but also on the interlayer insulating film 11 corresponding to the second wiring.

Next, as shown in FIG. 16, the organic coating film 20 is removed by a method such as etch back on the entire surface. The organic coating film 20 is left in the hole 13 for the connection hole and the second wiring The organic coating film 20 is also left thinly on the interlayer insulating film 11. Next, as shown in FIG. 17, an antireflection film 21 is formed on the entire surface. The antireflection film 21 is an organic ARC film as a coating film, a SiN film or a TiN film formed by sputtering or CVD. At this time,
Since the anti-reflection film 21 is further formed on the organic coating film 20, it is possible to sufficiently embed the hole 13 for the connection hole, so that the halation from the first wiring layer 7 is reduced by the anti-reflection film. 21 prevents this. The connection hole stopper film 8 and the second wiring stopper film 10 are covered with the organic coating film 20.

Next, as shown in FIG. 18, using the resist pattern 14 as a mask and the second wiring stopper film 10 as an etching stopper, the second wiring corresponding interlayer insulating film 11 is used.
Is etched to form a groove 15 for the second wiring layer.
At this time, since the connection hole stopper film 8 and the second wiring stopper film 10 are covered with the organic coating film 20,
It is not exposed during etching and is not directly attacked by the etching gas. When the second wiring stopper film 10 is not formed, the second wiring-corresponding interlayer insulating film 11 is etched by controlling the etching time.

Thereafter, the organic coating film 20 inside and outside the connection hole 13 is removed together with the resist pattern 14 in the same manner as in FIG. 12 of the first embodiment. The exposed connection hole stopper film 8 is removed to form a groove 15 for the second wiring layer and a hole 13 for the connection hole.

Next, similarly to FIG. 13 of the first embodiment, a barrier metal 16 such as TaN or TiN and a barrier metal 16 such as Cu are formed on the entire surface including the groove 15 for the second wiring layer and the hole 13 for the connection hole. A metal film 17 is formed. Next, in the same manner as in FIG. 14 of the first embodiment, CMP polishing is performed to form a barrier metal 16 such as TaN or TiN and a metal film 17 such as Cu on the second interlayer insulating film 11 and the wiring interlayer insulating film 9. The second wiring layer 18 and the connection hole 22 are formed.

As described above, the embedding into the connection hole 13 can be sufficiently performed, and the organic coating film 20 after the entire surface is etched back can be formed flat without receding on the connection hole 13. The antireflection film 21 can also be formed flat, and in etching for forming the groove 15 for the second wiring layer, halation from the first wiring layer 7 can be completely prevented, and the reproducibility can be improved. A good Cu wiring can be formed.

Embodiment 3 FIG. Embodiments 1 and 2 above
In the above, the case where the wiring groove is formed after the formation of the connection hole has been described. Here, the case where the connection hole and the wiring groove are formed simultaneously will be described. FIGS. 19 to 21 show Cu according to the dual damascene process according to the third embodiment of the present invention.
FIG. 4 is a process cross-sectional view illustrating a method of forming a wiring. The description will be made sequentially according to the drawings.

First, the steps up to the formation of the resist pattern 12 for the connection hole on the second wiring interlayer insulating film 11 are performed in the same manner as in FIGS. 1 to 6 of the first embodiment, and then as shown in FIG. Then, using the resist pattern 12 as a mask, the second wiring-corresponding interlayer insulating film 11 and the second wiring stopper film 10 on the first wiring layer 7 are etched to form the upper portion 1 of the hole for the connection hole.
3a is formed.

Next, as shown in FIG. 20, an antireflection film 21 is formed on the entire surface to a thickness of about 500 to 1000 angstroms. This antireflection film 21 is an organic ARC which is a coating film.
A film, a SiN film formed by sputtering or CVD, or the like. Halation from the first wiring layer 7 can be prevented by the antireflection film 21.

Next, as shown in FIG. 21, using the resist pattern 14 as a mask and the second wiring stopper film 10 as an etching stopper, the second wiring-corresponding interlayer insulating film 11 is used.
To form a groove 15 for the second wiring layer and to etch the wiring interlayer insulating film 9 using the pattern of the second wiring-corresponding interlayer insulating film 11 as a mask to form a lower portion 13b of a hole for a connection hole. .

Thereafter, in the same manner as in FIG. 12 of the first embodiment, the resist pattern 14 is removed, and the connection hole stopper film 8 exposed at the bottom of the lower portion 13b of the connection hole is removed. Thus, a groove 15 for the second wiring layer and a hole 13 for the connection hole are formed.

Next, similarly to FIG. 13 of the first embodiment, a barrier metal 16 such as TaN or TiN and a barrier metal 16 such as Cu are formed on the entire surface including the groove 15 for the second wiring layer and the hole 13 for the connection hole. A metal film 17 is formed. Next, in the same manner as in FIG. 14 of the first embodiment, CMP polishing is performed to form a barrier metal 16 such as TaN or TiN and a metal film 17 such as Cu on the second interlayer insulating film 11 and the wiring interlayer insulating film 9. The second wiring layer 18 and the connection hole 22 are formed.

This is because when the second wiring-corresponding interlayer insulating film 11 and the wiring interlayer insulating film 9 have to be formed thickly, the aspect ratio can be reduced in each etching, and a good hole 13 for a connection hole can be obtained. , And a good Cu wiring can be formed with good reproducibility.

[0042]

As described above, according to the present invention, a connection hole stopper film, a wiring interlayer insulating film, and a second wiring corresponding interlayer insulating film are formed on a first wiring corresponding interlayer insulating film including a first wiring layer. Are sequentially stacked, and the second wiring-corresponding interlayer insulating film and the wiring interlayer insulating film are sequentially etched using the connection hole stopper film as an etching stopper using the connection hole resist pattern as a mask. Forming an organic coating film on the entire surface including the connection hole and the second wiring-corresponding interlayer insulating film; and performing a full-etchback on the organic coating film. Forming an anti-reflection film on the entire surface, and etching the second wiring-corresponding interlayer insulating film using the resist pattern for the second wiring layer as a mask, thereby forming the second wiring Forming a groove for the second wiring layer, removing the resist pattern and the organic coating film for the second wiring layer, removing the connection hole stopper film, and removing the connection hole hole and the second hole. Forming a connection hole and a second wiring layer by embedding a barrier metal and a metal film in a groove for the wiring layer. Halation can be prevented, and the antireflection film is formed on the organic coating film so that the hole can be sufficiently embedded in the connection hole, and the etching for forming the groove for the second wiring layer can be performed. , And a good Cu wiring can be formed with good reproducibility.

In the step of etching back the entire surface of the organic coating film, the organic coating film on the second wiring interlayer insulating film is completely removed, so that the organic coating film is formed only in the connection hole. Since the resist pattern is left, it is possible to suppress variations in the film thickness from the base when the resist pattern is formed.

In the step of etching back the entire surface of the organic coating film, the thin film of the organic coating film is left on the interlayer insulating film corresponding to the second wiring, so that the antireflection film can be formed flat. Halation can be completely prevented in the etching for forming the groove for the second wiring layer.

Since the upper surface of the organic coating film in the connection hole is located above the lower surface of the second wiring interlayer insulating film, the shape of the connection hole can be formed stably. Also, there is no variation in the resistance value of the connection hole.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, the contact hole stopper film, the wiring interlayer insulating film, and the second wiring stopper are formed on the first wiring corresponding interlayer insulating film including the first wiring layer. A step of sequentially laminating a film and a second wiring-corresponding interlayer insulating film, and etching the second wiring-corresponding interlayer insulating film and the second wiring stopper film by using a resist pattern for a connection hole as a mask to form the connection. Forming an upper portion of the hole for the hole, forming an antireflection film on the entire surface including the upper portion of the hole for the connection hole and the second wiring-corresponding interlayer insulating film, and forming a second wiring The second wiring layer is etched by etching the antireflection film and the second wiring-corresponding interlayer insulating film using the second wiring stopper film as an etching stopper using the resist pattern for the layer as a mask. At the same time as forming the groove, the lower part of the connection hole is formed by etching the wiring interlayer insulating film from the bottom of the upper part of the connection hole using the connection hole stopper film as an etching stopper. A step of removing the resist pattern for the second wiring layer; a step of removing the connection hole stopper film; and a step of removing a lower portion of the hole for the connection hole and a groove for the second wiring layer. Forming a connection hole and a second wiring layer by burying a metal and a metal film, so that the second wiring-corresponding interlayer insulating film and the wiring interlayer insulating film must be formed thick. In each etching, the aspect ratio can be reduced, a good hole for a connection hole can be formed, and the first layer can be formed by forming an anti-reflection film. It is possible to prevent halation from a line layer, since the second wiring stopper film is not exposed, it is possible to perform the etching for forming the trench for the second wiring layer satisfactorily, with good reproducibility,
Good Cu wiring can be formed.

[Brief description of the drawings]

FIG. 1 is a one-step cross-sectional view showing a method for forming a Cu wiring by a dual damascene process according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 3 is a one-step cross-sectional view showing a method for forming a Cu wiring by a dual damascene process according to the first embodiment of the present invention;

FIG. 4 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 9 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 10 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 11 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 12 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 13 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 14 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the first embodiment of the present invention;

FIG. 15 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the second embodiment of the present invention;

FIG. 16 is a one-step cross-sectional view showing a method for forming a Cu wiring by a dual damascene process according to the second embodiment of the present invention;

FIG. 17 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the second embodiment of the present invention;

FIG. 18 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the second embodiment of the present invention;

FIG. 19 is a cross-sectional view showing a step of the method for forming a Cu wiring by the dual damascene process according to the third embodiment of the present invention;

FIG. 20 is a one-step cross-sectional view showing a method for forming a Cu wiring by a dual damascene process according to Embodiment 3 of the present invention;

FIG. 21 is a process cross-sectional view showing a method for forming a Cu wiring by a dual damascene process according to the third embodiment of the present invention;

FIG. 22 shows C obtained by a conventional dual damascene process.
FIG. 6 is a cross-sectional view showing a step of a method for forming a u-wiring.

FIG. 23 shows C obtained by a conventional dual damascene process.
FIG. 6 is a cross-sectional view showing a step of a method for forming a u-wiring.

FIG. 24 is a diagram showing C by a conventional dual damascene process.
FIG. 6 is a cross-sectional view showing a step of a method for forming a u-wiring.

FIG. 25 shows a C obtained by a conventional dual damascene process.
FIG. 6 is a cross-sectional view showing a step of a method for forming a u-wiring.

FIG. 26 shows C obtained by a conventional dual damascene process.
It is a figure showing a problem of a formation method of u wiring.

FIG. 27 shows C by a conventional dual damascene process.
It is sectional drawing which shows the problem of the formation method of u wiring.

FIG. 28 shows C obtained by a conventional dual damascene process.
It is sectional drawing which shows the problem of the formation method of u wiring.

[Explanation of symbols]

REFERENCE SIGNS LIST 3 first wiring corresponding interlayer insulating film, 7 first wiring layer, 8 connection hole stopper film, 9 wiring interlayer insulating film, 10 second wiring stopper film, 11 second wiring corresponding interlayer insulating film, 12
Connection hole resist pattern, 13 Connection hole hole, 1
3a upper part of the hole for connection hole, 13b lower part of the hole for connection hole, 14 resist pattern for second wiring layer, 15
Groove for second wiring layer, 16 barrier metal, 17 metal film,
18 second wiring layer, 20 organic coating film, 21 antireflection film, 22 connection hole.

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Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device having a connection hole on a first wiring layer and a second wiring layer on the connection hole, wherein a first wiring corresponding to the first wiring layer is provided. A step of sequentially stacking a connection hole stopper film, a wiring interlayer insulation film, and a second wiring-corresponding interlayer insulation film on the interlayer insulation film; and forming the connection hole stopper film as an etching stopper using the connection hole resist pattern as a mask. Forming a hole for the connection hole by sequentially etching the second wiring-corresponding interlayer insulating film and the wiring interlayer insulating film; and forming the connection hole and the second wiring-corresponding interlayer insulating film. A step of forming an organic coating film on the entire surface, a step of performing etch back on the entire organic coating film, a step of forming an anti-reflection film on the entire surface, and using a resist pattern for the second wiring layer as a mask Forming a groove for the second wiring layer by etching the interlayer insulating film corresponding to the second wiring, removing the resist pattern and the organic coating film for the second wiring layer, Removing the connection hole stopper film, and forming the connection hole and the second wiring layer by embedding a barrier metal and a metal film in the hole for the connection hole and the groove for the second wiring layer; A method for manufacturing a semiconductor device, comprising: 2. In the step of performing etch back on the entire surface of the organic coating film, the organic coating film on the second wiring-corresponding interlayer insulating film is completely removed, so that the organic coating film is formed only in the connection hole. 2. The method according to claim 1, wherein the semiconductor device is left. 3. The method according to claim 1, wherein in the step of etching back the entire surface of the organic coating film, a thin film of the organic coating film is left on the second wiring corresponding interlayer insulating film.
13. The method for manufacturing a semiconductor device according to item 5. 4. The method according to claim 1, wherein the upper surface of the organic coating film in the hole for the connection hole when the entire surface of the organic coating film is etched back is located above the lower surface of the second wiring corresponding interlayer insulating film. Item 3. A method for manufacturing a semiconductor device according to Item 2. 5. A method for manufacturing a semiconductor device, wherein a connection hole is formed on a first wiring layer, and a second wiring layer is formed on the connection hole, wherein the first wiring including the first wiring layer is provided. A step of sequentially stacking a connection hole stopper film, a wiring interlayer insulation film, a second wiring stopper film, and a second wiring corresponding interlayer insulation film on the corresponding interlayer insulation film; Forming the upper step of the hole for the connection hole by etching the interlayer insulating film corresponding to the wiring and the second wiring stopper film, and the step of forming the upper step of the hole for the connection hole and the second wiring Forming an anti-reflection film on the entire surface including over the interlayer insulating film; and using the second wiring stopper film as an etching stopper with the resist pattern for the second wiring layer as a mask;
Forming the groove for the second wiring layer by etching the wiring-corresponding interlayer insulating film, and simultaneously using the connection hole stopper film as an etching stopper from the bottom of the upper step of the connection hole. Forming a lower step of the hole for the connection hole by etching, removing the resist pattern for the second wiring layer, and removing the connection hole stopper film;
Forming the connection hole and the second wiring layer by embedding a barrier metal and a metal film in a lower portion of the connection hole and a groove for the second wiring layer. Semiconductor device manufacturing method.