KR100896849B1 - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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Publication number
KR100896849B1
KR100896849B1 KR1020070137184A KR20070137184A KR100896849B1 KR 100896849 B1 KR100896849 B1 KR 100896849B1 KR 1020070137184 A KR1020070137184 A KR 1020070137184A KR 20070137184 A KR20070137184 A KR 20070137184A KR 100896849 B1 KR100896849 B1 KR 100896849B1
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KR
South Korea
Prior art keywords
gate
tungsten silicide
pattern
poly
gate oxide
Prior art date
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KR1020070137184A
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Korean (ko)
Inventor
박동훈
Original Assignee
주식회사 동부하이텍
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Priority to KR1020070137184A priority Critical patent/KR100896849B1/en
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Publication of KR100896849B1 publication Critical patent/KR100896849B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In the present invention, in the process of tungsten silicide (WSix), by selectively removing the HV gate oxide film by a predetermined depth, the step difference between the moat and the field, which are hardly present due to STI CMP in the existing process, A step is generated and the generated step can be used to clearly recognize the bottom mort key and the overlay key in the gate pattern which are not seen later due to the reflectivity of the tungsten silicide.

Tungsten silicide, gate oxide, gate pattern

Description

Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in the process of tungsten silicide (WSix), the lower moat alignment in the pattern equipment caused by the reflectivity of the tungsten silicide at the time of the gate electrode pattern progression (moat align) and an overlay key (overlay key).

As is well known, the gate electrode of the semiconductor device is formed of a structure in which a gate oxide film and a polysilicon are stacked, and as the device is highly integrated, the gate electrode is formed of a tungsten polyside structure in which a gate oxide film / polysilicon / tungsten silicide (WSi2) is stacked. Lose.

This is because the tungsten polyside structure can adjust the sheet resistance to several tens of ohms (Ω), which can be used to manufacture ultra-high density semiconductor devices. Next, a process of using tungsten silicide as a gate electrode in the related art will be described with reference to FIGS. 1A to 1D.

That is, referring to FIG. 1A, an example of a semiconductor substrate on which a moat 101 and a field 103 are formed, as shown in FIG. 1B, is a high voltage (HV) gate oxide film 105. ).

Next, in the state where the HV gate oxide film 105 is formed, after performing chemical mechanical polishing (CMP), which is a planarization process, the poly gate 107 is formed on a scribe line as shown in FIG. 1C, for example. And tungsten silicide 109 are sequentially formed.

Next, an anti-reflective coating (ARC) 111 is formed on the tungsten silicide 109 as shown in FIG. 1D, and then used as a hard mask on the formed ARC 111. Photo resist (PR) 113 to be formed is sequentially formed. Thereafter, a gate electrode pattern may be formed through a conventional semiconductor process.

However, due to the reflectivity of tungsten silicide 109 due to the sequential formation of poly gate 107 and tungsten silicide 109 in a scribe line as shown in FIG. 1C of the background art operating as described above. During the gate pattern process, a moat key, which is a photo alignment key in the scribe line, does not appear as shown in FIG. There is a problem that this is impossible.

Accordingly, the technical problem of the present invention is to solve the problems described above, in the process of tungsten silicide (WSix) process, in the pattern equipment caused by the reflectivity of the tungsten silicide in the lower portion during the progress of the gate electrode pattern The present invention provides a method of manufacturing a semiconductor device capable of recognizing a moat align and an overlay key.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate oxide film on a semiconductor substrate having a moat and a field, forming a poly gate on the formed gate oxide film, Selectively removing the formed poly gate to form a poly gate pattern on the gate oxide layer, and performing an etching process using the formed poly gate pattern as a mask to selectively remove the gate oxide layer to a predetermined depth. And forming gate poly and tungsten silicide, forming an anti-reflection film (ARC) on the formed tungsten silicide, and forming a gate electrode pattern on the formed ARC while the poly gate pattern is removed. do.

The predetermined depth is characterized by being in the range of 450 mW to 550 mW.

The etching process may be removed by a deglaze method.

The poly gate pattern is characterized in that a field region excluding the moat is open.

In the present invention, in the process of tungsten silicide (WSix), by selectively removing the HV gate oxide film by a predetermined depth, the step difference between the moat and the field, which are hardly present due to STI CMP in the existing process, A step is generated, and by using the generated step, there is an effect of clearly recognizing the bottom mort key and the overlay key in the gate pattern which are not visible due to the reflectivity of tungsten silicide.

Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

3A to 3F are vertical cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

That is, as shown in FIG. 3A, an HV gate oxide film 305 is formed on an example of a semiconductor substrate on which a moat 301 and a field 303 are formed, as shown in FIG. 3B.

Next, CMP, which is a planarization process, is performed in a state where the HV gate oxide film 305 is formed, and then, for example, a poly gate 307 is formed on a scribe line as shown in FIG. 3C.

Next, an exposure process using a reticle designed in an arbitrary pattern of interest and a development process are performed to selectively remove a part of the front-coated PR to remove the moat 301 on the poly gate 307. A PR pattern is formed to define the (field) 303 region to be open, an etching process (for example, a dry method) is performed using the formed PR pattern as a mask, and the poly gate 307 is selectively removed. For example, as illustrated in FIG. 3D, the poly gate pattern 309 is formed on the HV gate oxide layer 305, and a stripping process is performed to remove the remaining PR patterns.

Subsequently, a deglaze process, which is an etch pretreatment process, is performed using the formed poly gate pattern 309 as a mask to selectively remove the HV gate oxide layer 305 by a predetermined depth, for example, as illustrated in FIG. 3E. (311). In this case, the predetermined depth is preferably in the range of 450 mW to 550 mW. Here, the step of removing the HV gate oxide film 305 by a predetermined depth selectively removes the step difference between the moat and the field, which rarely exist due to the STI CMP in the conventional process, through the process of FIG. 3E. Then, the bottom mort key and the overlay key in the gate pattern, which were not visible due to the reflectivity of the tungsten silicide, are clearly visible.

Finally, as shown in FIG. 3F, the gate poly 313 and the tungsten silicide 315 are sequentially formed with the poly gate pattern 309 removed, and the ARC 317 is formed on the formed tungsten silicide 315. The gate electrode pattern 319 may be formed by performing an etching process on the formed ARC 315 using a PR pattern as a mask.

As described above, in the present invention, in the process of tungsten silicide (WSix), the step between the moat and the field, which are hardly present due to STI CMP in the existing process, is described using the HV gate oxide film 305. A step is generated by selectively removing the set depth, and the step is used to clearly recognize the bottom mort key and the overlay key in the gate pattern which are not visible due to the reflectivity of tungsten silicide.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

1a to 1d is a vertical cross-sectional view for each process for using tungsten silicide as a gate electrode in the prior art,

FIG. 2 is a view illustrating that a moat key, which is a photo align key in a scribe line, is not visible in a conventional gate pattern process; FIG.

3A to 3F are vertical cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

301: moat 303: field

305: HV gate oxide film 307: Poly gate

309: poly gate pattern 313: gate poly

315 tungsten silicide 317 ARC

319: gate electrode pattern

Claims (4)

Forming a gate oxide film on a semiconductor substrate having a moat and a field; Forming a poly gate on the formed gate oxide layer; Selectively removing the formed poly gate to form a poly gate pattern on the gate oxide layer; Selectively removing the gate oxide layer by a predetermined depth by performing an etching process using the formed poly gate pattern as a mask; Forming gate poly and tungsten silicide, forming an anti-reflection film (ARC) on the formed tungsten silicide, and forming a gate electrode pattern on the formed ARC while the poly gate pattern is removed. Method for manufacturing a semiconductor device comprising a. The method of claim 1, The predetermined depth is in the range of 450 to 550 GHz. The method of claim 1, The etching process is a method of manufacturing a semiconductor device, characterized in that the removal by the deglaze method. The method of claim 1, The poly gate pattern is a method for manufacturing a semiconductor device, characterized in that the field region except for the moat is open.
KR1020070137184A 2007-12-26 2007-12-26 Method for manufacturing of semiconductor device KR100896849B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09293727A (en) * 1996-04-26 1997-11-11 Nec Corp Manufacture of semiconductor device
KR20050073050A (en) * 2004-01-08 2005-07-13 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
KR20050122475A (en) * 2004-06-24 2005-12-29 주식회사 하이닉스반도체 Transistor with recess gate and forming method thereof
JP2006080355A (en) 2004-09-10 2006-03-23 Nec Electronics Corp Manufacturing method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09293727A (en) * 1996-04-26 1997-11-11 Nec Corp Manufacture of semiconductor device
KR20050073050A (en) * 2004-01-08 2005-07-13 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
KR20050122475A (en) * 2004-06-24 2005-12-29 주식회사 하이닉스반도체 Transistor with recess gate and forming method thereof
JP2006080355A (en) 2004-09-10 2006-03-23 Nec Electronics Corp Manufacturing method of semiconductor device

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