KR100456420B1 - Method of forming a copper wiring in a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, wherein a first photoresist pattern is formed on a semiconductor substrate on which a predetermined structure is formed, and then a first ashing process is performed on the surface of the first photoresist pattern. Forming a second photoresist pattern on the entire structure, and then performing a second ashing process to form a second silicon oxide film on the surface of the second photoresist pattern; Forming and polishing; and removing the first and second photoresist patterns, the first and second silicon oxide layers, and then forming an interlayer insulating layer over the entire structure, wherein the dielectric constant of the low dielectric interlayer insulating layer is formed. Changes can be prevented from changing the dielectric constant at the source to maintain process reproducibility and improve device reliability and yield. The copper wiring formation method of a semiconductor element is proposed.

Description

Method of forming a copper wiring in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device. In particular, a silicon oxide film is formed on a via hole photoresist pattern and a surface thereof, and a silicon oxide film is formed on a trench photoresist pattern and its surface, and a copper layer is embedded and polished. By removing the pattern and the silicon oxide film and forming a low dielectric insulating film, it is possible to prevent the change in dielectric constant at the source to maintain the reproducibility of the process, and to improve the reliability and yield of the device. will be.

Due to the high integration of semiconductor devices, parasitic capacitances between operating speeds, resistances, and metal wirings have become a problem, and copper wiring has been spotlighted as a next-generation device wiring process instead of conventional aluminum wiring. However, since copper is difficult to be etched by a general etching process, the copper wiring may be formed using a dual damascene process in which an interlayer insulating layer is formed, a via hole for forming a plug, a trench for forming a wiring, and a copper is embedded. Form.

In addition, in order to reduce the RC delay of the semiconductor device, a low dielectric material is used as the interlayer insulating film instead of the oxide film. However, these low dielectric materials have a low dielectric constant due to their high dielectric constant during an etching process, an ashing process, or a cleaning process. For this reason, the etching, ashing, and cleaning process of the interlayer insulating film is a continuous problem in the copper wiring process in which the low dielectric material is used as the interlayer insulating film and the damascene process is embedded in the copper wiring process. Much effort is being made.

An object of the present invention relates to a method for forming a copper wiring of a semiconductor device which can prevent the change of dielectric constant of the interlayer insulating film by forming a copper wiring without performing the etching, ashing and cleaning processes of the interlayer insulating film.

Another object of the present invention is to form a silicon oxide film on the photoresist pattern by an ashing process, and after filling the copper layer to form a low dielectric interlayer insulating film in the portion where the photoresist pattern and the silicon oxide film is removed, it is possible to prevent the dielectric constant change of the interlayer insulation film The present invention provides a method for forming a copper wiring of a semiconductor device that can improve the reliability and yield of the device.

1 (a) to 1 (d) are cross-sectional views of devices sequentially shown in order to explain a method for forming a copper wiring of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 semiconductor substrate 12 first photosensitive film

13: first silicon oxide film 14: second photosensitive film

15 second silicon oxide film 16 copper layer

17: interlayer insulation film

In the method for forming a copper wiring of a semiconductor device according to the present invention, after forming a first photoresist pattern on a semiconductor substrate having a predetermined structure, a first ashing process is performed to form a first silicon oxide film on the surface of the first photoresist pattern. And forming a second silicon oxide film on the surface of the second photoresist pattern by performing a second ashing process after forming a second photoresist pattern on the entire structure. And then removing the first and second photoresist patterns, the first and second silicon oxide layers, and then forming an interlayer insulating layer over the entire structure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.

1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method for forming a copper wiring of a semiconductor device according to the present invention.

Referring to FIG. 1A, the first photosensitive film 12 is coated on the semiconductor substrate 11 having a predetermined structure. The first photosensitive film 12 is patterned by performing an exposure and development process using a via hole mask. At this time, the first photosensitive film 12 is formed using a photosensitive material containing a silicon compound. The oxygen ashing process is performed to allow the silicon compound of the first photosensitive film 12 to react with the oxygen plasma so that the first silicon oxide film 13 is formed on the surface of the first photosensitive film 12. As described above, the first silicon oxide film 13 formed on the surface of the first photosensitive film 12 has characteristics similar to those of the oxide film formed by the CVD method or the like, and has resistance to mixing with the second photosensitive film to be applied thereafter.

In FIG. 1B, the second photosensitive layer 14 is coated on the entire structure, and then patterned by performing exposure and development processes using a trench mask. At this time, the second photosensitive film 14 is also formed using a photosensitive material containing a silicon compound similarly to the first photosensitive film 12. An oxygen ashing process is performed to allow the silicon compound of the second photosensitive film 14 to react with the oxygen plasma to form a second silicon oxide film 15 on the surface of the second photosensitive film 14. The second silicon oxide film 15 formed as described above has similar characteristics to the oxide film formed by the CVD method or the like as the first silicon oxide film 13, and is not damaged by an acidic copper solution when forming a copper layer by electroplating. It does not become a state. Thereafter, the copper layer 16 is formed to fill the via hole and the trench by electroplating, and then the CMP process is performed to planarize the copper layer 16.

Referring to FIG. 1C, the first photoresist film 12, the first silicon oxide film 13, the second photoresist film 14, and the second silicon oxide film 15 may be removed by a wet etching process, and the copper layer 16 may be removed. Is left.

Referring to FIG. 1D, a low dielectric insulating film is formed on the entire structure including the copper layer 16 by spin coating and then planarized to form an interlayer insulating film 17. As a result, a copper wiring is formed.

As described above, according to the present invention, since the etching process of the low dielectric insulating film is completely excluded, the change in dielectric constant generated during the etching process, the ashing process, or the cleaning process can be fundamentally prevented. As a result, an insulating film having a desired dielectric constant can be formed, so that the reproducibility of the process can be maintained, and the reliability and yield of the device can be improved.

Claims (7)

Forming a first photoresist pattern on the semiconductor substrate having a predetermined structure; Performing a first ashing process to form a first silicon oxide film on a surface of the first photoresist pattern; Forming a second photoresist pattern on the entire structure; Performing a second ashing process to form a second silicon oxide film on the surface of the second photoresist pattern; Forming a copper layer on the entire structure and then polishing it; And Removing the first and second photoresist patterns and the first and second silicon oxide layers; Forming an interlayer insulating film over the entire structure, and then planarizing the copper wiring. The method of claim 1, wherein the first photosensitive film pattern is formed of a photosensitive material including a silicon compound. The method of claim 1, wherein the first photoresist pattern is formed by an exposure and development process using a via hole mask. The method for forming a copper wiring of a semiconductor device according to claim 1, wherein the first ashing step is performed using oxygen. The method of claim 1, wherein the second photosensitive film pattern is formed of a photosensitive material containing a silicon compound. The method of claim 1, wherein the second photosensitive film pattern is formed by an exposure and development process using a trench mask. The method for forming a copper wiring of a semiconductor device according to claim 1, wherein said second ashing step is performed using oxygen.