KR19990005866A - Interlayer planarization method of semiconductor device - Google Patents

Interlayer planarization method of semiconductor device Download PDF

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KR19990005866A
KR19990005866A KR1019970030084A KR19970030084A KR19990005866A KR 19990005866 A KR19990005866 A KR 19990005866A KR 1019970030084 A KR1019970030084 A KR 1019970030084A KR 19970030084 A KR19970030084 A KR 19970030084A KR 19990005866 A KR19990005866 A KR 19990005866A
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layer
interlayer insulating
metal layer
etching
metal
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KR100246805B1 (en
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이정래
김수찬
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 층간 평탄화 공정에 관한 것임.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an interlayer planarization process of a semiconductor device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

반도체 소자의 층간 절연 평탄막으로 사용되는 SOG(Spin On Glass)막은 비아 콘택 홀(via contact hole) 측면의 휨(bowing) 현상, 상부 금속층의 스텝 커버리지(step coverage) 악화 및 수분 방출에 의한 소자의 전기적 특성 저하 등의 문제점 때문에 에치-백(etch-back)을 실시하는데, 소자의 고집적화에 따른 초미세 회로 선폭 공정에서는 에치-백 타겟이 매우 작아져 안정된 에치백 공정을 실시할 수 없음.A spin on glass (SOG) film, which is used as an interlayer insulating flat film of a semiconductor device, has a bowing phenomenon on a side of a via contact hole, a deterioration of step coverage of an upper metal layer, and a water discharge. Due to problems such as deterioration of electrical characteristics, etch-back is performed. In the ultra-fine circuit line width process due to the high integration of the device, the etch-back target is very small and a stable etch-back process cannot be performed.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

하부 구조층 상부에 금속층 및 층간절연막을 연속적으로 증착한 다음 층간절연막의 식각공정과 금속층의 패턴공정을 순차적으로 실시함으로써 SOG막의 에치-백 공정 여유를 충분히 확보하고 금속층 패턴 상부에 남는 SOG막을 완전히 제거할 수 있도록 함.By sequentially depositing a metal layer and an interlayer insulating film on the lower structure layer, the etching process of the interlayer insulating film and the patterning process of the metal layer are sequentially performed to secure sufficient margin for the etch-back process of the SOG film and to completely remove the SOG film remaining on the metal layer pattern. To do it.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 소자의 층간 평탄화 공정.Interlayer planarization process of semiconductor device.

Description

반도체 소자의 층간 평탄화 방법Interlayer planarization method of semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 층간 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for planarizing an interlayer of a semiconductor device.

SOG층은 SOG 용액을 노즐을 통해 웨이퍼에 분사하여, 회전에 의해 용액을 고르게 도포하고 경화 및 소성을 거쳐 얻는다. 이후 비아 콘택 홀을 형성하는데, 이 때 측벽에 노출된 SOG층은 플라즈마 식각을 거치면서 측벽 휨(bowing) 현상을 일으키고 이는 금속 층덮힘(step coverage)을 악화시키며, 노출된 SOG층에서 방출되는 수분에 의해 소자의 전기적 특성이 저하되는 원인을 제공한다. 따라서 SOG층을 형성한 후 에치백함으로써 이러한 결점들을 해결한다. 그런데, SOG층으로 부터 나오는 수분에 대해 침투 방지막으로 일반적으로 사용되고 있는 절연막 들은 금속 패턴 선폭이상의 두께를 증착하게 되면 막 특성상 돌출부 때문에 층덮힘이 불량하여 빈 공간(void)을 발생 시키기 때문에 패턴 선폭 이상으로 증착 할 수 없다.The SOG layer is obtained by spraying the SOG solution onto the wafer through a nozzle, applying the solution evenly by rotation, curing and firing. A via contact hole is then formed, where the SOG layer exposed to the sidewalls undergoes plasma etching, causing sidewall bowing, which exacerbates the step coverage, and the moisture released from the exposed SOG layer. This provides a cause for the deterioration of the electrical characteristics of the device. Therefore, these defects are solved by etching back after forming the SOG layer. However, the insulating films generally used as a penetration barrier against moisture from the SOG layer are more than the pattern line width because when the thickness of the metal pattern line width is deposited, the layer covering is poor due to the protruding portion, resulting in voids. Can not be deposited.

한편 SOG층 에치백의 공정 타겟(target)은 금속막이 노출되지 않는 범위에서 결정되며 주로 금속층막 바로 위에 증착되는 수분 침투 방지막의 두께 위까지 에치-백 되기 때문에 초미세 회로 선폭의 공정에서는 에치-백의 공정 타겟이 매우 작아지게 된다. 즉 수분 침투 방지막의 두께를 얇게 할 수 밖에 없어 안정된 에치백 공정을 할 수 없다. 특히 광역 단차(global topology)를 갖는 소자에서는 주변 회로 지역에서 SOG층이 많이 남게 되므로 에치-백의 공정 타겟이 더욱 커져야만 금속배선 위의 SOG층을 완전히 에치-백 할 수 있다. 따라서 기존의 방식대로는 광역 단차가 있는 미세 선폭의 소자에서 금속층에 손상을 주지 않고 주변 회로 지역에서 SOG층의 완전히 에치-백 하는 것이 불가능하다.On the other hand, the process target of the SOG layer etchback is determined within the range where the metal film is not exposed and is mainly etched back to the thickness of the moisture barrier film deposited directly on the metal layer film. The target is very small. In other words, the thickness of the moisture intrusion prevention film can only be reduced and a stable etch back process cannot be performed. In particular, in devices with a global topology, the SOG layer remains in the peripheral circuit area, so that the process target of the etch-back becomes larger so that the SOG layer on the metallization can be completely etched back. Therefore, in the conventional manner, it is impossible to completely etch back the SOG layer in the peripheral circuit area without damaging the metal layer in the device having the wide stepped fine line width.

따라서 본 발명은 반도체 소자의 층간 평탄막으로 사용되는 SOG층의 에치-백 공정 여유를 확보하여 금속 배선 상부에 남는 SOG층을 최소화 시키고 안정된 형태의 비아 콘택 홀을 형성하는데 그 목적이 있다.Accordingly, an object of the present invention is to minimize the SOG layer remaining on the upper portion of the metal wiring by securing an etch-back process margin of the SOG layer used as the interlayer planar film of the semiconductor device, and to form a stable via contact hole.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 층간 평탄화 방법은, 하부 구조층 상부에 금속층 및 제 1 층간 절연막을 순차로 증착하고, 포토레지스트 패턴을 이용하여 제 1 층간 절연막 및 금속층을 순차적으로 식각함으로써 금속 배선을 형성하는 단계와, 상기 금속 배선을 포함하는 전체 구조 상부에 수분 침투 방지층 및 SOG층을 순차로 증착한 후, 에치-백 공정을 실시하여 금속 배선 상부에 SOG층이 남아있지 않도록 식각함으로써 평탄화를 이루는 단계와, 상기 평탄화된 전체 구조 상부에 제 2 층간 절연막을 증착하고 선택된 영역에 비아 콘택 홀을 형성하는 단계로 이루어진 것을 특징으로 한다.In the interlayer planarization method of a semiconductor device according to the present invention for achieving the above object, the metal layer and the first interlayer insulating film are sequentially deposited on the lower structure layer, and the first interlayer insulating film and the metal layer are sequentially formed by using a photoresist pattern. Forming a metal wiring by etching, and sequentially depositing a moisture penetration preventing layer and an SOG layer on the entire structure including the metal wiring, and then performing an etch-back process so that the SOG layer remains on the metal wiring. Forming a second interlayer insulating film over the entire planarized structure and forming a via contact hole in a selected region.

도 1(a) 내지 도 1(g)는 본 발명에 의한 반도체 소자의 층간 평탄화 방법을 설명하기 위해 순차적으로 도시한 단면도.1 (a) to 1 (g) are cross-sectional views sequentially shown in order to explain the interlayer planarization method of a semiconductor device according to the present invention.

도 2는 본 발명에 의한 또다른 실시예를 설명하기 위해 도시한 단면도.Figure 2 is a cross-sectional view for explaining another embodiment according to the present invention.

도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of the drawings

11 및 21 : 실리콘 기판 12 및 22 : 하부 구조층11 and 21: silicon substrate 12 and 22: lower structure layer

13 및 23 : 금속층 14 및 24 : 제 1 층간 절연막13 and 23: metal layer 14 and 24: first interlayer insulating film

15 : 포토레지스트층 16 및 25 : 수분 침투 방지막15: photoresist layer 16 and 25: moisture penetration prevention film

17 및 26 : SOG(Spin On Glass)층 18 : 제 2 층간 절연막17 and 26: SOG (Spin On Glass) layer 18: second interlayer insulating film

27 : SOP(Spin On Polymer)층27: SOP (Spin On Polymer) Layer

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 1(a) 내지 도 1(g)는 본 발명에 의한 반도체 소자의 층간 평탄화 방법을 설명하기 위해 순차적으로 도시한 단면도이다.1 (a) to 1 (g) are cross-sectional views sequentially shown in order to explain the interlayer planarization method of a semiconductor device according to the present invention.

도 1(a)는 실리콘 기판(11)상의 하부 구조층(12) 상부에 금속층(13) 및 제 1 층간 절연막(14)을 순차로 증착한 후, 금속층(13)의 패턴을 형성하기 위하여 선택된 영역에 포토레지스트층(15)을 형성한 단면도이다. 이 때 제 1 층간 절연막(14)은 SOG층의 최대 잔류 두께인 1,000 Å ∼ 10,000 Å 정도로 증착하고, 포토레지스트층(15)은 0.5 ㎛ ∼ 2.0 ㎛의 두께로 증착하여 패턴을 형성한다.FIG. 1A is selected to form a pattern of the metal layer 13 after sequentially depositing the metal layer 13 and the first interlayer insulating layer 14 on the lower structure layer 12 on the silicon substrate 11. It is sectional drawing in which the photoresist layer 15 was formed in the area | region. At this time, the first interlayer insulating film 14 is deposited at a thickness of 1,000 GPa to 10,000 GPa, which is the maximum remaining thickness of the SOG layer, and the photoresist layer 15 is deposited to a thickness of 0.5 µm to 2.0 µm to form a pattern.

포토레지스트 패턴(15)에 의하여 먼저 제 1 층간 절연막(14)을 식각한다. 이 때 사용하는 식각 기체는 탄소(C)-불소(F)계 가스로 CF4, C2F6, CHF3, C3F8, C4F8등을 이용한다. 이 과정에서 도 1(b)에 도시된 것과 같이, 적절한 두께로 조절하여 증착된 포토레지스트층(15)도 일부 식각되면서 점차적으로 작아진다.The first interlayer insulating layer 14 is first etched by the photoresist pattern 15. In this case, as the etching gas, CF 4 , C 2 F 6 , CHF 3 , C 3 F 8 , C 4 F 8, and the like are used as the carbon (C) -fluorine (F) -based gas. In this process, as shown in FIG.

도 1(c)는 제 1 층간 절연막(14) 식각 후, 금속 배선을 형성하기 위해 금속층(13)을 식각하는 공정을 나타낸다. 금속층(13)의 식각이 진행되면서, 제 1 층간 절연막(14) 식각시 같이 식각되어 일부 작은 크기로 남아있던 포토레지스트 패턴(15)이 모두 식각되어 없어지게 된다.FIG. 1C illustrates a process of etching the metal layer 13 after etching the first interlayer insulating layer 14 to form metal wires. As the metal layer 13 is etched, all of the photoresist patterns 15, which are etched as the first interlayer insulating layer 14 is etched and remain in a small size, are etched away.

따라서 도 1(d)에 도시된 것과 같이 금속층(13) 식각 공정이 완전히 끝나고 나면, 포토레지스트층(15)은 완전히 제거되고, 제 1 층간 절연막(14) 패턴의 모서리 부분도 일부 식각된다. 위와 같이 제 1 층간 절연막(14) 패턴의 윗 모서리가 없어지게 함으로써, 고집적 소자의 높고 좁은 배선 간격에 대해서도 상부 형성층의 층덮힘 및 골 채움(gap-fill)을 유리하게 진행시킬 수 있다. 한편 제 1 층간 절연막(14) 및 금속층(13)의 식각은 같은 챔버 내에서 순차적으로 실시할 수도 있고, 다른 챔버에서 각 증착 층에 대해 분리하여 실시할 수도 있는 공정 적용상의 장점을 가지고 있다. 일반적으로 알루미늄(Al)을 금속층(13)으로 형성했을 경우 금속층(13)의 식각 기체는 Cl2와 같은 염소(Cl)계 가스를 사용하고, 텅스텐(W)을 금속층(13)으로 형성했을 경우는 금속층(13)의 식각 기체로 SF2와 같은 황(S)-불소(F)계 가스를 사용한다.Accordingly, after the etching process of the metal layer 13 is completely completed, as shown in FIG. 1D, the photoresist layer 15 is completely removed, and the edge portion of the first interlayer insulating layer 14 pattern is partially etched. By eliminating the upper edge of the first interlayer insulating film 14 as described above, it is possible to advantageously advance the layer covering and gap-fill of the upper formation layer even for the high and narrow wiring spacing of the highly integrated device. Meanwhile, the etching of the first interlayer insulating layer 14 and the metal layer 13 may be sequentially performed in the same chamber, or may be performed separately for each deposition layer in another chamber. In general, when aluminum (Al) is formed of the metal layer 13, the etching gas of the metal layer 13 uses chlorine (Cl) -based gas such as Cl 2 and when tungsten (W) is formed of the metal layer 13 The sulfur (S) -fluorine (F) -based gas such as SF 2 is used as an etching gas of the metal layer 13.

도 1(e)는 형성된 패턴을 포함하는 전체 구조 상부에 수분 침투 방지막(16) 및 SOG층(17)을 증착한 단면도이다. SOG층(17)은 1.1 ∼ 4.0의 유전상수 값을 가지는 유기계, 무기계 및 속이 빈 실리카(silica) 알맹이를 사용하여 순간 고속 회전 증착법 및 저온 증착법으로 증착한다.FIG. 1E is a cross-sectional view of depositing a moisture barrier film 16 and an SOG layer 17 on the entire structure including the formed pattern. The SOG layer 17 is deposited by using an instantaneous high speed rotary deposition method and a low temperature deposition method using organic, inorganic and hollow silica particles having dielectric constant values of 1.1 to 4.0.

SOG층(17) 형성 후 도 1(f)에 도시된 것과 같이 SOG층(17)을 에치-백 하여 금속층(13) 상부에 SOG층(17)이 남아있지 않도록 함으로써 소자의 광역 및 국부적 평탄화를 이루게 한다. SOG층(17)의 에치-백 공정에 사용되는 식각 기체는 제 1 층간 절연막(14) 식각시 사용한 것과 같은 탄소(C)-불소(F)계 가스로 CF4, C2F6, CHF3, C3F8, C4F8등을 이용하고, 수분 침투 방지층(16) 및 제 1 층간절연막(14)과 SOG층(17)의 식각 선택비를 0.3 ∼ 2.0 : 1로 제어한다.After the SOG layer 17 is formed, as shown in FIG. 1 (f), the SOG layer 17 is etched back so that the SOG layer 17 does not remain on the metal layer 13 so that the device has a wide area and local planarization. To achieve. The etching gas used for the etch-back process of the SOG layer 17 is the same carbon (C) -fluorine (F) -based gas used for etching the first interlayer insulating film 14, and CF 4 , C 2 F 6 , CHF 3 , C 3 F 8 , C 4 F 8 and the like are used to control the etching selectivity of the moisture penetration prevention layer 16, the first interlayer insulating film 14, and the SOG layer 17 to 0.3 to 2.0: 1.

SOG층(17)의 에치-백 공정으로 금속층(13) 패턴의 홈 사이에만 SOG층이 채워져 평탄화가 이루어진 전체 구조 상부에 도 1(g)와 같이 제 2 층간 절연막(18)을 증착하고 선택된 영역에 비아 콘택 홀을 형성한다. 따라서 광역 단차의 주변회로 지역에 높게 존재하는 SOG층(17)을 완전히 에치-백할 수 있는 공정 여유의 확보로 비아 콘택 홀을 형성하였을 때 홀의 측벽에 제 2 층간 절연막(18)만이 존재하게 되어 SOG층(17)이 측벽에 노출되었을 때 유발되는 휨현상 등의 문제가 해결된다.The second interlayer insulating film 18 is deposited on the entire structure where the SOG layer is filled only between the grooves of the metal layer 13 pattern by the etch-back process of the SOG layer 17, as shown in FIG. Form a via contact hole in the. Therefore, when the via contact hole is formed to secure a process allowance to completely etch back the SOG layer 17 that exists in the peripheral circuit area of the wide step, only the second interlayer insulating film 18 is present on the sidewall of the hole. Problems such as warpage caused when the layer 17 is exposed to the sidewalls are solved.

한편 도 2는 본 발명에 의한 또다른 실시예를 설명하기 위해 도시한 단면도로써, 도 1(e)의 공정 후 SOG층(26)을 에치-백 하여 평탄화를 이루는 대신에 희생 산화막 역할을 하는 SOP(Spin On Polymer)층(27)을 증착하고 화학적기계연마 공정을 실시하여 도 1(f)와 같은 평탄화를 이루게 한다.Meanwhile, FIG. 2 is a cross-sectional view illustrating another embodiment of the present invention, and the SOP acts as a sacrificial oxide instead of etch-backing the SOG layer 26 after the process of FIG. (Spin On Polymer) layer 27 is deposited and chemical mechanical polishing is performed to achieve planarization as shown in FIG. 1 (f).

상술한 바와 같이 본 발명에 의하면, 금속 층간 절연막 뿐만 아니라 보호막에도 같은 내용의 공정을 적용함으로써 SOG층을 패턴의 홈에만 채워진 상태로 고립시켜 수분 침투 경로를 차단하고, 따라서 PCT(Pressured Cooking Test)후의 버블(bubble) 형태의 결함을 방지할 수 있다. 또한 광역 단차가 심한 소자에서 본 공정을 적용하고, 광역 단차 평탄화용으로 SOP층을 희생막으로 사용함으로써 SOG막의 에치-백 공정을 대용할 수 있다.As described above, according to the present invention, by applying the same process to not only the metal interlayer insulating film but also the protective film, the SOG layer is isolated in a state filled only in the groove of the pattern to block the moisture penetration path, and thus after the Pressed Cooking Test (PCT) Bubble defects can be prevented. In addition, by applying the present process to a device having a large stepped area and using a SOP layer as a sacrificial film for planarization of the stepped step, the etch-back process of the SOG film can be substituted.

Claims (18)

기판 상부에 금속층 및 제 1 층간 절연막을 순차로 증착하고, 감광막 패턴을 이용하여 제 1 층간 절연막 및 금속층을 순차적으로 식각함으로써 금속 패턴을 형성하는 단계와,Forming a metal pattern by sequentially depositing a metal layer and a first interlayer insulating layer on the substrate, and sequentially etching the first interlayer insulating layer and the metal layer using a photosensitive film pattern; 상기 금속 패턴을 포함하는 전체 구조 상부에 수분 침투 방지층 및 스핀-온-글래스층을 순차로 증착한 후, 에치-백 공정을 실시하여 금속 배선 상부에 스핀-온-글래스층이 남아있지 않도록 식각함으로써 평탄화를 이루는 단계와,By sequentially depositing a moisture intrusion prevention layer and a spin-on-glass layer on the entire structure including the metal pattern, by performing an etch-back process to etch so that the spin-on-glass layer does not remain on the metal wiring Flattening, 상기 평탄화된 전체 구조 상부에 제 2 층간 절연막을 증착하고 선택된 영역에 금속층이 노출되도록 비아 콘택 홀을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.Depositing a second interlayer insulating film over the entire planarized structure and forming a via contact hole to expose a metal layer in a selected region. 제 1항에 있어서, 상기 제 1 층간 절연막은 1,000 Å 내지 10,000 Å의 두께로 증착하는 것을 특징으로하는 반도체 소자의 층간 평탄화 방법.The method of claim 1, wherein the first interlayer insulating film is deposited to a thickness of 1,000 GPa to 10,000 GPa. 제 1항에 있어서, 상기 포토레지스트 패턴은 0.5 ㎛ 내지 3.0 ㎛의 두께로 증착하는 것을 특징으로하는 반도체 소자의 층간 평탄화 방법.The method of claim 1, wherein the photoresist pattern is deposited to a thickness of 0.5 μm to 3.0 μm. 제 1항에 있어서, 상기 제 1 층간 절연막의 식각 또는 스핀-온-글래스층의 에치-백 공정은 CF4, C2F6, CHF3, C3F8, C4F8등과 같은 탄소-불소계 가스를 식각 기체로 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 1, wherein the etching of the first interlayer insulating layer or the etch-back process of the spin-on-glass layer is performed using a carbon-based material such as CF 4 , C 2 F 6 , CHF 3 , C 3 F 8 , C 4 F 8, and the like. An interlayer planarization method of a semiconductor device comprising using a fluorine-based gas as an etching gas. 제 1항에 있어서, 상기 SOG층은 1.1 내지 4.0의 유전 상수값을 가지는 유기계, 무기계 및 속이 빈 실리카 알맹이를 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 1, wherein the SOG layer uses organic, inorganic, and hollow silica kernels having dielectric constant values of 1.1 to 4.0. 제 1항에 있어서, 에치-백 공정시 상기 수분 침투 방지층 및 상기 제 1 층간 절연막과 SOG층의 식각 선택비를 0.3 대 1 내지 2.0 대 1로 제어하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 1, wherein an etch selectivity of the moisture barrier layer, the first interlayer insulating layer, and the SOG layer is controlled to be 0.3 to 1 to 2.0 to 1 during an etch-back process. 제 1항에 있어서, 상기 금속층은 알루미늄 및 텅스텐중 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 1, wherein the metal layer uses any one of aluminum and tungsten. 제 7항에 있어서, 상기 금속층이 알루미늄일 때 식각 공정에서 식각 기체로 염소계 가스를 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 7, wherein a chlorine-based gas is used as an etching gas in an etching process when the metal layer is aluminum. 제 7항에 있어서, 상기 금속층이 텅스텐일 때 식각 공정에서 식각 기체로 황-불소계 가스를 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 7, wherein a sulfur-fluorine-based gas is used as an etching gas in an etching process when the metal layer is tungsten. 하부 구조층 상부에 금속층 및 제 1 층간 절연막을 순차로 증착하고, 감광막 패턴을 이용하여 제 1 층간 절연막 및 금속층을 순차적으로 식각함으로써 금속 패턴을 형성하는 단계와, 상기 금속 패턴을 포함하는 전체 구조 상부에 수분 침투 방지층 및 스핀-온-글래스층을 순차로 증착한 후, 희생 산화막을 증착하고 연마 공정을 실시하여 금속 패턴 상부에 스핀-온-글래스층이 남아있지 않도록 평탄화를 이루는 단계와, 상기 평탄화된 전체 구조 상부에 제 2 층간 절연막을 증착하고 선택된 영역에 금속층이 노출되도록 콘택 홀을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.Sequentially depositing a metal layer and a first interlayer insulating layer on the lower structure layer and sequentially etching the first interlayer insulating layer and the metal layer by using a photosensitive film pattern to form a metal pattern, and the upper part of the entire structure including the metal pattern Depositing a water permeation prevention layer and a spin-on-glass layer in order, and then depositing a sacrificial oxide film and performing a polishing process to planarize so that the spin-on-glass layer does not remain on the metal pattern; Depositing a second interlayer insulating film over the entire structure and forming a contact hole to expose a metal layer in a selected region. 제 10항에 있어서, 상기 제 1 층간 절연막은 1,000 Å 내지 10,000 Å의 두께로 증착하는 것을 특징으로하는 반도체 소자의 층간 평탄화 방법.The method of claim 10, wherein the first interlayer insulating film is deposited to a thickness of 1,000 GPa to 10,000 GPa. 제 10항에 있어서, 상기 포토레지스트 패턴은 0.5 ㎛ 내지 3.0 ㎛의 두께로 증착하는 것을 특징으로하는 반도체 소자의 층간 평탄화 방법.The method of claim 10, wherein the photoresist pattern is deposited to a thickness of 0.5 μm to 3.0 μm. 제 10항에 있어서, 상기 제 1 층간 절연막의 식각은 CF4, C2F6, CHF3, C3F8, C4F8등과 같은 탄소-불소계 가스를 식각 기체로 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 10, wherein the etching of the first interlayer insulating film is characterized in that using a carbon-fluorine-based gas such as CF 4 , C 2 F 6 , CHF 3 , C 3 F 8 , C 4 F 8, etc. as an etching gas Interlayer planarization method of semiconductor device. 제 10항에 있어서, 상기 SOG층은 1.1 내지 4.0의 유전 상수값을 가지는 유기계, 무기계 및 속이 빈 실리카 알맹이를 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 10, wherein the SOG layer uses organic, inorganic, and hollow silica kernels having dielectric constant values of 1.1 to 4.0. 제 10항에 있어서, 상기 금속층은 알루미늄 및 텅스텐중 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 10, wherein the metal layer uses any one of aluminum and tungsten. 제 10항에 있어서, 상기 희생산화막은 스핀-온-폴리머인 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 10, wherein the sacrificial oxide film is a spin-on-polymer. 제 15항에 있어서, 상기 금속층이 알루미늄일 때 식각 공정에서 식각 기체로 염소계 가스를 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 15, wherein a chlorine-based gas is used as an etching gas in an etching process when the metal layer is aluminum. 제 15항에 있어서, 상기 금속층이 텅스텐일 때 식각 공정에서 식각 기체로 황-불소계 가스를 사용하는 것을 특징으로 하는 반도체 소자의 층간 평탄화 방법.The method of claim 15, wherein a sulfur-fluorine-based gas is used as an etching gas in an etching process when the metal layer is tungsten.
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KR100467817B1 (en) * 2003-01-30 2005-01-25 동부아남반도체 주식회사 Method for preventing metal corrosion of semiconductor
KR100685618B1 (en) * 2000-12-09 2007-02-22 주식회사 하이닉스반도체 Methoe for fabricating of semiconductor device

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KR100453864B1 (en) * 2001-03-13 2004-10-26 산요덴키가부시키가이샤 Semiconductor device and manufacturing method thereof
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