KR20040001503A - Method for forming single damascene pattern in semiconductor device - Google Patents
Method for forming single damascene pattern in semiconductor device Download PDFInfo
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- KR20040001503A KR20040001503A KR1020020036721A KR20020036721A KR20040001503A KR 20040001503 A KR20040001503 A KR 20040001503A KR 1020020036721 A KR1020020036721 A KR 1020020036721A KR 20020036721 A KR20020036721 A KR 20020036721A KR 20040001503 A KR20040001503 A KR 20040001503A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000010949 copper Substances 0.000 claims abstract description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052802 copper Inorganic materials 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 21
- 239000011810 insulating material Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 238000004380 ashing Methods 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
본 발명은 반도체 소자의 싱글 다마신 패턴 형성방법에 관한 것으로, 보다 상세하게는 저유전상수 물질에 대한 식각공정을 배제하여 유전율 열화를 방지할 수 있는 반도체 소자의 싱글 다마신 패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a single damascene pattern of a semiconductor device, and more particularly, to a method of forming a single damascene pattern of a semiconductor device capable of preventing dielectric constant deterioration by eliminating an etching process for a low dielectric constant material.
최근 반도체 소자가 집적화되고 공정 기술력이 향상되면서 소자의 동작속도나 저항, 금속간의 기생용량 등의 특성을 개선시키기 위한 일환으로 기존의 알루미늄(Al) 배선 대신에 구리(Cu) 배선 공정이 제안되었다. 또한, 절연막으로 기존의 옥사이드(Oxide) 대신 저유전율(Low-k) 절연물질이 차세대 소자의 배선 공정으로 각광을 받고 있다.Recently, as semiconductor devices have been integrated and process technology has been improved, copper (Cu) wiring processes have been proposed in place of conventional aluminum (Al) wiring as part of improving characteristics of device operation speed, resistance, and parasitic capacitance between metals. In addition, a low dielectric constant (Low-k) insulating material instead of the oxide (Oxide) as the insulating film is in the spotlight as the wiring process of the next generation device.
하지만, 이러한 구리와 저유전율 절연물질을 이용한 배선 공정의 경우 구리(Cu)의 식각 특성이 매우 열악하다는 문제가 있다. 따라서, 기존의 공정 방식 대신 미합중국특허 제5,635,423호에 개시된 것과 같은 다마신(Damascene) 공정이 구리 배선에 적합한 공정으로 알려져 있다.However, in the wiring process using the copper and the low dielectric constant insulating material, there is a problem that the etching characteristics of copper (Cu) are very poor. Therefore, a damascene process such as that disclosed in US Pat. No. 5,635,423 is known as a suitable process for copper wiring instead of the conventional process method.
그러나, 종래 기술에 따른 반도체 소자의 싱글 다마신 패턴 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the single damascene pattern forming method of the semiconductor device according to the prior art has the following problems.
종래 기술에 있어서는, RC 시정수의 지연(Delay)을 줄이기 위해 기존의 층간절연막으로 사용되던 옥사이드(Oxide) 대신에 유전상수(k)가 낮은 저유전율(Low-k) 절연물질을 사용하게 되었다. 그렇지만, 저유전율 절연물질은 그 경도(Hardness)나 탄성률(Modulus)이 옥사이드의 경도나 탄성률보다 열악하다. 따라서, 저유전율 절연물질은 식각(Etching), 애싱(Ashing) 및 세정(Cleaning) 공정중에 유전율이 열화(k-value Degradation)되어 결국 절연특성의 상당 부분을 잃어버리게 되는 문제점이 있다.In the related art, a low dielectric constant (k) having a low dielectric constant (k) is used instead of oxide, which is used as a conventional interlayer insulating film, to reduce the delay of RC time constant. However, the low dielectric constant insulating material is poor in hardness and modulus of elasticity than oxide hardness and modulus. Accordingly, the low dielectric constant insulating material has a problem in that the dielectric constant is degraded during etching, ashing, and cleaning, resulting in a loss of a large part of the insulating property.
이에, 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 다마신 구조 형성을 위한 포토리소그래피 공정을 실리콘 함유 레지스트를 이용하여 수행함으로써 저유전율 절연물질에 대한 식각공정을 배제할 수 있는 반도체 소자의 싱글 다마신 패턴 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, an object of the present invention is to perform an etching process for a low dielectric insulating material by performing a photolithography process for forming a damascene structure using a silicon-containing resist. The present invention provides a method for forming a single damascene pattern of a semiconductor device capable of eliminating the problem.
도 1 내지 도 7은 본 발명에 따른 반도체 소자의 다마신 패턴 형성방법을 설명하기 위한 공정별 단면도.1 to 7 are cross-sectional views for each process for explaining a method for forming a damascene pattern of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100; 반도체 기판110; 실리콘 함유 레지스트 패턴100; Semiconductor substrate 110; Silicon-containing resist pattern
120; SiOX막130; 구리층120; SiO X film 130; Copper layer
130a; 구리배선140; 저유전 절연물질층130a; Copper wiring 140; Low dielectric insulation layer
140a; 층간절연막140a; Interlayer insulation film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 싱글 다마신 패턴 형성방법은, 반도체 기판상에 레지스트 패턴을 형성하는 단계; 상기 레지스트 패턴 표면에 SiOX막을 형성하는 단계; 상기 레지스트 패턴이 형성된 기판상에 전기도금으로 구리층을 형성하는 단계; 상기 레지스트 패턴이 노출되도록 상기 구리층을 화학기계적 연마하여 구리배선으로 형성하는 단계; 상기 레지스트 패턴을 제거하는 단계; 상기 구리배선이 형성된 기판상에 저유전 절연물질층을 형성하는 단계; 및 상기 저유전 절연물질층을 화학기계적 연마하여 층간절연막으로 형성하는 단계를 포함하는 것을 특징으로 한다.Method for forming a single damascene pattern of a semiconductor device according to the present invention for achieving the above object, forming a resist pattern on a semiconductor substrate; Forming a SiO X film on the resist pattern surface; Forming a copper layer on the substrate on which the resist pattern is formed by electroplating; Chemically polishing the copper layer to expose the resist pattern to form a copper wiring; Removing the resist pattern; Forming a low dielectric insulating material layer on the substrate on which the copper wiring is formed; And chemically mechanically polishing the low dielectric insulating material layer to form an interlayer insulating film.
본 발명에 의하면, 저유전율 물질에 대한 식각공정이 완전히 배제되기 때문에 식각, 애싱 및 세정공정중에서 발생할 수 있는 저유전율 절연물질의 유전율 열화(k-value Degradation)를 원천적으로 막을 수 있게 된다.According to the present invention, since the etching process for the low dielectric constant material is completely excluded, the dielectric constant deterioration (k-value degradation) of the low dielectric constant insulating material which can occur during the etching, ashing and cleaning processes can be prevented at the source.
이하, 본 발명에 따른 반도체 소자의 싱글 다마신 패턴 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a single damascene pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 7은 본 발명에 따른 반도체 소자의 다마신 패턴 형성방법을 설명하기 위한 공정별 단면도이다.1 to 7 are cross-sectional views illustrating processes for forming a damascene pattern of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 다마신 패턴 형성방법은, 도 1에 도시된 바와 같이, 실리콘(Si)과 같은 반도체 원소로 구성된 반도체 기판(100)상에 실리콘이 함유되어 있는 레지스트의 도포, 노광 및 현상공정 등을 통하여 일정한 형태의 레지스트 패턴(110)을 형성한다. 이때, 상기 레지스트 패턴(110)은 일련의 후속공정으로 형성될 싱글 다마신 패턴(Single Damascene Pattern)과 동일하게끔 형성한다.As shown in FIG. 1, the method for forming a damascene pattern of a semiconductor device according to the present invention includes coating, exposing and exposing a resist containing silicon on a semiconductor substrate 100 composed of a semiconductor element such as silicon (Si). A resist pattern 110 having a certain shape is formed through a developing process or the like. In this case, the resist pattern 110 is formed to be the same as a single damascene pattern to be formed in a series of subsequent processes.
이어서, 도 2에 도시된 바와 같이, 상기 레지스트 패턴(110) 표면상에 SiOX막(120)을 O2애싱(Aahing) 공정을 이용하여 형성한다. 상기 SiOX막(120)은 상기 레지스트 패턴(110)내의 실리콘과 O2플라즈마간의 반응에 의해 형성되는 것으로, 화학기상증착법(CVD)으로 증착된 산화막과 유사한 특성을 지니며, 후속하는 구리 전기도금(Cu Electroplating) 과정시 상기 레지스트 패턴(110)을 산성의 구리 용액(Cu Solution)의 어택(Attack)으로부터 보호한다.Subsequently, as shown in FIG. 2, a SiO X film 120 is formed on the surface of the resist pattern 110 using an O 2 ashing process. The SiO X film 120 is formed by the reaction between the silicon and the O 2 plasma in the resist pattern 110, has similar characteristics to the oxide film deposited by chemical vapor deposition (CVD), and subsequent copper electroplating. During the Cu Electroplating process, the resist pattern 110 is protected from an attack of an acidic copper solution.
그다음, 도 3에 도시된 바와 같이, 상기 SiOX막(120)이 형성된 레지스트 패턴(110)상에 배선으로 사용될 구리층(130)을 전기도금법으로 형성한다.Next, as shown in FIG. 3, a copper layer 130 to be used as a wiring is formed on the resist pattern 110 on which the SiO X film 120 is formed by electroplating.
이어서, 도 4에 도시된 바와 같이, 전기도금으로 형성된 상기 구리층(130)을 상기 SiOX막(120)이 노출되도록 화학기계적 연마(CMP) 과정을 진행하여 평탄화시켜 구리배선(130a)을 형성한다.Subsequently, as shown in FIG. 4, the copper layer 130 formed by electroplating is planarized by performing a chemical mechanical polishing (CMP) process to expose the SiO X film 120 to form a copper wiring 130a. do.
그런다음, 도 5에 도시된 바와 같이, 상기 구리배선(130a)을 제외한 나머지 구조물인 상기 SiOX막(120) 및 레지스트 패턴(110)을 옥사이드 에칭(Oxide Etching)으로 제거한다.Then, as shown in FIG. 5, the SiO X film 120 and the resist pattern 110, which are structures other than the copper wiring 130a, are removed by oxide etching.
이어서, 도 6에 도시된 바와 같이, 상기 구리배선(130a)만 남은 기판(100) 전면상에 저유전상수 물질을 갭 필(Gap Fill) 특성이 우수하도록 고밀도플라즈마 화학기상증착법으로 증착하여 저유전 절연물질층(140)을 형성한다.Subsequently, as shown in FIG. 6, a low dielectric constant material is deposited on the entire surface of the substrate 100 having only the copper wiring 130a by a high density plasma chemical vapor deposition method so as to have excellent gap fill characteristics. The material layer 140 is formed.
그런다음, 도 7에 도시된 바와 같이, 상기 저유전 절연물질층(140)을 화학기계적 연마 공정으로 평탄화시켜 층간절연막(140a)으로 형성한다. 그리하여, 저유전 절연물질로 된 층간절연막(140a)에 구리배선(130a)이 매립된 형태의 싱글 다마신 패턴(Single Damascene Pattern)을 완성한다.Then, as shown in FIG. 7, the low dielectric insulating material layer 140 is planarized by a chemical mechanical polishing process to form an interlayer insulating film 140a. Thus, a single damascene pattern of a type in which the copper wiring 130a is embedded in the interlayer insulating film 140a made of a low dielectric insulating material is completed.
상기와 같은 공정을 통하면 저유전 절연물질층(140)에 대한 식각 공정이 완전히 배제된다. 따라서, 식각을 비롯한 애싱 및 세정 공정에 의해 발생되는 유전율 열화(k-value degradation)가 원천적으로 방지된다.Through the above process, the etching process for the low dielectric insulating material layer 140 is completely excluded. Thus, k-value degradation caused by ashing and cleaning processes, including etching, is essentially prevented.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바와 같이 본 발명에 따른 반도체 소자의 싱글 다마신 패턴 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the single damascene pattern forming method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 층간절연막으로 사용되는 저유전율 절연물질에 대한 식각, 에싱 및 세정공정이 배제되므로 유전율 열화(k-value Degradation)가 원천적으로 방지되는 효과가 있다.In the present invention, since the etching, ashing, and cleaning processes for the low dielectric constant insulating material used as the interlayer insulating film are excluded, dielectric constant degradation (k-value degradation) is essentially prevented.
아울러, 안정적인 유전율로 인하여 공정 재현성이 유지되고, 안정적 공정 재현성 유지를 통해 소자 개발 및 생산 수율을 향상시킬 수 있는 효과가 있다.In addition, the process reproducibility is maintained due to the stable dielectric constant, there is an effect that can improve the device development and production yield through maintaining a stable process reproducibility.
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| KR100456420B1 (en) * | 2002-07-04 | 2004-11-10 | 매그나칩 반도체 유한회사 | Method of forming a copper wiring in a semiconductor device |
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| KR100456420B1 (en) * | 2002-07-04 | 2004-11-10 | 매그나칩 반도체 유한회사 | Method of forming a copper wiring in a semiconductor device |
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