CN104124150A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
- Publication number
- CN104124150A CN104124150A CN201310157858.4A CN201310157858A CN104124150A CN 104124150 A CN104124150 A CN 104124150A CN 201310157858 A CN201310157858 A CN 201310157858A CN 104124150 A CN104124150 A CN 104124150A
- Authority
- CN
- China
- Prior art keywords
- layer
- groove
- hard mask
- mask layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
A method for forming a semiconductor device comprises the steps of providing a semiconductor substrate and sequentially forming a dielectric layer, a mask layer and a photoresist layer; forming a groove penetrating the thickness of the photoresist layer; filling the groove with a first hard mask layer; removing the remaining photoresist layer; and utilizing the first hard mask layer to serve as a mask to etch the mask layer and the dielectric layer until a through hole or a groove is formed in the dielectric layer. According to the method, the formed through hole or the groove is not missed easily and is good in appearance, and the semiconductor device comprising the formed through hole or the groove is good in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of semiconductor device.
Background technology
Along with the making of integrated circuit develops to very lagre scale integrated circuit (VLSIC) (ULSI), its inner current densities is increasing, contained number of elements constantly increases, and makes the surface of wafer cannot provide enough areas to make required interconnection line (Interconnect).For co-operating member dwindles rear increased interconnection line demand, utilize the design of the two-layer above multiple layer metal interconnection line that through hole realizes, become the method that very large scale integration technology institute must employing.
Existing technique forms through hole and mainly comprises the steps: to provide Semiconductor substrate, and forms successively from the bottom to top dielectric layer and photoresist layer in described Semiconductor substrate; Formation runs through the groove of described photoresist layer thickness; The photoresist layer that comprises groove of take is mask, dielectric layer is carried out to etching, until form through hole in described dielectric layer.
And constantly dwindling along with feature sizes of semiconductor devices, better in order to make to be formed at the pattern of photoresist layer further groove, avoid pattern in photoresist layer that photoresist layer or impurity because of bottom portion of groove residual fraction thickness causes to be transferred to completely in medium, and avoid being formed at through hole generation disappearance or distortion in dielectric layer, need constantly dwindle the thickness of photoresist layer.Yet, take the photoresist layer that comprises groove, it is mask, when described in etching, dielectric layer forms through hole, because photoresist layer is too thin, before in groove is transferred to dielectric layer completely, part photoresist layer is removed, and the partial through holes disappearance or the pattern that cause being formed in dielectric layer are poor, affects the formation technique of follow-up semiconductor device.
In view of the foregoing, existing technique has also proposed that a kind of to take the layered mask structure that comprises mask layer and mask layer top photoresist layer be mask, and dielectric layer is carried out to etching, forms the method for through hole in dielectric layer.It roughly comprises the steps: first in photoresist layer, to form the groove that runs through photoresist layer thickness, then photoresist layer further groove is transferred in mask layer; After photoresist layer has been consumed, then the groove of mask layer is transferred in dielectric layer, until form through hole in dielectric layer.
But, because thinner thickness and the hardness of photoresist layer are lower, still cannot guarantee that the groove in photoresist layer can be transferred in the mask layer of its below completely, cause being formed at mask layer further groove disappearance or distortion occur, the through hole disappearance or the pattern that finally cause being formed in dielectric layer are poor, the performance of the impact semiconductor device that forms.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device, avoids formed through hole or groove that disappearance and distortion occur, and improves the performance of the semiconductor device that comprises formed through hole or groove.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising:
Semiconductor substrate is provided, and forms successively from the bottom to top dielectric layer, mask layer and photoresist layer in described Semiconductor substrate;
Formation runs through the groove of described photoresist layer thickness;
In described groove, fill full the first hard mask layer;
Remove remaining described photoresist layer;
Described the first hard mask layer of take is mask, and described mask layer and dielectric layer are carried out to etching, until form through hole or groove in described dielectric layer.
Optionally, the material of described the first hard mask layer is spin-coating glass, fills full the first hard mask layer and comprise in described groove: in described groove and the polymer that forms spin-coating glass on the photoresist layer of groove both sides; Polymer to spin-coating glass is cured processing, forms the first hard mask material layer; Removal is positioned at the first hard mask material layer on the photoresist layer of described groove both sides.
Optionally, the method that forms the polymer of described spin-coating glass is spin coating proceeding; The method of described curing processing is that ultraviolet ray is irradiated or baking.
Optionally, on described dielectric layer, forming mask layer comprises: on described dielectric layer, form successively from the bottom to top organic distribution layer and the second hard mask layer.
Optionally, after formation runs through the groove of described photoresist layer thickness, and fill full the first hard mask layer in described groove before, also comprise: in the bottom of described groove and the upper surface of sidewall and groove both sides photoresist layer, form protective layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form mask layer and photoresist layer on dielectric layer after, first form the groove that runs through photoresist layer thickness, in groove, fill again full the first hard mask layer, and remove remaining photoresist layer, take the first hard mask layer as mask, mask layer and dielectric layer are carried out to etching, until form through hole or groove in dielectric layer; Take the first hard mask layer as mask, when mask layer is carried out to etching, due to etching technics to the etch rate of the first hard mask layer much smaller than the etch rate to mask layer, before the photoresist layer pattern that comprises groove is transferred to mask layer completely, guarantee the integrality of pattern in the first hard mask layer, and then guarantee to comprise that the photoresist layer pattern of groove can be transferred in dielectric layer complete, accurately, avoid formed through hole or groove that disappearance and distortion occur, improve the performance of the semiconductor device that comprises formed through hole or groove.
Further, the material of described the first hard mask layer is spin-coating glass; In described groove, filling full the first hard mask layer comprises: in described groove and the polymer that forms spin-coating glass on the photoresist layer of groove both sides; Polymer to spin-coating glass is cured processing, forms the first hard mask material layer; Removal is positioned at the first hard mask material layer on the photoresist layer of described groove both sides.Due to can be by spin coating proceeding in groove and the polymer that forms spin-coating glass on the photoresist layer of groove both sides, even if photoresist layer further groove live width is less, also can guarantee the filling quality of groove, simplify the formation technique of the first hard mask layer.
Further; after formation runs through the groove of described photoresist layer thickness; and fill full the first hard mask layer in described groove before; in the bottom of described groove and the upper surface of sidewall and groove both sides photoresist layer, form protective layer; to protect described photoresist layer in forming the first hard mask layer process, avoid corrosion; the integrality of the photoresist layer pattern that assurance comprises groove; make the pattern of formed through hole or groove better, and then make to comprise that the performance of semiconductor device of formed through hole or groove is better.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the schematic diagram of formation method first embodiment of semiconductor device of the present invention;
Fig. 6 to Fig. 9 is the schematic diagram of formation method second embodiment of semiconductor device of the present invention.
Embodiment
Just as described in the background section, the formed through hole of existing technique easily occur disappearance or pattern poor, cause the performance of formed semiconductor device not good.
Inventor finds through research, can first in Semiconductor substrate, form dielectric layer, mask layer and photoresist layer, and forms the groove that runs through described photoresist layer thickness, and the photoresist layer pattern that makes to comprise groove is corresponding with follow-up formation through hole or groove; Then, in described groove, fill full the first hard mask layer, and remove remaining photoresist layer, take the first hard mask layer as mask, mask layer and dielectric layer described in etching.When to mask layer and dielectric layer etching, due to etching technics to the etch rate of the first hard mask layer much smaller than the etch rate to mask layer, before the photoresist layer pattern that comprises groove is transferred to mask layer completely, can guarantee the integrality of pattern in the first hard mask layer, complete and the pattern that makes to be formed at through hole in dielectric layer or groove is better, the final performance that improves the semiconductor device that comprises formed through hole or groove.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
It should be noted that, below only take and in dielectric layer, form groove as example, the formation method of semiconductor device of the present invention is described, and the method that forms through hole in dielectric layer is similar with the method that forms groove, at this, does not repeat.
The first embodiment
With reference to figure 1, Semiconductor substrate (not shown) is provided, and in described Semiconductor substrate, form successively from the bottom to top dielectric layer 200a, mask layer and photoresist layer 206.
In the present embodiment, the material of described Semiconductor substrate can well known to a person skilled in the art other materials for monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, silicon-on-insulator, III-V group element compound, monocrystalline silicon carbide etc.
In addition, in described Semiconductor substrate, also can be formed with device architecture (not shown), described device architecture can be the device architecture forming in semiconductor FEOL, such as MOS transistor etc.
In the present embodiment, the material of described dielectric layer 200a is low-k materials or super low-k materials, and the method that forms described dielectric layer 200a can be chemical vapor deposition method.
In the present embodiment, described mask layer is sandwich construction.On described dielectric layer 200a, forming mask layer comprises: on described dielectric layer 200a, form successively from the bottom to top organic distribution layer 202a, the second hard mask layer 204 and bottom anti-reflection layer 205.Concrete, the thickness of described organic distribution layer 202a is 500 dust～3000 dusts, its formation method can be spin coating proceeding or depositing operation; The material of described the second hard mask layer 204 is siliceous antireflection material (Si-ARC), low temperature oxide material (Low Tempreture Oxide, referred to as LTO), silicon nitride or titanium nitride, and thickness is 50 dust～1000 dusts; The thickness of described bottom anti-reflection layer 205 is 100 dust～1000 dusts.The thickness of described photoresist layer 206 is 300 dust～1500 dusts.
It should be noted that, in other embodiments, also can omit described bottom anti-reflection layer 205, on the second hard mask layer 204, directly form photoresist layer 206.
Continuation, with reference to figure 1, forms the groove (not shown) that runs through described photoresist layer 206 thickness.
Concrete, the method that forms described groove can be exposure and developing process.The photoresist layer 206 that comprises groove is corresponding with the follow-up shape that is formed at groove in dielectric layer 200a.
Continuation, with reference to figure 1, forms protective layer 208a in the bottom of described groove and the upper surface of sidewall and groove both sides photoresist layer 206.
In the present embodiment, the material of described protective layer 208a can be silica or silicon nitride; The thickness of described protective layer 208a is 10 dust～100 dusts; The method that forms described protective layer 208a can be physical gas-phase deposition, atom layer deposition process or chemical vapor deposition method.
Continuation, with reference to figure 1, forms the first hard mask material layer 210a on described protective layer 208a.
Concrete, the material of described the first hard mask material layer 210a is can the curing polymer of spin coating, forms described the first hard mask material layer 210a and comprises: by spin coating proceeding, on described protective layer 208a, forming can the curing polymer of spin coating; To being cured processing by the curing polymer of spin coating, form the first hard mask material layer 210a.To can the curing polymer of spin coating being cured the method for processing, can be that ultraviolet ray is irradiated or baking.
It should be noted that, can also need to meet by the curing polymer of spin coating: when the described photoresist layer 206 of follow-up removal, be cured and can there is higher selection ratio with photoresist layer 206 by the curing polymer of spin coating after processing, with in removing described photoresist layer 206 processes, avoid being cured can be removed by the curing polymer of spin coating after processing.
In the present embodiment, the material of described the first hard mask material layer 210a is spin-coating glass (Spin On Glass, referred to as SOG, main component is SiOCH).Concrete, form described the first hard mask material layer 210a and comprise: the polymer (organic substance that comprises Si, C and O atom) that forms spin-coating glass on described protective layer 208a; Polymer to spin-coating glass is cured processing, forms the first hard mask material layer 210a.
Owing to can the curing polymer of spin coating being liquid, it has good filling capacity, and the groove that comprises protective layer 208a can be filled up by the curing polymer of spin coating completely; To after can the curing polymer of spin coating being cured processing, photoresist layer 206 patterns that comprise groove are transferred in protective layer 208 and the first hard mask material layer 210a completely.
Due to what be not cured processing, can the curing polymer of spin coating be organic substance; it has stronger corrosivity; on photoresist layer 206 by the bottom at groove and sidewall and groove both sides, form protective layer 208a; can effectively protect described photoresist layer 206; avoid affecting the pattern of formed groove because photoresist layer 206 is corroded, improved the performance of the semiconductor device that comprises groove.
In other embodiments; can also omit described protective layer 208a; in described groove and on the photoresist layer 206 of groove both sides, directly formation can the curing polymer of spin coating; and adopt ultraviolet ray irradiate or toast being cured processing by the curing polymer of spin coating, form the first hard mask material layer 210a.
With reference to figure 2, to remove in Fig. 1 and be positioned at the first hard mask material layer 210a and the protective layer 208a on groove both sides photoresist layer 206, residue is positioned at the protective layer 208b on bottom portion of groove and sidewall and is positioned at the first hard mask layer 210b of described groove.
In the present embodiment, removing the first hard mask material layer 210a be positioned on groove both sides photoresist layer 206 and the method for protective layer 208a is dry etching, and the gas of described dry etching can be fluoro-gas, as CF
4, CHF
3deng.
With reference to figure 3, remove photoresist layer 206 described in Fig. 2.
In the present embodiment, the method for removing described photoresist layer 206 is cineration technics, and its concrete technology is well known to those skilled in the art, and does not repeat them here.
When removing described photoresist layer 206 by cineration technics, because cineration technics is higher to the selection of can the spin coating curing polymer after solidify processing and photoresist layer 206, cineration technics is less to the removal speed of can the spin coating curing polymer after solidify processing, can effectively avoid being cured can be removed in cineration technics by the curing polymer of spin coating after processing, in the first hard mask layer 210b, the pattern of channel patterns is better.
With reference to figure 4; take the first hard mask layer 210b described in Fig. 3 and protective layer 208b is mask; described bottom anti-reflection layer 205, the second hard mask layer 204, organic distribution layer 202a and dielectric layer 200a are carried out to etching, until form groove 212 in dielectric layer 200b.
It should be noted that, because organic distribution layer 202a in Fig. 3 is thicker, after forming groove 212, dielectric layer 200b at least goes back on surface organic distribution layer 202b of remainder thickness.
In the present embodiment, described bottom anti-reflection layer 205, the second hard mask layer 204, organic distribution layer 202a are jointly as mask layer.Although the thickness of the thickness of the first hard mask layer 210b and photoresist layer 206 is more or less the same, but because the first hard mask layer 210b is hard compared with photoresist layer 206, in etching, form in the process of groove, etching technics is less to the etch rate of the first hard mask layer 210b, before in the pattern of groove is transferred to bottom anti-reflection layer 205 completely, guarantee the integrality of channel patterns (the former photoresist layer that comprises groove 206 patterns) in the first hard mask layer 210b.After etching process in, after the first hard mask layer 210b and protective layer 208b have been consumed, by bottom anti-reflection layer 205, make mask; After bottom anti-reflection layer 205 has been consumed, by the second hard mask layer 204, make mask; After the second hard mask layer 204 has been consumed, organic distribution layer 200a makees mask, channel patterns is progressively transferred in bottom anti-reflection layer 205, the second hard mask layer 204, organic distribution layer 202b and dielectric layer 200b, guarantee, before organic distribution layer 200a has been consumed, in dielectric layer 200b, to form groove 212.
In the present embodiment, when described photoresist layer 206 is exposed, described bottom anti-reflection layer 205 can prevent that the light in exposure device from reflecting, the photoresist layer outside groove is exposed, and the pattern of the impact groove that forms.Take the first hard mask material layer 210a and protective layer 208a, it is mask; when etching forms groove 212; described bottom anti-reflection layer 205 can also further increase the thickness of mask layer; form groove 212 in dielectric layer 200b after; guarantee that dielectric layer 200b is still covered by part mask layer, and then guarantee the pattern of the groove that forms 212.
With reference to figure 5, remove organic distribution layer 202b described in Fig. 4.
In the present embodiment, the method for removing described organic distribution layer 202b can be dry etching, also can be wet etching, and it does not limit the scope of the invention.
Finally, at the full metal of the interior filling of groove described in Fig. 5 212, to form metal interconnecting wires (not shown).
Concrete, the material of described metal interconnecting wires can be copper, and it specifically forms technique and is well known to those skilled in the art, and does not repeat them here.
In the present embodiment, form successively from the bottom to top the mask layer and photoresist layer of dielectric layer, sandwich construction in Semiconductor substrate after, first by exposure and developing process, form the groove that runs through its thickness in photoresist layer, the photoresist layer pattern that makes to comprise groove is corresponding with the channel patterns of follow-up formation; Then bottom and the sidewall at groove forms protective layer, and within comprising the groove of protective layer, fills the first hard mask layer that full material is spin-coating glass; Then remove photoresist layer, usining the first hard mask layer and protective layer carries out etching to mask layer, dielectric layer successively as mask, and channel patterns is transferred in interlayer dielectric layer, forms groove; Finally in groove, fill full metal, to form metal interconnecting wires.Because the polymer of spin-coating glass has good filling capacity, guarantee that the first hard mask layer can fill up the groove that comprises protective layer, and then guarantee that channel patterns can be transferred in the first hard mask layer and protective layer complete, accurately; Again because the hardness of spin-coating glass is larger, can be before channel patterns be transferred to mask layer, guarantee the integrality of channel patterns, and then guarantee that channel patterns can be transferred in interlayer dielectric layer complete, exactly, make the pattern of formed groove better, and then make the pattern of formed metal interconnecting wires better, improved the performance of the semiconductor device that comprises formed metal interconnecting wires.
The second embodiment
With reference to figure 6, Semiconductor substrate (not shown) is provided, in described Semiconductor substrate, form successively from the bottom to top dielectric layer 300a, mask layer 302a and photoresist layer 304, and form the groove (not shown) that runs through described photoresist layer 304 thickness.
In the present embodiment, the material of described Semiconductor substrate and dielectric layer 300a, formation technique please, respectively with reference to the appropriate section in the first embodiment, do not repeat them here.
In the present embodiment, described mask layer 302a is single layer structure.The material of described mask layer 302a can be bottom anti-reflective material, and the method that forms described mask layer 302a is spin coating proceeding; The thickness of described mask layer 302a is 500 dust～3000 dusts.The thickness of described photoresist layer 304 is 300 dust～1500 dusts.
Continuation, with reference to figure 6, forms the first hard mask material layer 306a in described groove and on the photoresist layer 304 of groove both sides.
In the present embodiment, identical with material, the formation method of the first hard mask material layer 210a in the first embodiment in material, the formation method of described the first hard mask material layer 306a, do not repeat them here.
With reference to figure 7, remove the first hard mask material layer 306a on the photoresist layer 304 of Fig. 6 further groove both sides, to the upper surface that exposes described photoresist layer 304, residue is positioned at the first hard mask layer 306b of groove.
In the present embodiment, the method for removing the first hard mask material layer 306a on the photoresist layer 304 of groove both sides is dry etching, and the gas of described dry etching can be fluoro-gas.
With reference to figure 8, remove photoresist layer 304 described in Fig. 7, and to take the first hard mask layer 306b be mask, mask layer 302a and dielectric layer 300a described in etching, channel patterns (pattern of the former photoresist layer that comprises groove 304) in the first hard mask layer 306b is transferred in mask layer 302b and dielectric layer 300b, in dielectric layer 300b, forms groove 308.
In the present embodiment, the method for mask layer 302a and dielectric layer 300a can be dry etching described in etching, and its concrete etching technics is well known to those skilled in the art, and does not repeat them here.
Because described mask layer 302a is thicker, form groove 308 in dielectric layer 300b after, guarantee on dielectric layer 300b the still mask layer 302b of remainder thickness, guaranteed the pattern of the groove that forms 308.
With reference to figure 9, remove remaining mask layer 302b in Fig. 8.
In the present embodiment, remove remaining mask layer 302b in Fig. 8 and can be cineration technics, the gas of described cineration technics can be oxygen.
In other embodiments, after formation runs through the groove of described photoresist layer 304 thickness, and before forming described the first hard mask material layer 306a, can also comprise: in described groove and on the photoresist layer 304 of groove both sides, form protective layer.The material of described protective layer, thickness and formation method please refer to the first embodiment, do not repeat them here.Described protective layer can be protected described photoresist layer 304 in the first hard mask material layer 306a forming process, finally makes the pattern of formed groove 308 better.Now, on the photoresist layer 304 of removal groove both sides, after the first hard mask material layer 306a, also need removal to be positioned at the protective layer on groove both sides photoresist layer 304, so that described photoresist layer 304 exposes, be beneficial to the removal technique of follow-up photoresist layer.
Finally, at the full metal of the interior filling of groove described in Fig. 9 308, to form metal interconnecting wires (not shown).The material of described metal interconnecting wires can be copper, and it specifically forms technique and is well known to those skilled in the art, and does not repeat them here.
In the present embodiment, form successively from the bottom to top the mask layer and photoresist layer of dielectric layer, single layer structure in Semiconductor substrate after, first by exposure and developing process, form the groove that runs through its thickness in photoresist layer, the photoresist layer pattern that makes to comprise groove is corresponding with the channel patterns of follow-up formation; Then in groove, fill the first hard mask layer that full material is spin-coating glass; Then remove photoresist layer, first hard mask layer of usining carries out etching to mask layer, dielectric layer successively as mask, and channel patterns is transferred in interlayer dielectric layer, forms groove; Finally in groove, fill full metal, to form metal interconnecting wires.When forming the first hard mask layer, because the polymer of spin-coating glass has good filling capacity, guarantee that the first hard mask layer can fill up described groove, and then guarantee that channel patterns can be transferred in the first hard mask layer complete, accurately; Again because the hardness of spin-coating glass is larger, can be before channel patterns be transferred to mask layer, guarantee the integrality of channel patterns, and then guarantee that channel patterns can be transferred in interlayer dielectric layer complete, exactly, make the pattern of formed groove better, and then make the pattern of formed metal interconnecting wires better, comprise that the performance of semiconductor device of formed metal interconnecting wires is better.
Compare with the first embodiment, in the present embodiment, described mask layer is single layer structure, and the technique that forms mask layer is simple, has saved the time that forms groove, has reduced the cost that forms groove.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. a formation method for semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided, and forms successively from the bottom to top dielectric layer, mask layer and photoresist layer in described Semiconductor substrate;
Formation runs through the groove of described photoresist layer thickness;
In described groove, fill full the first hard mask layer;
Remove remaining described photoresist layer;
Described the first hard mask layer of take is mask, and described mask layer and dielectric layer are carried out to etching, until form through hole or groove in described dielectric layer.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described the first hard mask layer is spin-coating glass, fills full the first hard mask layer and comprise in described groove:
In described groove and the polymer that forms spin-coating glass on the photoresist layer of groove both sides;
Polymer to described spin-coating glass is cured processing, to form the first hard mask material layer;
Removal is positioned at the first hard mask material layer on the photoresist layer of described groove both sides.
3. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the method that forms the polymer of described spin-coating glass is spin coating proceeding; The method of described curing processing is that ultraviolet ray is irradiated or baking.
4. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the method that removal is positioned at the first hard mask material layer on the photoresist layer of described groove both sides is dry etching.
5. the formation method of semiconductor device as claimed in claim 1, is characterized in that, described mask layer is sandwich construction.
6. the formation method of semiconductor device as claimed in claim 5, is characterized in that, forms mask layer and comprise on described dielectric layer: on described dielectric layer, form successively from the bottom to top organic distribution layer and the second hard mask layer.
7. the formation method of semiconductor device as claimed in claim 6, is characterized in that, the thickness of described organic distribution layer is 500 dust～3000 dusts; The material of described the second hard mask layer is siliceous antireflection material, low temperature oxide material, silicon nitride or titanium nitride, and thickness is 50 dust～1000 dusts.
8. the formation method of semiconductor device as claimed in claim 6, is characterized in that, after forming described the second hard mask layer, and before forming described photoresist layer, also comprises: on described the second hard mask layer, form bottom anti-reflection layer.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, described mask layer is single layer structure.
10. the formation method of semiconductor device as claimed in claim 9, is characterized in that, the material of described mask layer is bottom anti-reflective material, and thickness is 500 dust～3000 dusts.
The formation method of 11. semiconductor device as claimed in claim 1; it is characterized in that; after formation runs through the groove of described photoresist layer thickness; and fill full the first hard mask layer in described groove before, also comprise: in the bottom of described groove and the upper surface of sidewall and groove both sides photoresist layer, form protective layer.
The formation method of 12. semiconductor device as claimed in claim 1, is characterized in that, after forming through hole or groove, also comprises: in described through hole or groove, fill full metal, to form metal plug or metal interconnecting wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310157858.4A CN104124150A (en) | 2013-04-28 | 2013-04-28 | Method for forming semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310157858.4A CN104124150A (en) | 2013-04-28 | 2013-04-28 | Method for forming semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104124150A true CN104124150A (en) | 2014-10-29 |
Family
ID=51769520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310157858.4A Pending CN104124150A (en) | 2013-04-28 | 2013-04-28 | Method for forming semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104124150A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020083330A1 (en) * | 2018-10-24 | 2020-04-30 | 浙江驰拓科技有限公司 | Manufacturing method for semiconductor device |
| WO2023284010A1 (en) * | 2021-07-13 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method, semiconductor structure, and memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05129299A (en) * | 1991-11-01 | 1993-05-25 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| KR100620195B1 (en) * | 2002-12-30 | 2006-09-01 | 동부일렉트로닉스 주식회사 | Method for forming gate pole |
| WO2013022081A1 (en) * | 2011-08-11 | 2013-02-14 | ＡｚエレクトロニックマテリアルズＩｐ株式会社 | Composition for forming tungsten oxide film and method for producing tungsten oxide film using same |
-
2013
- 2013-04-28 CN CN201310157858.4A patent/CN104124150A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05129299A (en) * | 1991-11-01 | 1993-05-25 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| KR100620195B1 (en) * | 2002-12-30 | 2006-09-01 | 동부일렉트로닉스 주식회사 | Method for forming gate pole |
| WO2013022081A1 (en) * | 2011-08-11 | 2013-02-14 | ＡｚエレクトロニックマテリアルズＩｐ株式会社 | Composition for forming tungsten oxide film and method for producing tungsten oxide film using same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020083330A1 (en) * | 2018-10-24 | 2020-04-30 | 浙江驰拓科技有限公司 | Manufacturing method for semiconductor device |
| CN111092014A (en) * | 2018-10-24 | 2020-05-01 | 中电海康集团有限公司 | Method for manufacturing semiconductor device |
| WO2023284010A1 (en) * | 2021-07-13 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method, semiconductor structure, and memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8916472B2 (en) | Interconnect formation using a sidewall mask layer | |
| US10937694B2 (en) | Chamferless via structures | |
| CN102044426B (en) | Semiconductor device and manufacturing method thereof | |
| CN101355047B (en) | Method for forming through hole in low dielectric coefficient medium layer | |
| CN107346759B (en) | Semiconductor structure and manufacturing method thereof | |
| CN104037121A (en) | Method Of Fabricating Air Gap By Using Damascene Process | |
| US11495684B2 (en) | Method of removing an etch mask | |
| CN104124137A (en) | Semiconductor device forming method | |
| CN104979203A (en) | MOS transistor and formation method of conductive plug | |
| CN105789111A (en) | Formation method for semiconductor structure | |
| CN106158725A (en) | The forming method of semiconductor structure | |
| CN103337476A (en) | Method for reducing critical size of copper interconnection groove | |
| CN103066014A (en) | Copper/ air gap preparation method | |
| CN101123212B (en) | Forming method for contact hole | |
| CN104124150A (en) | Method for forming semiconductor device | |
| CN102820260A (en) | Method for improving via hole pattern performance expression | |
| US9831124B1 (en) | Interconnect structures | |
| CN102299097B (en) | Method for etching metal connecting line | |
| CN104347489A (en) | Forming method of conductive plug | |
| CN104022068A (en) | Semiconductor structure and forming method thereof | |
| CN105336676B (en) | The forming method of contact plunger | |
| CN111430241B (en) | Semiconductor structure and forming method thereof | |
| US20230369104A1 (en) | Method for manufacturing semiconductor device | |
| CN105742183A (en) | Method for forming semiconductor structure | |
| CN105742229A (en) | Method for forming semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20141029 |
|
| RJ01 | Rejection of invention patent application after publication |