CN104347489A - Forming method of conductive plug - Google Patents
Forming method of conductive plug Download PDFInfo
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- CN104347489A CN104347489A CN201310342926.4A CN201310342926A CN104347489A CN 104347489 A CN104347489 A CN 104347489A CN 201310342926 A CN201310342926 A CN 201310342926A CN 104347489 A CN104347489 A CN 104347489A
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- dielectric layer
- interlayer dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
The invention relates to a forming method of a conductive plug. The forming method comprises the following steps of providing a substrate which is provided with a source and a drain, forming a first interlayer dielectric layer with an opening in the substrate, filling a metal layer in the opening, covering the surface of the first interlayer dielectric layer by the metal layer, and chemically and mechanically polishing the metal layer to the first interlayer dielectric layer so as to form a metal grid, wherein chemical and mechanical polishing residues are formed on the surface of the first interlayer dielectric layer; etching one thick part of the first interlayer dielectric layer to remove the residues; forming a second interlayer dielectric layer on the remained first interlayer dielectric layer and the surface of the metal grid; forming a source through hole and a drain through hole in the second interlayer dielectric layer and the first interlayer dielectric layer, wherein the source through hole is formed in a source, and the drain through hole is formed in a drain; filling the source through hole and the drain through hole with conductive layers to form a source conductive plug and a drain conductive plug. The method has the advantages that the failure density of the conductive plugs on the substrate is reduced, and the property of a subsequently formed semiconductor device is further improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to the formation method of conductive plunger.
Background technology
Along with the making of integrated circuit develops to very lagre scale integrated circuit (VLSIC), the current densities of IC interior is increasing, and the number of elements comprised also gets more and more, and this development makes crystal column surface that enough area cannot be provided to make required interconnection line.
In order to meet element reduce after interconnection line demand, the design of two-layer and two-layer above multiple layer metal interconnection line becomes a kind of method that very large scale integration technology adopts usually.At present, the conducting between the device in different metal layer or metal level and substrate is realized by the conductive plunger in the dielectric layer between metal level and metal level or between metal level and substrate.
The formation method of conductive plunger in prior art, concrete formation method is as follows:
The substrate being formed with source electrode, drain electrode is provided.Substrate is formed first interlayer dielectric layer with opening, in opening, fills aluminium lamination.First interlayer dielectric layer is chemically mechanically polished to aluminium lamination, forms aluminium gate.The second interlayer dielectric layer is formed on the surface of the first interlayer dielectric layer and aluminium gate.Between the second layer, dielectric layer surface forms the photoresist of patterning, the position of definition aluminium gate through hole, source electrode through hole and drain electrode through hole and distribution, with the photoresist of patterning for mask, second interlayer dielectric layer and the first interlayer dielectric layer are etched, forms gate via, source electrode through hole and drain electrode through hole.Adopt the metal filled gate via of tungsten, source electrode through hole and drain electrode through hole, form grid tungsten plug, source electrode tungsten plug and drain electrode tungsten plug.Grid tungsten plug, source electrode tungsten plug and drain electrode tungsten plug are electrically connected with aluminium gate, source electrode and drain electrode respectively.
In prior art, the failure density of suprabasil tungsten plug is higher, affects the performance of the semiconductor device of follow-up formation.
Summary of the invention
The problem that the present invention solves is that the failure density of suprabasil tungsten plug in prior art is higher, affects the performance of the semiconductor device of follow-up formation.
For solving the problem, the invention provides a kind of formation method of conductive plunger, it is characterized in that, comprising:
The substrate being formed with source electrode and drain electrode is provided, form first interlayer dielectric layer with opening on the substrate, metal level is filled in described opening, described metal level also covers dielectric layer surface between described ground floor, be chemically mechanically polished to described first interlayer dielectric layer to described metal level and form metal gates, between described ground floor, dielectric layer surface has CMP residues;
First interlayer dielectric layer of etched portions thickness is to remove described residue;
The second interlayer dielectric layer is formed at remaining described first interlayer dielectric layer and described metal gates surface;
Formed in described second interlayer dielectric layer and described first interlayer dielectric layer and be positioned at the source electrode through hole on source electrode, the drain electrode through hole be positioned in drain electrode;
In described source electrode through hole, drain electrode through hole, filled conductive layer forms source conductive connector, Drain Electrodes Conductive connector.
Optionally, the first interlayer dielectric layer of described etched portions thickness, with before the step removing described residue, is chemically mechanically polished to after described first interlayer dielectric layer forms the step of metal gates to described metal level, also comprises the following steps:
Oxidation processes is carried out to described metal gates, forms metal oxide layer on described metal gates surface.
Optionally, the method for described metal gates being carried out to oxidation processes comprises: adopt and bombard described metal gates surface containing oxygen plasma, or,
Adopt oxygen and described metal gates surface that chemical reaction occurs.
Optionally, described is oxygen plasma, carbon monoxide plasma, carbon dioxide plasma or ozone plasma containing oxygen plasma.
Optionally, described containing oxygen plasma be oxygen plasma time, formed by oxygen plasma, the flow velocity of described oxygen is 100sccm ~ 400sccm, and bias power is 200W ~ 2000W, and the time of described oxidation processes is 5s ~ 20s.
Optionally, the thickness of described metal oxide layer is 5 dust ~ 15 dusts.
Optionally, the etching gas of the first interlayer dielectric layer of etched portions thickness is CF
4, CH
3one or more in F or CO, bias power is less than 500W.
Optionally, described segment thickness is 30 dust ~ 70 dusts.
Optionally, described metal gates is aluminium gate, and described metal oxide layer is alumina layer.
Optionally, the formation method of conductive plunger described in the technical program also comprises:
In described second interlayer dielectric layer, form gate via, described gate via is positioned on described metal gates;
In described gate via, filled conductive layer forms Gate Electrode Conductive connector.
Optionally, the material of described first interlayer dielectric layer is SiO
2.
Optionally, the material of described second interlayer dielectric layer is SiO
2.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the present embodiment, the first interlayer dielectric layer of etched portions thickness, can remove residue.The second interlayer dielectric layer is formed after removing residue, when in the first interlayer dielectric layer and the second interlayer dielectric layer, etching is formed and is positioned at the source electrode through hole on source electrode, the drain electrode through hole be positioned in drain electrode, etching forms source electrode through hole, the position of drain electrode through hole can not be stopped by the residue of dielectric layer surface between ground floor, can make source electrode through hole, drain electrode through hole through in the first interlayer dielectric layer and the second interlayer dielectric layer, can make source electrode through hole, drain electrode through hole bottom expose source electrode, drain electrode respectively.The source conductive connector that filled conductive layer is formed in this source electrode through hole, drain electrode through hole, Drain Electrodes Conductive connector can be electrically connected with the source electrode in substrate and drain electrode, thus the failure density of the conductive plunger that reduction substrate is formed, and then improve the performance of semiconductor device of follow-up formation.
Further, first interlayer dielectric layer of etched portions thickness is with before removing described residue, after described metal level being chemically mechanically polished to the step of described first interlayer dielectric layer formation metal gates, oxidation processes is carried out to metal gates surface, forms metal oxide layer on the surface of metal gates.This metal oxide layer can protect metal gates injury-free in the process of the first interlayer dielectric layer of etched portions thickness.Moreover when in the second interlayer dielectric layer, etching forms the process of gate via, metal oxide layer can also protect metal gates, this metal gates is formed in the process of gate via in etching and reduces damage.At this moment, metal oxide layer also can be removed clean along band etching in above-mentioned two step etchings.If metal oxide layer also has a small amount of residue in above-mentioned two step etchings; in gate via, filled conductive layer is formed in the process of Gate Electrode Conductive connector; need to adopt the method for sputter deposition in gate via, form laying and diffusion impervious layer; Ar ion in sputter deposition method can bombard metal gates surface; therefore; remaining metal oxide layer can also protect metal gates in sputter deposition, reduce damage; meanwhile, remaining metal oxide layer is removed clean in described sputter deposition step.And then, the performance of the semiconductor device of follow-up formation can be improved further.
Accompanying drawing explanation
Fig. 1 ~ Fig. 2 is the generalized section of formation method in each production phase of conductive plunger in prior art;
Fig. 3 ~ Fig. 9 is the generalized section of formation method in each production phase of conductive plunger in the embodiment of the present invention.
Embodiment
The analysis found that, in prior art, the failure density of suprabasil tungsten plug is higher.Wherein, suprabasil tungsten plug lost efficacy three kinds of situations: the inefficacy of source electrode tungsten plug, the inefficacy of drain electrode tungsten plug, source electrode tungsten plug and drain electrode tungsten plug lost efficacy simultaneously.
Lost efficacy for suprabasil source electrode tungsten plug and drain electrode tungsten plug below simultaneously and be described, the failure density of suprabasil tungsten plug is higher, and the reason affecting the performance of the semiconductor device of follow-up formation is:
With reference to figure 1, the first interlayer dielectric layer 11 is chemically mechanically polished to aluminium lamination, forms aluminium gate 12.After adopting the method for chemico-mechanical polishing aluminium lamination to be planarized to the first interlayer dielectric layer 11, residue 13 is formed on the surface of the first interlayer dielectric layer 11, residue 13 meeting cover part first interlayer dielectric layer 11, time serious, residue 13 can cover the first interlayer dielectric layer 11 flood (with reference to figure 2).This residue 13 be formed with two reasons: be on the one hand the residual of metallic aluminium; Be in the process of chemico-mechanical polishing aluminium lamination on the other hand, polishing fluid aluminium lamination being carried out to polishing does not clean up, and this polishing fluid with the first interlayer dielectric layer 11 surface, chemical reaction occurs again and produces, and in actual process, more difficult cleaning is removed.Then, the second interlayer dielectric layer 14 is formed on the surface of the first interlayer dielectric layer 11 and aluminium gate 12.
With reference to figure 2, the photoresist (not shown) of patterning is formed on the second interlayer dielectric layer 14 surface, the position of definition aluminium gate through hole, source electrode through hole and drain electrode through hole and distribution, with the photoresist of patterning for mask, second interlayer dielectric layer 14 and the first interlayer dielectric layer 11 are etched, forms gate via 15, source electrode through hole 16 and drain electrode through hole 17.
In the second interlayer dielectric layer 14, form gate via 15, etching is formed in the process of source electrode through hole 16 and drain electrode through hole 17 in the first interlayer dielectric layer 11 and the second interlayer dielectric layer 14, the position that etching forms source electrode through hole 16 and drain electrode through hole 17 is stopped by the residue 13 on the first interlayer dielectric layer 11 surface, make source electrode through hole 16 and drain electrode through hole 17 cannot continue to be etched to the bottom of the first interlayer dielectric layer 11 to expose source electrode and drain surface, but stop at residue 13 place.
Adopt the metal filled gate via 15 of tungsten, source electrode through hole 16 and drain electrode through hole 17, form grid tungsten plug, source electrode tungsten plug and drain electrode tungsten plug.Grid tungsten plug can be electrically connected with grid, but source electrode tungsten plug and drain electrode tungsten plug cannot be electrically connected with draining with source electrode, causes source electrode tungsten plug and drain electrode tungsten plug all to lose efficacy, thus affects the performance of Subsequent semiconductor device.
Correspondingly, a kind of formation method of conductive plunger is inventor provided.For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to figure 3, provide the substrate 30 being formed with source electrode and drain electrode, described substrate 30 is formed first interlayer dielectric layer 31 with opening, in described opening, fills metal level 32 '.
In the present embodiment, the material of described substrate 30 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be other material, such as GaAs etc. III-V compounds of group.Substrate 30 inside is formed with source electrode (not shown) or drain electrode (not shown).Substrate 30 inside is also formed with isolation structure, and described isolation structure can be fleet plough groove isolation structure, or well known to a person skilled in the art other isolation structures for device isolation or active area isolation.
Adopt the method for deposition in substrate 30, form the first interlayer dielectric layer 31.The material of the first interlayer dielectric layer 31 is SiO
2.
After forming the first interlayer dielectric layer 31, first interlayer dielectric layer 31 forms patterned mask layer (not shown), the definition position of opening and shape, then with patterned mask layer for mask etching first interlayer dielectric layer 31, formation opening the first interlayer dielectric layer 31 in.In the present embodiment, described patterned mask layer is photoresist.Then, depositing metal layers 32 ' in opening, described metal level 32 ' also covers the first interlayer dielectric layer 31.Be aluminium lamination in the present embodiment, in other embodiments, other metal levels that also can be well known to those skilled in the art.
With reference to figure 4, be chemically mechanically polished to described first interlayer dielectric layer 31 form metal gates 32 to described metal level 32 ', described first interlayer dielectric layer 31 surface has CMP residues 33.
In the present embodiment, after the first interlayer dielectric layer 31 inside forms metal gates 32, CMP residues 33(can be formed on the surface of the first interlayer dielectric layer 31 and hereinafter be called for short residue 33), this residue 33 be formed with two reasons: be the residual of metallic aluminium on the one hand; Be in the process of chemico-mechanical polishing aluminium lamination on the other hand, polishing fluid aluminium lamination being carried out to polishing does not clean up, and this polishing fluid with the first interlayer dielectric layer 31 surface, chemical reaction occurs again and produces, and in actual process, more difficult cleaning is removed.
With reference to figure 5, oxidation processes is carried out to described metal gates 32, form metal oxide layer 34 on described metal gates 32 surface.
In the present embodiment, metal oxide layer 34 is by bombarding metal gates 32 surface containing oxygen plasma, makes metal gates 32 surface oxidation form metal oxide layer 34, in the present embodiment, forms alumina layer on aluminium gate surface.
Wherein, be formed by the gas plasma in plasm reaction cavity comprising oxygen element containing oxygen plasma.Described plasm reaction cavity can be MMT(Modified Magnetron Tped, modified model magnetoelectricity tubular type) plasma reaction chamber, SPA(Slot Plan Antenna, channel-shaped surface antenna type) plasma reaction chamber or other similar plasm reaction cavity.The more excellent employing oxygen plasma of the present embodiment carries out bombardment to metal gates 32 surface and forms metal oxide layer 34, and wherein, oxygen plasma is formed by oxygen plasma.Concrete technology is: the flow velocity of oxygen is that 100sccm(marks condition milliliter per minute) ~ 400sccm(mark condition milliliter per minute), bias power is 200W ~ 2000W, and the time of oxidation processes is 5s ~ 20s.The flow velocity of oxygen is too large, bias power is too high or oxidation treatment time is oversize, the metal oxide layer 34 of formation can be made too thick, be difficult to remove totally in subsequent technique, the metal oxide formed remains the resistance of the conductive plunger that can increase follow-up formation, thus affects the performance of the device of follow-up formation.The flow velocity of oxygen is too little, bias power is too low or oxidation treatment time is too short, and metal oxide layer 34 densification or the thickness low LCL not of formation, makes metal oxide layer 34 pairs of metal gates 32 not have the effect of protection.Thickness 5 dust ~ 15 dust of the metal oxide layer 34 adopting said method to be formed.In other embodiments, thickness range can be regulated according to the size of device.In other embodiments, the flow velocity of oxygen, bias power or oxidation treatment time can the differences of different according to concrete technology from plasma apparatus and different.
In other embodiments, also CO (carbon monoxide converter) gas, carbon dioxide or ozone-plasma can be formed containing oxygen plasma.
In other embodiments, in reaction chamber, also can metal gates surface be enclosed in the atmosphere of oxygen, oxidation chemistry reaction occurs, form metal oxide layer on metal gates surface.
In conjunction with reference to figure 5 and Fig. 6, after forming described metal oxide layer 34, the first interlayer dielectric layer 31 of etched portions thickness is to remove described residue 33.
Metal oxide layer 34 is when the first interlayer dielectric layer 31 of etched portions thickness, and metal oxide 34 can protect metal gates 32 injury-free.
In the present embodiment, the etching gas of the first interlayer dielectric layer 31 of etched portions thickness is CF
4, CH
3one or more in F or CO, bias power is less than 500W.Why bias power is less than 500W; be because: when the first interlayer dielectric layer 31 of etched portions thickness is to remove described residue 33; the thickness of metal oxide layer 34 also can remove segment thickness along band etching; thus make the reduced thickness of metal oxide layer 34; if bias voltage is too large; easily metal oxide layer 34 is carried out over etching, metal oxide layer 34 pairs of aluminium gate cannot be protected, therefore can produce damage to aluminium gate.Described segment thickness is 30 dust ~ 70 dusts.If the thickness of etching removal first interlayer dielectric layer 31 is too large, aluminium gate can be more higher than the first interlayer dielectric layer 31, when subsequent deposition the second interlayer dielectric layer, between adjacent aluminium gate, depth-to-width ratio is relatively large, easily makes to form air-gap in the second interlayer dielectric layer of follow-up formation.This space gap can affect the performance of the device of follow-up formation.If the thickness of etching removal first interlayer dielectric layer 31 is too little, be not easy the residue 33 on the first interlayer dielectric layer 31 surface to remove.
With reference to figure 7, form the second interlayer dielectric layer 35 at described metal oxide layer 34 and remaining described first interlayer dielectric layer 31 surface.
In the present embodiment, the material of the second interlayer dielectric layer 35 is SiO2.Form the method for the second interlayer dielectric layer 35 for deposition.
With reference to figure 8, formed in the second interlayer dielectric layer 35 and the first interlayer dielectric layer 31 and be positioned at the source electrode through hole 362 on source electrode, the drain electrode through hole 363 be positioned in drain electrode, in the second interlayer dielectric layer, form gate via 361.
In the present embodiment, bottom gate via 361, expose aluminium gate.Source electrode through hole 362 and drain electrode through hole 363 are through the first interlayer dielectric layer 31 and the second interlayer dielectric layer 35, and source electrode and drain electrode are exposed, not shown source electrode and drain electrode respectively in the bottom of source electrode through hole 362 and drain electrode through hole 363.
The method forming source electrode through hole 361, drain electrode through hole 362 and gate via 363 is dry etching, for those skilled in the art know technology, does not repeat them here.Source electrode through hole 361, drain electrode through hole 362 are formed in same step photoetching process, gate via can be formed in same step photoetching process with source electrode through hole 361, drain electrode through hole 362, also can be formed before formation source electrode through hole 361, drain electrode through hole 362, can also be formed after formation source electrode through hole 361, drain electrode through hole 362.In the present embodiment, gate via and source electrode through hole 361, drain electrode through hole 362 are formed in same step photoetching process.
With reference to figure 9, in described source electrode through hole 362, drain electrode through hole 363, filled conductive layer forms source conductive connector 372, Drain Electrodes Conductive connector 373.In gate via 361, filled conductive layer forms Gate Electrode Conductive connector 371.
In the present embodiment, conductive layer can be aluminium, copper or tungsten metal.Concrete formation method is: first bottom gate via 361, source electrode through hole 362 and drain electrode through hole 363 and sidewall adopt the method for sputter deposition to form one deck laying, described laying is titanium layer, act as: as the follow-up adhesive inserted between conductive layer in through hole and the second interlayer dielectric layer 35.
Then, laying adopt the method for sputter deposition form one deck diffusion impervious layer, to stop the diffusion of the follow-up conductive layer be packed in through hole.Described diffusion impervious layer is titanium nitride layer.
Finally, in gate via 361, source electrode through hole 362 and drain electrode through hole 363, filled conductive layer forms Gate Electrode Conductive connector 371, source conductive connector 372 and Drain Electrodes Conductive connector 373 respectively.
It should be noted that: in the present embodiment, as mentioned above, the first interlayer dielectric layer 31 of etched portions thickness is to remove in the process of described residue 33, and metal oxide layer 34 also also can be removed segment thickness by along band.When in the second interlayer dielectric layer 35, etching forms gate via 361, there will be two kinds of situations for remaining metal oxide layer 34: situation 1, and remaining metal oxide layer 34 can continue to be removed segment thickness by along band; Situation 2, remaining metal oxide layer 34 can be completely removed.For situation 1: in the process forming Gate Electrode Conductive connector 371; need to adopt the method for sputter deposition to form laying and diffusion impervious layer in gate via 361; Ar ion in sputter deposition method can bombard metal oxide layer 34 surface; remaining metal oxide layer 34 can continue to be lost to be removed completely again; metal gates 32 below can be protected simultaneously, make metal gates 32 below reduce damage.For situation 2: in the process forming Gate Electrode Conductive connector 371, although physical sputtering technology can damage metal gates 32, the method forming metal oxide layer in the present embodiment also reduces the damage to metal gates on the whole equally.
In the present embodiment, the formation method of conductive plunger has following advantages:
First interlayer dielectric layer 31 of etched portions thickness, can remove residue 33.The second interlayer dielectric layer 35 is formed after removing residue 33, first interlayer dielectric layer 31 and in the second interlayer dielectric layer 35, etching forms the drain electrode through hole 363 being positioned at source electrode through hole on source electrode 362 and be positioned in drain electrode time, etching forms source electrode through hole 362, the position of drain electrode through hole 363 can not be stopped by the residue on the first interlayer dielectric layer 31 surface, can make source electrode through hole 362, drain electrode through hole 363 through in the first interlayer dielectric layer 31 and the second interlayer dielectric layer 35, can make source electrode through hole 362, drain electrode through hole 363 bottom expose source electrode and drain electrode.The source conductive connector 372 that filled conductive layer is formed in this source electrode through hole 362, drain electrode through hole 363, Drain Electrodes Conductive connector 373 can with source electrode, draining is electrically connected, and then improves the performance of semiconductor device of follow-up formation.
Further, the first interlayer dielectric layer 31 of etched portions thickness, with before removing described residue 33, carries out oxidation processes to metal gates 32 surface, forms metal oxide layer 34 on the surface of metal gates 32.This metal oxide layer 34 can protect metal gates 32 injury-free in the process of the first interlayer dielectric layer 31 of etched portions thickness.Moreover when in the second interlayer dielectric layer 35, etching forms gate via 361, metal oxide layer 34 can also protect metal gates 32 to form reduction damage in the process of gate via 361 in etching.At this moment, metal oxide layer 34 also can be removed clean along band etching in above-mentioned two step etchings.If metal oxide layer 34 also has a small amount of residue in above-mentioned two step etchings; formed in the process of Gate Electrode Conductive connector 371; need to adopt the method for sputter deposition to form laying and diffusion impervious layer in gate via 361; Ar ion in sputter deposition method can bombard metal gates 32 surface, and remaining metal oxide layer 34 also can protect metal gates 32 to reduce damage in sputter deposition.And then, the performance of the semiconductor device of follow-up formation can be improved.
It should be noted that, after sputter deposition technique, metal oxide layer 34 is completely removed.
In the present embodiment, the method that metal gates is not formed metal oxide also belongs within protection scope of the present invention.
Form tungsten plug for the method applying the present embodiment, the failure density that application tungsten plug failure density checkout gear (CTW-CMP EBI Scan) detects suprabasil tungsten plug is 10ea/cm
2, that is, the substrate of 1 sq has 10 tungsten plugs lost efficacy.And in prior art, the failure density that application tungsten plug failure density checkout gear detects suprabasil tungsten plug is 305ea/cm
2, that is, the substrate of 1 sq has 305 tungsten plugs lost efficacy.Therefore, adopt the method for the present embodiment to substantially reduce the inefficacy of tungsten plug, and then substantially increase the performance of semiconductor device.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. a formation method for conductive plunger, is characterized in that, comprising:
The substrate being formed with source electrode and drain electrode is provided, form first interlayer dielectric layer with opening on the substrate, metal level is filled in described opening, described metal level also covers dielectric layer surface between described ground floor, be chemically mechanically polished to described first interlayer dielectric layer to described metal level and form metal gates, between described ground floor, dielectric layer surface has CMP residues;
First interlayer dielectric layer of etched portions thickness is to remove described residue;
The second interlayer dielectric layer is formed at remaining described first interlayer dielectric layer and described metal gates surface;
Formed in described second interlayer dielectric layer and described first interlayer dielectric layer and be positioned at the source electrode through hole on source electrode, the drain electrode through hole be positioned in drain electrode;
In described source electrode through hole, drain electrode through hole, filled conductive layer forms source conductive connector, Drain Electrodes Conductive connector.
2. the formation method of conductive plunger as claimed in claim 1, it is characterized in that, first interlayer dielectric layer of described etched portions thickness is with before the step removing described residue, after described metal level being chemically mechanically polished to the step of described first interlayer dielectric layer formation metal gates, also comprise the following steps:
Oxidation processes is carried out to described metal gates, forms metal oxide layer on described metal gates surface.
3. the formation method of conductive plunger as claimed in claim 2, it is characterized in that, the method for described metal gates being carried out to oxidation processes comprises: adopt and bombard described metal gates surface containing oxygen plasma, or,
Adopt oxygen and described metal gates surface that chemical reaction occurs.
4. the formation method of conductive plunger as claimed in claim 3, is characterized in that, described is oxygen plasma, carbon monoxide plasma, carbon dioxide plasma or ozone plasma containing oxygen plasma.
5. the formation method of conductive plunger as claimed in claim 4, it is characterized in that, described containing oxygen plasma be oxygen plasma time, formed by oxygen plasma, the flow velocity of described oxygen is 100sccm ~ 400sccm, bias power is 200W ~ 2000W, and the time of described oxidation processes is 5s ~ 20s.
6. the formation method of conductive plunger as claimed in claim 5, it is characterized in that, the thickness of described metal oxide layer is 5 dust ~ 15 dusts.
7. the formation method of conductive plunger as claimed in claim 1, it is characterized in that, the etching gas of the first interlayer dielectric layer of etched portions thickness is CF
4, CH
3one or more in F or CO, bias power is less than 500W.
8. the formation method of conductive plunger as claimed in claim 7, it is characterized in that, described segment thickness is 30 dust ~ 70 dusts.
9. the formation method of conductive plunger as claimed in claim 2, it is characterized in that, described metal gates is aluminium gate, and described metal oxide layer is alumina layer.
10. the formation method of conductive plunger as claimed in claim 1 or 2, is characterized in that, also comprise:
In described second interlayer dielectric layer, form gate via, described gate via is positioned on described metal gates;
In described gate via, filled conductive layer forms Gate Electrode Conductive connector.
The formation method of 11. conductive plungers as claimed in claim 1, is characterized in that, the material of described first interlayer dielectric layer is SiO
2.
The formation method of 12. conductive plungers as claimed in claim 1, is characterized in that, the material of described second interlayer dielectric layer is SiO
2.
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| CN111106158A (en) * | 2018-10-29 | 2020-05-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111106158B (en) * | 2018-10-29 | 2023-11-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112201619A (en) * | 2020-10-12 | 2021-01-08 | 合肥晶合集成电路股份有限公司 | Forming method of metal interconnection structure |
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Application publication date: 20150211 |