CN104979203A - MOS transistor and formation method of conductive plug - Google Patents
MOS transistor and formation method of conductive plug Download PDFInfo
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- CN104979203A CN104979203A CN201410135921.9A CN201410135921A CN104979203A CN 104979203 A CN104979203 A CN 104979203A CN 201410135921 A CN201410135921 A CN 201410135921A CN 104979203 A CN104979203 A CN 104979203A
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Abstract
The present invention provides an MOS transistor and a formation method of a conductive plug, wherein the formation method of the conductive plug comprises the steps of providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate; forming a hard mask layer on the dielectric layer, wherein an opening penetrating the thickness of the hard mask layer is arranged in the hard mask layer; by taking the hard mask layer as a mask, etching the dielectric layer along the opening to form a first through hole, wherein the bottom of the first through hole is equipped with a polymer layer; removing the polymer layer at the bottom of the first through hole; by taking the hard mask layer as the mask continuously, etching the dielectric layer continuously along the first through hole until the semiconductor substrate is exposed to form a second through hole; filling a conductive layer in the second through hole to form the conductive plug. According to the method of the present invention, the performance of the conductive plug can be improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of formation method of MOS transistor and conductive plunger.
Background technology
Along with the making of integrated circuit develops to very lagre scale integrated circuit (VLSIC), the current densities of IC interior is increasing, and the number of elements comprised also gets more and more, and this development makes crystal column surface that enough area cannot be provided to make required interconnection line.
In order to meet element reduce after interconnection line demand, the design of interconnecting metal layer becomes a kind of method that very large scale integration technology adopts usually.At present, the conducting between interconnecting metal layer is realized by conductive plunger.Wherein, the conducting between the semiconductor device such as the CMOS in interconnecting metal layer and substrate is realized by contact plunger (contact).
With reference to figure 1 ~ Fig. 5, the cross-sectional view of the forming process of gate contact connector of the prior art and source contact connector.Concrete forming process is as follows:
With reference to figure 1, provide Semiconductor substrate 100, described Semiconductor substrate 100 forms grid 101, in the Semiconductor substrate of described grid 101 both sides, form source electrode and drain electrode (not shown).Form dielectric layer 102 on a semiconductor substrate 100, described dielectric layer covers described grid 101, source electrode and drain electrode.Dielectric layer forms mask layer, described mask layer comprises amorphous carbon (Amorphous-Carbon) layer 103, silicon nitride layer 104 and patterned photoresist layer 105 3 layers, and described patterned photoresist layer 105 is for defining gate contact hole, the distribution of source contact openings and size.
Then, with reference to figure 2, be mask etch nitride silicon layer 104 and amorphous carbon layer 103 successively with described patterned photoresist layer 105, by the Graphic transitions on photoresist layer 105 on silicon nitride layer 104 and amorphous carbon layer 103, form the first opening 106 and the second opening 107 running through silicon nitride layer 104 and amorphous carbon layer 103, wherein the first opening 106 is corresponding with the position of grid, and the second opening 107 is corresponding with the position of source electrode.
Then, in conjunction with referring to figs. 2 to Fig. 4, after the first opening 106 and the second opening 107 are formed, patterned photoresist layer 105 has been consumed.Then with silicon nitride layer 104 and amorphous carbon layer 103 for mask, adopt the method etch media layer 102 of anisotropic dry etch along the first opening 106 and the second opening 107, form gate contact hole 108 and source contact openings 109 respectively.
Then, with reference to figure 4 and Fig. 5, in gate contact hole 108 and source contact openings 109, fill tungsten metal, form gate contact connector 112 and source contact connector 113.
The source contact connector adopting the method for prior art to be formed cannot conducting.
Summary of the invention
The problem to be solved in the present invention is that the method formation source contact connector of employing prior art cannot conducting.
The invention provides a kind of formation method of MOS transistor, described method comprises:
Semiconductor substrate is provided, forms grid on the semiconductor substrate, in the Semiconductor substrate of described grid both sides, form source electrode and drain electrode;
Form dielectric layer on the semiconductor substrate, described dielectric layer covers described grid, source electrode and drain electrode;
Described dielectric layer forms hard mask layer, and have the first opening and the second opening that run through its thickness in described hard mask layer, described first opening is corresponding with described gate location, and described second opening is corresponding with described source electrode or drain locations;
With described hard mask layer for mask, described dielectric layer is etched along described first opening and the second opening, the contact hole etching the formation of described dielectric layer along described first opening is gate contact hole, etching along described second opening the contact hole that described dielectric layer formed is the first source contact openings or the first drain contact hole, and the bottom that the bottom of described gate contact hole and the first source contact openings has polymeric layer or described gate contact hole and the first drain contact hole has polymeric layer;
Remove described polymeric layer;
Continue with described hard mask layer for mask, continuing the described dielectric layer of etching to exposing described source electrode or drain electrode along the first source contact openings or the first drain contact hole, forming the second source contact openings or the second drain contact hole;
In described gate contact hole, fill full conductive layer form gate contact connector, in described second source contact openings, the full conductive layer of filling forms source contact connector or in described second drain contact hole, fills full conductive layer formation drain contact connector.
Optionally, described hard mask layer is single layer structure or laminated construction, and when described hard mask is single layer structure, the material of described hard mask layer is boron nitride, silicon nitride or titanium nitride; When described hard mask layer is laminated construction, described hard mask layer is the two-layer arbitrarily or three-decker in boron nitride layer, silicon nitride layer or titanium nitride layer.
Optionally, described dielectric layer forms hard mask layer, the method in described hard mask layer with the first opening and the second opening running through its thickness comprises:
Described dielectric layer forms hard mask layer;
Described hard mask layer forms the first patterned photoresist layer;
With described first patterned photoresist layer for mask, etch described hard mask layer, there is in described hard mask layer the first opening and the second opening that run through its thickness.
Optionally, before described hard mask layer forms the first graphical photoresist layer, after described dielectric layer forms hard mask layer, also comprise the following steps:
Described hard mask layer is formed advanced figure rete;
Described advanced figure rete forms light-absorption layer.
Optionally, before the step of described first patterned photoresist layer for hard mask layer described in mask etching, after described hard mask layer is formed the photoresist layer of second graphical, also to comprise with described first patterned photoresist layer for mask, etch described advanced figure rete and described light-absorption layer.
Optionally, after described figure rete forms the step of light-absorption layer, be also included on described light-absorption layer before described hard mask layer is formed the step of the first patterned photoresist layer and form bottom anti-reflection layer.
Optionally, before the step being figure rete advanced described in mask etching and light-absorption layer with described first patterned photoresist layer, described hard mask layer is formed after the first patterned photoresist layer, the step that also to comprise with described first patterned photoresist layer be bottom anti-reflection layer described in mask etching.
Optionally, the material of described advanced figure rete is amorphous carbon, and the material of described light-absorption layer is silicon oxynitride, carbon doped silicon oxide or silicon nitride.
Optionally, the method removing described polymeric layer comprises: pass into removal gas to gate contact hole and the first source contact openings or gate contact hole and the first drain contact hole, described removal gas comprise in oxygen or nitrogen one or both.
Compared with prior art, technical scheme of the present invention has the following advantages:
Because the removal gas and hard mask layer of removing the first source contact openings bottom polymeric have very high Selection radio, therefore, remove in the process of the first source contact openings bottom polymeric, hard mask layer is damaged hardly.Like this, can continue to take hard mask layer as mask, the described dielectric layer of etching is continued to exposing described source electrode along the first source contact openings, form better second source contact openings of pattern, the source contact connector that the conductive layer of filling in described second source contact openings is formed can realize the electrical connection with source electrode, thus improves the performance of the MOS transistor of follow-up formation.
For solving the problem, present invention also offers a kind of formation method of conductive plunger, described method comprises:
Semiconductor base is provided;
Described semiconductor base forms dielectric layer;
Described dielectric layer forms hard mask layer, there is in described hard mask layer the opening running through its thickness;
With described hard mask layer for mask, along opening etch media layer, form the first through hole, the bottom of described first through hole has polymeric layer;
Remove the polymeric layer of described first via bottoms;
Continue with described hard mask layer for mask, continuing the described dielectric layer of etching to exposing semiconductor base along the first through hole, forming the second through hole;
In described second through hole, fill full conductive layer, form conductive plunger.
Optionally, described hard mask layer is single layer structure or laminated construction, and when described hard mask is single layer structure, the material of described hard mask layer is boron nitride, silicon nitride or titanium nitride; When described hard mask layer is laminated construction, described hard mask layer is the two-layer arbitrarily or three-decker in boron nitride layer, silicon nitride layer or titanium nitride layer.
Optionally, described dielectric layer forms hard mask layer, the method in described hard mask layer with the opening running through its thickness comprises:
Described dielectric layer forms hard mask layer;
Described hard mask layer is formed the photoresist layer of second graphical;
With the photoresist layer of described second graphical for mask, etch described hard mask layer, formed in described hard mask layer and there is the opening running through its thickness.
Optionally, before described hard mask layer is formed the photoresist layer of second graphical, after described dielectric layer forms hard mask layer, also comprise the following steps:
Described hard mask layer is formed advanced figure rete;
Described advanced figure rete forms light-absorption layer.
Optionally, before the step of the photoresist layer of described second graphical for hard mask layer described in mask etching, after described hard mask layer is formed the photoresist layer of second graphical, also comprise with the photoresist layer of described second graphical for figure rete advanced described in mask etching and light-absorption layer.
Optionally, after described advanced figure rete forms the step of light-absorption layer, be also included in before described hard mask layer is formed the photoresist layer of second graphical on described light-absorption layer and form bottom anti-reflection layer.
Optionally, before the step being figure rete advanced described in mask etching and light-absorption layer with the photoresist layer of described second graphical, after described hard mask layer is formed the photoresist layer of second graphical, the step that also to comprise with described patterned photoresist layer be bottom anti-reflection layer described in mask etching.
Optionally, the material of described advanced figure rete is amorphous carbon.
Optionally, the material of described light-absorption layer is silicon oxynitride, carbon doped silicon oxide or silicon nitride.
Optionally, the method removing the polymeric layer of described first via bottoms comprises: in the first through hole, pass into removal gas, described removal gas comprise in oxygen or nitrogen one or both.
Compared with prior art, technical scheme of the present invention has the following advantages:
Because the removal gas and hard mask layer of removing the first via bottoms polymer have very high Selection radio, therefore, remove in the process of the first via bottoms polymer, hard mask layer is damaged hardly, like this, can continue to take hard mask layer as mask, the described dielectric layer of etching is continued to exposing described semiconductor base along the first through hole, form better second through hole of pattern, the conductive plunger that the metal level of filling in described second through hole is formed can realize the electrical connection with conductive layer in semiconductor base, thus improve the performance of conductive plunger, and then improve the performance of semiconductor device of follow-up formation.
Accompanying drawing explanation
Fig. 1 ~ Fig. 5 is the cross-sectional view of the forming process of gate contact connector of the prior art and source contact connector;
Fig. 6 ~ Figure 12 is the cross-sectional view of the forming process of gate contact connector in the present invention one specific embodiment and source contact connector;
Figure 13 ~ Figure 17 is the cross-sectional view of the forming process of conductive plunger in another specific embodiment of the present invention.
Embodiment
Through finding and analyzing, the source contact connector adopting the method for prior art to be formed cannot the reason of conducting as follows:
Referring to figs. 2 and 3, with silicon nitride layer 104 and amorphous carbon layer 103 for mask, along the first opening 106 and the second opening 107 etch media layer 102, formed in the process of gate contact hole 108 and source contact openings 109, etching gas can form polymeric layer in the bottom of the bottom in gate contact hole 108 and sidewall, source contact openings 109 and sidewall.The polymeric layer that sidewall is formed can ensure that each contact hole sidewall is injury-free in etching process, and the polymeric layer that specific thicknesses is formed on bottom can make the etching of etching gas stopping to each contact hole, to prevent from forming over etching to the device on substrate.Be specially, by controlling same etching condition, form the polymeric layer 110 of specific thicknesses bottom gate contact hole 108, this polymeric layer 110 can stop the etching to gate contact hole.Meanwhile, form the polymeric layer 111 of specific thicknesses bottom source contact openings 109, this polymeric layer 111 can stop the etching to source contact openings.But gate contact hole 108 is identical with the width dimensions of source contact openings 109, and depth dimensions differs greatly.Therefore, control same etching condition, the polymeric layer simultaneously namely forming suitable thickness in the bottom in gate contact hole 108 at the top of grid 101, to stop the etching to gate contact hole 108, namely to form the polymeric layer of suitable thickness in the bottom of source contact openings 109 to stop the etching to source contact openings on source electrode, is almost difficult to realize.
Therefore, in prior art, with silicon nitride layer 104 and amorphous carbon layer 103 for mask, when adopting the method etch media layer 102 of anisotropic dry etch along the first opening 106 and the second opening 107, often occur following situations: the bottom in the gate contact hole 108 of formation has polymeric layer 110, this polymeric layer 110 makes the top etching in gate contact hole 108 just in time being stopped to grid 101.Because the degree of depth of source contact openings 109 is much larger than the degree of depth in gate contact hole 108, under same etching condition, bottom source contact openings 109 formed polymeric layer 111 make source contact openings too early stop in dielectric layer 102, dielectric layer 102 is not worn to expose source electrode quarter.
Then, with reference to figure 4 and Fig. 5, the method of wet etching is adopted to be removed by the polymeric layer in gate contact hole 108 and source contact openings 109 clean, full metal level is filled in gate contact hole 108 and source contact openings 109, form gate contact connector 112 and source contact connector 113, metal level in source contact connector 113 does not have and source contact, and therefore, the source contact connector 113 that prior art is formed can not realize conducting.
For this reason, through research, when find source contact openings do not have wear dielectric layer quarter time, there is again new problem while adopting following method to solve the problem, specific as follows:
With reference to figure 2 ~ Fig. 4, with silicon nitride layer 104 and amorphous carbon layer 103 for mask, the method etch media layer 102 of anisotropic dry etch is adopted along the first opening 106 and the second opening 107, polymeric layer 110 is formed in the bottom in gate contact hole 108, after polymeric layer 111 is formed on the bottom of source contact openings 109, oxygen is adopted to remove the polymeric layer 110 of segment thickness and the polymeric layer 111 of segment thickness, to make etching gas with silicon nitride layer 104 and amorphous carbon layer 103 for mask, the remaining dielectric layer 102 of etching is continued along source contact openings 109, expose to make the source electrode bottom dielectric layer 102.But the source contact connector formed in this approach still cannot conducting.Reason is as follows: in actual process operation, the consumption amorphous carbon layer 103 that oxygen is also a large amount of while removing the polymeric layer bottom each contact hole, when the polymeric layer bottom each contact hole is removed to satisfactory thickness, the thickness of amorphous carbon layer 103 cannot meet the requirement of mask plate, thus make to continue cannot carry out the etching of dielectric layer 102 along source contact openings 109, source electrode is not still exposed in the bottom of source contact openings.
Embodiment one
The invention provides a kind of formation method of MOS transistor for this reason, adopt method of the present invention can improve the performance of gate contact connector, source contact connector and drain contact connector in MOS transistor, thus improve the performance of MOS transistor further.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to figure 6, provide Semiconductor substrate 200, form grid 201 on the semiconductor substrate, in the Semiconductor substrate of described grid both sides, form source electrode and drain electrode (not shown).
In the present embodiment, Semiconductor substrate 200 is silicon substrates.In other embodiments, Semiconductor substrate also can be germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or its laminated construction, or diamond substrate, or well known to a person skilled in the art other semiconductive material substrate.
The material of grid 201 is polysilicon.Formed the method for grid 201 be those skilled in the art know technology, do not repeat them here.
In the Semiconductor substrate 200 of the both sides of grid 201, carry out ion implantation, form source electrode and drain electrode.
Then, continue with reference to figure 6, form etching stop layer 202 on Semiconductor substrate 200 surface and grid 201 surface.
In the present embodiment, the material of etching stop layer 202 is silicon nitride.Acting as of etching stop layer 202: in subsequent process steps; when dielectric layer 203 is etched, can stop on etching stop layer 202, prevent from carrying out over etching to semiconductor device; such as, etching stop layer 202 can protect the top of grid 201, source electrode and drain electrode not by over etching.
In other embodiments, do not form etching stop layer 202 at semiconductor substrate surface and gate surface, belong to protection scope of the present invention yet.
Then, continue with reference to figure 6, form dielectric layer 203 on the semiconductor substrate, described dielectric layer 203 covers described grid 201, source electrode and drain electrode.
In the present embodiment, dielectric layer 203 is single layer structure, and material is silica.In other embodiments, the material of the dielectric layer of single layer structure also can be low k dielectric, as the SiO of low k
2, SiOF, SiCOH, SiO, SiCO or SiCON etc., can also be ultra low k dielectric materials, as black diamond etc.In other embodiments, dielectric layer can be the laminated construction of above-mentioned random layer composition.
In the present embodiment, the formation method of dielectric layer 203 is deposition.Be specifically as follows high-density plasma (High Density Plasma, HDP) chemical vapour deposition (CVD) or high depth ratio fills out ditch technique (HighAspect Ratio Process, HARP).Adopt above-mentioned two kinds of method filling capacities comparatively strong, the isolation effect of the dielectric layer of formation is relatively good.Certainly, the formation method of dielectric layer also can be that other depositing operations well known to those skilled in the art also belong to protection scope of the present invention.
Then, with reference to figure 8 and Fig. 9, dielectric layer 203 is formed hard mask layer 204, there is in described hard mask layer 204 the first opening 213 and the second opening 214 running through its thickness, described first opening 213 is corresponding with described grid 201 position, and described second opening 214 is corresponding with the position of described source electrode.
Concrete forming process is as follows:
In the present embodiment, with reference to figure 6, described hard mask layer 204 is single layer structure, is titanium nitride.In other embodiments, the material of hard mask layer 204 is boron nitride, silicon nitride or titanium nitride.In other embodiments, hard mask layer also can be laminated construction, and described hard mask layer is the two-layer arbitrarily or three-decker in boron nitride layer, silicon nitride layer or titanium nitride layer.
In the present embodiment, dielectric layer 203 forms the method for hard mask layer 204 for deposition.Be specially physical vapour deposition (PVD), technique is as follows:
First the mist of nitrogen and argon gas is passed into reaction chamber, wherein the flow of nitrogen is 150 ~ 250sccm, and the flow of argon gas is 100 ~ 200sccm, and reaction chamber pressure is for being greater than 1.1Torr, reaction chamber temperature is 250 ~ 400 DEG C, and the reaction time is 30 ~ 80s.
In the process forming hard mask layer 204, the pressure of reaction chamber is greater than 1.1Torr, the pattern of the hard mask layer 204 of generation can be changed, changed into the needle-like of separation by continuous print graininess before, thus release the stress of the hard mask layer 204 of follow-up formation.Moreover the heating process forming hard mask layer is equivalent to anneal to the hard mask layer of follow-up formation, releases stress further.Therefore, the stress of the hard mask layer adopting the method for the present embodiment to be formed is low, the flexibility of each layer under hard mask layer can be made to reduce, thus improve the performance of the device of follow-up formation.
In the present embodiment, the thickness of hard mask layer 204 is 100 ~ 300 dusts.If hard mask layer 204 is too thick, improve process costs on the one hand; On the other hand, in subsequent technique, after forming each contact hole, too thick hard mask layer can improve the depth-to-width ratio of each contact hole, thus there is space conductive plunger inside conductive layer being inserted formed in each contact hole.If the thickness of hard mask layer 204 is too thin, in subsequent technique, being formed at etch media layer in the process of each contact hole, not having protective effect to not needing the dielectric layer etched.
Then, continue with reference to figure 6, hard mask layer 204 is formed advanced figure rete (Advanced Patterning Film from the bottom to top successively, APF) 205, light-absorption layer 206, bottom anti-reflection layer (BottomAnti-reflection Coating, BARC) 207 and there is the first patterned photoresist layer 208.The first figure in photoresist layer 208 is used for defining the first opening 213(in hard mask layer 204 with reference to figure 8), the second opening 214(is with reference to figure 8) size and distribution.
The material of advanced figure rete 205 is amorphous carbon layer.The method forming advanced figure rete 205 is chemical vapour deposition (CVD).In the present embodiment, the thickness of advanced figure rete 205 is 1000 ~ 2500 dusts.
Light-absorption layer 206 on advanced figure rete 205 can be used for absorbing the light be irradiated on it, light-absorption layer can improve the depth-width ratio of the first opening 213 and the second opening 214 top and bottom formed in the first figure in advanced graphic films layer, hard mask layer, that is, the sidewall of the first opening 213 and the second opening 214 formed in hard mask layer can be made to keep vertical.The extinction effect of light-absorption layer 206 is better, the first opening 213 formed in hard mask layer 204 and the sidewalls orthogonal rate of the second opening 214 higher.
Wherein, light-absorption layer 206 can be represented by the thickness of refractive index (n), extinction coefficient (k) and light-absorption layer 206 uptake of light.And it is relevant with the material that light-absorption layer 206 is selected to n, k value of light-absorption layer 206.In a particular embodiment, light-absorption layer 206 can select antireflecting inorganic layer, as dielectric anti-reflective layer (Dielectric Anti-Reflection Coating, DARC).In a particular embodiment, dielectric anti-reflective layer can use plasma enhanced chemical vapor deposition (Plasma EnhancedChemical Vapor Deposition, PECVD) mode to generate.Described dielectric anti-reflective layer material comprises containing silicon oxynitride (SiON), carbon doped silicon oxide (SiCO) or silicon nitride (SiN).
In a particular embodiment, by selecting the material of suitable light-absorption layer 206, make the scope of the refractive index n values of light-absorption layer 206 be 1.5 ~ 2.5, the scope of extinction coefficient k value is 0.3 ~ 2, can reach the best absorption completely to light.And the thickness to light-absorption layer 206, thickness is larger, then the uptake of light-absorption layer 206 to light is larger.But for having the light-absorption layer of particular range n, k value, the thickness of light-absorption layer 206 can determine suitable scope according to the chemical simulation of light-absorption layer 206 selected materials.In the present embodiment, the thickness range of light-absorption layer 206 is 50 ~ 300 dusts.
In a particular embodiment, the selection of light-absorption layer is not limited to dielectric anti-reflective layer, is also feasible for other other materials that can reach light-absorbing effect same.
In the present embodiment, the material of the bottom anti-reflection layer 207 that light-absorption layer 206 is formed is organic material.In a particular embodiment, described organic material is in a liquid state, the method forming bottom anti-reflection layer 207 can be: utilize the method such as spin coating or spraying to apply organic material layer on light-absorption layer 206, then carries out soft baking to organic material layer and forms bottom anti-reflection layer 207.In the present embodiment, the bottom anti-reflection layer 207 of organic material has good mobility, and the bottom anti-reflection layer 207 therefore formed has comparatively uniform surface.In addition, have the first patterned photoresist layer 208 in follow-up formation and carry out in the process exposed, bottom anti-reflection layer 207 plays antireflecting effect, guarantees that first of follow-up formation the patterned photoresist layer 208 has higher resolution further.
The patterned photoresist layer 208 of the first patterned photoresist layer 208, first that bottom anti-reflection layer 207 is formed defines the position of the first opening 213 and the second opening 214 on hard mask layer.The method forming the first patterned photoresist layer is known to those skilled in the art, does not repeat them here.Then, there is the first patterned photoresist layer 208 for mask, method etching bottom anti-reflecting layer 207, light-absorption layer 206, advanced figure rete 205 and the hard mask layer 204 successively of using plasma dry etching, forms the first opening 213 and the second opening 214 running through its thickness in hard mask layer 204.
In the present embodiment, because the characteristic size of semiconductor device is more and more less, the thickness of photoresist layer is more and more thinner, directly with the photoresist layer being formed with the first figure for mask hard mask layer 204 is etched time, photoresist layer was easily completely removed before the first opening 213 and the second opening 214 are formed, in the present embodiment, first can define the first figure in photoresist layer 208, in etching afterwards, the first figure is transferred to bottom anti-reflection layer 207, light-absorption layer 206 and advanced figure rete 205, after photoresist layer 208 and bottom anti-reflection layer 207 have been consumed, mask is made by light-absorption layer 206, after light-absorption layer 206 has been consumed, mask is made by advanced figure rete 205.
In other embodiments, on light-absorption layer and have between the first patterned photoresist layer and do not form bottom anti-reflection layer, also belong to protection scope of the present invention, the poor accuracy just forming the first opening and the second opening figure on hard mask layer is a little.
In other embodiments, do not form advanced figure rete and light-absorption layer, also belong to protection scope of the present invention between hard mask layer and bottom anti-reflection layer, the poor accuracy just forming the first opening and the second opening figure on hard mask layer is a little.
In other embodiments, hard mask layer is only formed there is the first patterned photoresist layer, also belong to protection scope of the present invention, a little in the poor accuracy forming the first opening and the second opening figure on hard mask layer like this.
Then, in conjunction with reference to figure 8 and Fig. 9, with described hard mask layer 204 for mask, described dielectric layer 203 is etched along described first opening 213 and the second opening 214, the contact hole etching the formation of described dielectric layer 203 along the first opening 213 is gate contact hole 215, the contact hole etching the formation of described dielectric layer 203 along the second opening 214 is the first source contact openings 216, and described gate contact hole 215 and the first source contact openings 216 have polymeric layer.
The method of etch media layer 203 is plasma dry etch.Specific as follows: etching air pressure is 10 ~ 1000mtorr, radio-frequency power is 1000 ~ 3000W, and etching gas is C
4f
6, C
10f
8in one or both, carrier gas is argon gas and oxygen.Wherein, the flow of etching gas is 10 ~ 50sccm, and the flow of argon gas is 200 ~ 1500sccm, and the flow of oxygen is 10 ~ 50sccm.
Acting as of argon gas ensures etching direction.
Formed in the process of each contact hole at etch media layer; as previously mentioned; all can form polymeric layer at the sidewall of each contact hole and bottom, lateral wall polymer layer can protect the sidewall of contact hole not by over etching, thus ensures the sidewall profile of the contact hole of follow-up formation.When the etching of each contact hole reaches desired depth, certain thickness bottom polymeric layer is conducive to the etching stopping to dielectric layer.But blocked up bottom polymeric layer can make to stop too early the etching of dielectric layer, that is, make the degree of depth of each contact hole not reach desired depth, just stopped.The main carbon containing of composition of above-mentioned lateral wall polymer layer and bottom polymeric layer, oxygen can be formed easily by carbon dioxide that vacuum pump is taken away with the carbon reaction in lateral wall polymer layer and bottom polymeric layer.Thus control the thickness balance of lateral wall polymer and bottom polymeric, to make the technique of etch media layer carry out smoothly, and, ensure that the sidewall profile of each contact hole of follow-up formation is good.
In other embodiments, etching gas also comprises CF
4.CF
4the flow of gas is 10 ~ 1000sccm.Relative to C
4f
6, C
10f
8etching gas, CF
4the etching performance of etching gas is more powerful, and the polymeric layer of formation is less.
In the present embodiment, to dielectric layer 203 after etching after a while, form gate contact hole 215 and the first source contact openings 216.The bottom in gate contact hole 215 has polymeric layer 217, and this polymeric layer 217 makes etching gas just in time stop at the top of grid 201 to the etching in gate contact hole 215.Bottom first source contact openings 216, there is polymeric layer 218.Because the degree of depth of source contact openings that finally formed is much larger than the degree of depth in gate contact hole 215, under same etching condition, the polymeric layer be difficult in control first source contact openings 216 makes etching gas just in time stop exposing source electrode place the etching of dielectric layer.Therefore, under same etching condition, the polymeric layer 218 bottom the first source contact openings 216 makes the etching of etching gas to dielectric layer 203 always stop too early.That is, dielectric layer 203 is not worn along the second opening 214 in hard mask layer 204 quarter by this etching gas, and do not expose etching stop layer 202 bottom the first source contact openings 216, bottom remains dielectric layer 203.
Then, with reference to Figure 10, the polymeric layer in gate contact hole 215 and the first source contact openings 216 is removed.
In the present embodiment, the method removing polymeric layer is pass into removal gas in gate contact hole 215 and the first source contact openings 216.In the present embodiment, the actual conditions adopting removal gas to remove polymeric layer is: removal pressure is 20 ~ 50torr, and removal power is 400 ~ 1000W, and removal gas is oxygen, and the flow of oxygen is 10 ~ 1000sccm.
Polymeric layer mainly become carbon, the carbon of oxygen and polymeric layer reacts and generates easily by the carbon dioxide outside vacuum pump sucking-off cavity, therefore, oxygen in the process of etch media layer, can make the thickness of polymeric layer reduce even remove.In the present embodiment, if the flow of removal pressure, removal power, removal gas is excessive, the thickness easily destroying lateral wall polymer layer and bottom polymeric layer balances, and such as, the thickness of easy reduction lateral wall polymer, the pattern of the contact hole of follow-up formation is bad.If the flow of removal pressure, removal power, removal gas is too small, also easily destroy the thickness balance of lateral wall polymer layer and bottom polymeric layer, such as, make bottom polymeric accumulation too much, the easy etching stopped dielectric layer.
In other embodiment, remove the mist that gas can also be nitrogen and argon gas, wherein the flow of nitrogen is 10 ~ 1000sccm, and the flow of argon gas is 10 ~ 1000sccm.
In other embodiment, removing gas can also be nitrogen.Wherein the flow of nitrogen is 100 ~ 1000sccm.
It should be noted that; in the present embodiment; removing gas does not make the polymer bottom the first source contact openings remove completely, leaves very thin polymeric layer in the first source contact openings, as long as etching gas can be made to continue etch media layer belong to protection scope of the present invention yet.
In the present embodiment, remove in the process of the polymer in gate contact hole 215 and the first source contact openings 216, remove gas high with the etching selection ratio of hard mask layer 204, therefore, hard mask layer 204 damaged hardly in the atmosphere of removal gas.Like this, during remaining media layer 203 bottom follow-up continuation etching first source contact openings, hard mask layer 204 still has accurate second opening figure, therefore, when etching the remaining media layer 203 bottom the first source contact openings 216, still can with hard mask layer 204 for mask.
Then, with reference to Figure 11, continue with described hard mask layer 204 for mask, continuing the described dielectric layer 203 of etching to exposing described etching stop layer 202 along the first source contact openings 216, forming the second source contact openings 219.
In the present embodiment, continue the described dielectric layer 203 of etching along the first source contact openings 216 identical with the lithographic method forming the first source contact openings 216 to the lithographic method exposing described etching stop layer 202.The bottom of the second source contact openings 219 formed exposes etching stop layer 202.
In other embodiments, if do not form etching stop layer on the surface of the surface of Semiconductor substrate 200 or grid 201, then, the bottom of the second source contact openings 219 exposes source electrode.
It should be noted that, the described dielectric layer 203 of etching is continued in the process exposing etching stop layer 202 along the first source contact openings 216, if still blocked up polymeric layer can be formed in the bottom of the first source contact openings 216, temporarily stop in reaction chamber and pass into etching gas, afterwards, in reaction chamber, removal gas is passed into remove the polymeric layer formed new bottom the first source contact openings 216.Remove in the process of new polymeric layer, hard mask layer 204 does not also almost damage.Therefore, can continue with described hard mask layer 204 as mask, the remaining dielectric layer 203 of etching is continued along the first source contact openings 216, the process of the dielectric layer bottom repeated removal first source contact openings bottom polymeric, continuation etching first source contact openings, until form the second source contact openings 219 exposing described etching stop layer 202.In above process, the pattern of hard mask layer 204 is still intact, therefore, can realize the formation of the second source contact openings 219, and the pattern of the second source contact openings 219 formed is relatively good.
Need to go on to say, because the bottom in gate contact hole 215 has exposed etching stop layer 202.Therefore, continue the described dielectric layer 203 of etching in the process exposing described etching stop layer 202 along the first source contact openings 216, the degree of depth in gate contact hole 215 is constant.
Further, need again to go on to say, in the present embodiment, for advanced figure rete 205, the thickness of hard mask layer 204 only has 100 ~ 300 dusts, and also can not damaged in the removal technique of polymeric layer.Therefore, very thick hard mask layer is not needed just can to realize the good pattern of gate contact hole and source contact openings.
After forming the second source contact openings, the method for wet etching is adopted to remove the polymeric layer of the final formation in gate contact hole and the second source contact openings.
In the present embodiment, after described wet etching, hard mask layer 204 can be removed, remove method that the method for hard mask layer 204 can be dry etching or remove for the method for wet etching.
If adopt the method for dry etching to remove hard mask layer 204, etching gas is chlorine, and the flow of chlorine is 20 ~ 200sccm, and carrier gas is one or both in nitrogen, methane.Wherein the acting as of nitrogen: protect the nitride layer on substrate injury-free in the process of etching.Acting as of methane: protect the oxide skin(coating) on substrate injury-free in the process of etching.
If adopt the method for wet etching to remove hard mask layer 204, then wet etching agent is the mixed solution of hydrogen peroxide and hydrochloric acid or the mixed solution for hydrogen peroxide and sulfuric acid.
Follow-up in gate contact hole 215 and the second source contact openings 219 during filled conductive layer, the removal of hard mask can reduce the depth-to-width ratio of each contact hole, thus reduces the air-gap that is filled in conductive layer, to improve the performance of each contact plunger of follow-up formation.
In other embodiment, after forming gate contact hole and the second source contact openings, because the thickness of hard mask layer is less, less on the padding impact in each contact hole, also can remove hard mask layer, also belong to protection scope of the present invention.
Then, with reference to Figure 12, in described gate contact hole 215, fill full conductive layer form gate contact connector 220, in described second source contact openings 219, fill full conductive layer form source contact connector 221.
In the present embodiment, described conductive layer is copper or tungsten.
The method forming gate contact connector, does not repeat them here for those skilled in the art know technology with the concrete grammar forming source contact connector.
It should be noted that, in the present embodiment, the formation method of drain contact connector is identical with the formation method of source contact connector, and is formed with source contact connector simultaneously.
Therefore, in the present embodiment, because the removal gas and hard mask layer of removing the first source contact openings bottom polymeric have very high Selection radio, therefore, remove in the process of the first source contact openings bottom polymeric, hard mask layer is damaged hardly, like this, can continue to take hard mask layer as mask, the described dielectric layer of etching is continued to exposing described etching stop layer along the first source contact openings, form better second source contact openings of pattern, the source contact connector that the conductive layer of filling in described second source contact openings is formed can realize the electrical connection with source electrode, thus improve the performance of the MOS transistor of follow-up formation.
Embodiment two
With reference to Figure 13 ~ Figure 17, present invention also offers a kind of formation method of conductive plunger, comprising:
With reference to Figure 13, semiconductor base 300 is provided, described semiconductor base 300 forms dielectric layer 304.
Described semiconductor base 300 comprises: the semiconductor substrate layer 301 being formed with the semiconductor element (not shown) such as transistor, be formed at the metal level 302 in Semiconductor substrate, wherein said metal level 302 realizes the electrical connection with other devices for the conductive plunger formed by the present embodiment.Particularly, the material of metal level is copper or aluminium.Semiconductor base 300 also comprises the separator 303 flushed with metal level 302.
In other embodiments, described semiconductor base may also be only the basalis being formed with the semiconductor elements such as transistor.
Material and the concrete formation method of dielectric layer 304 please refer to an embodiment.
Continue, with reference to Figure 14, described dielectric layer 304 to form hard mask layer 305, there is in described hard mask layer 305 opening 310 running through its thickness.
Concrete formation method is as follows:
Continue, with reference to Figure 13, first to adopt the method for deposition to form hard mask layer 305 on dielectric layer 304.Specifically please refer to an embodiment.
Then, hard mask layer 305 is formed from the bottom to top successively advanced figure rete 306, light-absorption layer 307, bottom anti-reflection layer 308 and there is the photoresist layer 309 of second graphical.Second graph in photoresist layer 309 is used for the size of the opening 310 defined in hard mask layer 305 and distribution.
Then, to have photoresist layer 309 etching bottom anti-reflecting layer 308, light-absorption layer 307 and advanced figure rete 306 and the hard mask layer 305 successively of second graphical.Hard mask layer 305 is formed opening 310.
Concrete technology please refer to an embodiment.
Refer to figs. 14 and 15, with described hard mask layer 305 for mask, along opening 310 etch media layer 304, form the first through hole 311, the bottom of described first through hole 311 has polymeric layer 312.
Perfect condition situation: etching gas can form polymeric layer in the bottom of the through hole of follow-up formation and sidewall simultaneously.The polymeric layer that sidewall is formed can ensure that the through-hole side wall of follow-up formation is injury-free in etching process, the polymeric layer that specific thicknesses is formed on bottom can make the etching of etching gas stopping to through hole, and the metal level exposed to prevent via bottoms forms over etching.But the thickness how controlling lateral wall polymer layer in same through hole is injury-free with the sidewall of just right this through hole of protection, the thickness simultaneously controlling bottom polymeric layer stops etching on the metal layer with just right this through hole that makes, and is very difficult.
Therefore; in prior art; can there is following situations in etching gas: during along opening 310 etch media layer 304 in the process of etch media layer 304; following situations is difficult to realize: the thickness controlling lateral wall polymer layer in same through hole is injury-free with the sidewall of just right this through hole of protection; the thickness simultaneously controlling bottom polymeric layer stops etching on the metal layer with just right this through hole that makes; therefore; in prior art; dielectric layer 304 can cannot be continued because via bottoms polymeric layer is too thick to carve further wear, just define the first through hole 311.That is, metal level is not exposed in the bottom of the first through hole 311, and the bottom of the first through hole 311 is remaining dielectric layers 304.
In the present embodiment, the bottom of the first through hole 311 has blocked up polymeric layer 312.
Specifically please refer to the description to the first source contact openings in an embodiment.
In conjunction with reference to Figure 15 and Figure 16, remove the polymeric layer 312 bottom described first through hole 311.
Employing removal gas removes the polymeric layer 312 bottom the first through hole 311.Described removal gas is oxygen or nitrogen, specifically please refer to an embodiment.
It should be noted that, when removing the polymeric layer 312 of described first through hole 311 inner bottom part, hard mask layer 305 damaged hardly.
With reference to Figure 16, continue with described hard mask layer 305 for mask, continuing the described dielectric layer 304 of etching to exposing semiconductor base 300 along the first through hole 311, forming the second through hole 313.
Specifically please refer to an embodiment.
After forming the second through hole 313, the method for wet etching is adopted to remove the polymeric layer of the final formation in the second through hole 313.
With reference to Figure 17, in described second through hole 313, fill full conductive layer, form conductive plunger 314.
Specifically please refer to an embodiment.
Therefore, in the present embodiment, the etching gas of the first through hole is formed and hard mask layer has very high Selection radio due to etch media layer, therefore, remove in the process of the first via bottoms polymer, hard mask layer is damaged hardly, like this, can continue to take hard mask layer as mask, the described dielectric layer of etching is continued to exposing described semiconductor base along the first through hole, form better second through hole of pattern, the conductive plunger that the metal level of filling in described second through hole is formed can realize the electrical connection with metal level in semiconductor base, thus improve the performance of conductive plunger, and then improve the performance of semiconductor device of follow-up formation.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (19)
1. a formation method for MOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided, forms grid on the semiconductor substrate, in the Semiconductor substrate of described grid both sides, form source electrode and drain electrode;
Form dielectric layer on the semiconductor substrate, described dielectric layer covers described grid, source electrode and drain electrode;
Described dielectric layer forms hard mask layer, and have the first opening and the second opening that run through its thickness in described hard mask layer, described first opening is corresponding with described gate location, and described second opening is corresponding with described source electrode or drain locations;
With described hard mask layer for mask, described dielectric layer is etched along described first opening and the second opening, the contact hole etching the formation of described dielectric layer along described first opening is gate contact hole, etching along described second opening the contact hole that described dielectric layer formed is the first source contact openings or the first drain contact hole, and the bottom that the bottom of described gate contact hole and the first source contact openings has polymeric layer or described gate contact hole and the first drain contact hole has polymeric layer;
Remove described polymeric layer;
Continue with described hard mask layer for mask, continuing the described dielectric layer of etching to exposing described source electrode or drain electrode along the first source contact openings or the first drain contact hole, forming the second source contact openings or the second drain contact hole;
In described gate contact hole, fill full conductive layer form gate contact connector, in described second source contact openings, the full conductive layer of filling forms source contact connector or in described second drain contact hole, fills full conductive layer formation drain contact connector.
2. form method as claimed in claim 1, it is characterized in that, described hard mask layer is single layer structure or laminated construction, and when described hard mask is single layer structure, the material of described hard mask layer is boron nitride, silicon nitride or titanium nitride; When described hard mask layer is laminated construction, described hard mask layer is the two-layer arbitrarily or three-decker in boron nitride layer, silicon nitride layer or titanium nitride layer.
3. form method as claimed in claim 1, it is characterized in that, described dielectric layer forms hard mask layer, the method in described hard mask layer with the first opening and the second opening running through its thickness comprises:
Described dielectric layer forms hard mask layer;
Described hard mask layer forms the first patterned photoresist layer;
With described first patterned photoresist layer for mask, etch described hard mask layer, there is in described hard mask layer the first opening and the second opening that run through its thickness.
4. form method as claimed in claim 3, it is characterized in that, before described hard mask layer forms the first graphical photoresist layer, after described dielectric layer forms hard mask layer, also comprise the following steps:
Described hard mask layer is formed advanced figure rete;
Described advanced figure rete forms light-absorption layer.
5. form method as claimed in claim 4, it is characterized in that, before the step of described first patterned photoresist layer for hard mask layer described in mask etching, after described hard mask layer is formed the photoresist layer of second graphical, also to comprise with described first patterned photoresist layer for mask, etch described advanced figure rete and described light-absorption layer.
6. form method as claimed in claim 5, it is characterized in that, after described figure rete forms the step of light-absorption layer, be also included on described light-absorption layer before described hard mask layer is formed the step of the first patterned photoresist layer and form bottom anti-reflection layer.
7. form method as claimed in claim 6, it is characterized in that, before the step being figure rete advanced described in mask etching and light-absorption layer with described first patterned photoresist layer, described hard mask layer is formed after the first patterned photoresist layer, the step that also to comprise with described first patterned photoresist layer be bottom anti-reflection layer described in mask etching.
8. form method as claimed in claim 4, it is characterized in that, the material of described advanced figure rete is amorphous carbon, and the material of described light-absorption layer is silicon oxynitride, carbon doped silicon oxide or silicon nitride.
9. form method as claimed in claim 1, it is characterized in that, the method removing described polymeric layer comprises: pass into removal gas to gate contact hole and the first source contact openings or gate contact hole and the first drain contact hole, described removal gas comprise in oxygen or nitrogen one or both.
10. a formation method for conductive plunger, is characterized in that, comprising:
Semiconductor base is provided;
Described semiconductor base forms dielectric layer;
Described dielectric layer forms hard mask layer, there is in described hard mask layer the opening running through its thickness;
With described hard mask layer for mask, along opening etch media layer, form the first through hole, the bottom of described first through hole has polymeric layer;
Remove the polymeric layer of described first via bottoms;
Continue with described hard mask layer for mask, continuing the described dielectric layer of etching to exposing semiconductor base along the first through hole, forming the second through hole;
In described second through hole, fill full conductive layer, form conductive plunger.
11. form method as claimed in claim 10, it is characterized in that, described hard mask layer is single layer structure or laminated construction, and when described hard mask is single layer structure, the material of described hard mask layer is boron nitride, silicon nitride or titanium nitride; When described hard mask layer is laminated construction, described hard mask layer is the two-layer arbitrarily or three-decker in boron nitride layer, silicon nitride layer or titanium nitride layer.
12. form method as claimed in claim 10, it is characterized in that, described dielectric layer forms hard mask layer, and the method in described hard mask layer with the opening running through its thickness comprises:
Described dielectric layer forms hard mask layer;
Described hard mask layer is formed the photoresist layer of second graphical;
With the photoresist layer of described second graphical for mask, etch described hard mask layer, formed in described hard mask layer and there is the opening running through its thickness.
13. form method as claimed in claim 12, it is characterized in that, before described hard mask layer is formed the photoresist layer of second graphical, after described dielectric layer forms hard mask layer, also comprise the following steps:
Described hard mask layer is formed advanced figure rete;
Described advanced figure rete forms light-absorption layer.
14. form method as claimed in claim 13, it is characterized in that, before the step of the photoresist layer of described second graphical for hard mask layer described in mask etching, after described hard mask layer is formed the photoresist layer of second graphical, also comprise with the photoresist layer of described second graphical for figure rete advanced described in mask etching and light-absorption layer.
15. form method as claimed in claim 14, it is characterized in that, after described advanced figure rete forms the step of light-absorption layer, be also included in before described hard mask layer is formed the photoresist layer of second graphical on described light-absorption layer and form bottom anti-reflection layer.
16. form method as claimed in claim 15, it is characterized in that, before the step being figure rete advanced described in mask etching and light-absorption layer with the photoresist layer of described second graphical, after described hard mask layer is formed the photoresist layer of second graphical, the step that also to comprise with described patterned photoresist layer be bottom anti-reflection layer described in mask etching.
17. form method as claimed in claim 13, it is characterized in that, the material of described advanced figure rete is amorphous carbon.
18. form method as claimed in claim 13, it is characterized in that, the material of described light-absorption layer is silicon oxynitride, carbon doped silicon oxide or silicon nitride.
19. form method as claimed in claim 10, it is characterized in that, the method removing the polymeric layer of described first via bottoms comprises: in the first through hole, pass into removal gas, described removal gas comprise in oxygen or nitrogen one or both.
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