KR20030058605A - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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Publication number
KR20030058605A
KR20030058605A KR1020010089119A KR20010089119A KR20030058605A KR 20030058605 A KR20030058605 A KR 20030058605A KR 1020010089119 A KR1020010089119 A KR 1020010089119A KR 20010089119 A KR20010089119 A KR 20010089119A KR 20030058605 A KR20030058605 A KR 20030058605A
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South Korea
Prior art keywords
plug
scribe lane
contact hole
etched
forming
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KR1020010089119A
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Korean (ko)
Inventor
남병섭
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주식회사 하이닉스반도체
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Priority to KR1020010089119A priority Critical patent/KR20030058605A/en
Publication of KR20030058605A publication Critical patent/KR20030058605A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to easily and precisely measure an alignment degree by etching even an interlayer oxide layer near a plug formed in a scribe lane in a process for forming a contact for a bitline so that the plug in the scribe lane is exposed. CONSTITUTION: The first interlayer dielectric including a contact hole for a plug(35) is formed on a substrate in which a main chip area and a scribe lane are defined such that the contact hole for the plug is formed in the scribe lane too. The plug is filled in the contact hole. The second interlayer dielectric is formed on the resultant structure including the plug. The second interlayer dielectric is etched to form an interconnection contact hole through a photolithography process using a mask transmitting light to a portion adjacent to the plug formed in the scribe lane. The first and second interlayer dielectrics are etched to expose the plug in the scribe lane.

Description

반도체 소자의 제조 방법{Method for manufacturing a semiconductor device}Method for manufacturing a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 비트 라인(Bitline)용 콘택 형성 공정 시 스크라이브 레인(Scribe lane)에 형성된 플러그(Plug) 주위의 층간 산화막도 식각하여 상기 스크라이브 레인의 플러그를 노출시키므로 소자의 수율 및 신뢰성을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, during the contact forming process for a bit line, an interlayer oxide film around a plug formed in a scribe lane is also etched to expose the plug of the scribe lane. The present invention relates to a method for manufacturing a semiconductor device for improving the yield and reliability of the device.

도 1은 오버레이 측정용 마크와 스텝퍼 얼라인 키를 도시한 평면도이다.1 is a plan view illustrating an overlay measurement mark and a stepper alignment key.

도 1을 참조하면, 메인 칩(Main chip) 영역(100)과 스크라이브 레인(101)이 정의된 반도체 기판(102)에서, 오버레이(Overlay) 정도를 측정하기 위한 오버레이 마크(Mark)(103)가 상기 스크라브 레인(101)에 형성되고, 각 공정 단계의 정렬 정도(精度)를 측정하는 스텝퍼 얼라인 키(Stepper align key)(105)가 상기 오버레이 마크(103)와 간격을 갖으며 상기 스크라브 레인(101)에 형성된다.Referring to FIG. 1, in a semiconductor substrate 102 in which a main chip region 100 and a scribe lane 101 are defined, an overlay mark 103 for measuring an overlay degree may be formed. Stepper align key 105 formed in the scrabble lane 101 to measure the degree of alignment of each process step is spaced apart from the overlay mark 103 and the scrabbe It is formed in the lane 101.

도 2a 내지 도 2c는 종래 기술에 따른 스텝퍼 얼라인 키를 도시한 단면도이다.2A to 2C are cross-sectional views illustrating stepper alignment keys according to the prior art.

도 2a를 참조하면, 메인 칩 영역과 스크라이브 레인이 정의된 반도체 기판(도시하지 않음) 상에 형성된 게이트 전극을 포함한 하부 구조물(11) 상에 콘택홀(부호화 하지 않음)을 구비한 제 1 층간 산화막(13)을 형성한다.Referring to FIG. 2A, a first interlayer oxide film having contact holes (not encoded) on a lower structure 11 including a gate electrode formed on a semiconductor substrate (not shown) in which a main chip region and a scribe lane are defined. (13) is formed.

그리고, 상기 콘택홀을 포함한 전면에 다결정 실리콘층을 형성한 후, 상기 제 1 층간 산화막(13)을 식각 방지막으로 사용하는 화학적 기계 연마 방법에 의해 상기 다결정 실리콘층을 평탄 식각하여 플러그(15)를 형성한다.After the polycrystalline silicon layer is formed on the entire surface including the contact hole, the polycrystalline silicon layer is flat-etched by a chemical mechanical polishing method using the first interlayer oxide layer 13 as an etch stop layer. Form.

도 2b를 참조하면, 상기 플러그(15)를 포함한 전면에 제 2 층간 산화막(17)을 형성한다.Referring to FIG. 2B, a second interlayer oxide film 17 is formed on the entire surface including the plug 15.

그리고, 비트 라인 콘택용 마스크를 사용한 사진 식각 공정에 의해 상기 제2 층간 산화막(17)을 식각하여 상기 메인 칩 영역에 비트 라인용 콘택홀(도시하지 않음)을 형성한다.The second interlayer oxide layer 17 is etched by a photolithography process using a bit line contact mask to form a bit line contact hole (not shown) in the main chip region.

도 2c를 참조하면, 상기 메인 칩 영역의 비트 라인용 콘택홀을 포함한 전면에 비트 라인용 금속층(19)을 형성한다.Referring to FIG. 2C, the bit line metal layer 19 is formed on the entire surface including the bit line contact hole in the main chip region.

여기서, 상기 플러그(15)가 상기 제 2 층간 산화막(17)과 금속층(19)에 의해 덮여지기 때문에 키의 단차가 형성되지 않아 각 단계의 정렬 측정이 어렵게 된다.Here, since the plug 15 is covered by the second interlayer oxide film 17 and the metal layer 19, no step difference is formed so that alignment measurement at each step becomes difficult.

종래의 플러그 형성 공정 후 층간 절연막 및 비트 라인용 금속층의 증착 공정으로 스크라이브 레인에 형성된 상기 플러그도 덮여지기 때문에 정렬 정도(精度)를 측정하기 위한 키의 단차가 형성되지 않아 패턴 형성 공정 시 정렬 정도(精度)의 계측을 어렵게 하는 문제점이 있었다.Since the plug formed in the scribe lane is also covered by the deposition process of the interlayer insulating film and the bit line metal layer after the conventional plug forming process, a key step for measuring alignment is not formed, and thus the alignment degree in the pattern forming process ( There has been a problem that makes measurement of precision difficult.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 비트 라인용 콘택 형성 공정 시 스크라이브 레인에 형성된 플러그 주위의 층간 산화막도 식각하여 상기 스크라이브 레인의 플러그를 노출시키므로, 정렬 정도(精度)의 계측이 용이한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and during the bit line contact forming process, the interlayer oxide film around the plug formed in the scribe lane is also etched to expose the plug of the scribe lane, thereby making it easy to measure alignment accuracy. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

도 1은 오버레이 측정용 마크와 스텝퍼 얼라인 키를 도시한 평면도.1 is a plan view showing an overlay measurement mark and a stepper alignment key;

도 2a 내지 도 2c는 종래 기술에 따른 스텝퍼 얼라인 키를 도시한 단면도.2A-2C are cross-sectional views illustrating stepper alignment keys according to the prior art;

도 3a 내지 도 3d는 본 발명의 실시 예에 따른 스텝퍼 얼라인 키를 도시한 단면도.3A to 3D are cross-sectional views illustrating stepper alignment keys according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11, 31: 하부 구조물13, 33: 제 1 층간 산화막11, 31: substructure 13, 33: first interlayer oxide film

15, 35: 플러그17, 37: 제 2 층간 산화막15, 35: plug 17, 37: second interlayer oxide film

19, 41: 금속층39: 감광막 패턴19 and 41: metal layer 39: photosensitive film pattern

100: 메인 칩 영역101: 스크라브 레인100: main chip area 101: scribe lane

102: 반도체 기판103: 오버레이 마크102: semiconductor substrate 103: overlay mark

105: 스텝퍼 얼라인 키105: stepper alignment key

이상의 목적을 달성하기 위한 본 발명은 메인 칩 영역과 스크라이브 레인이 정의된 기판 상에 플러그용 콘택홀이 구비된 제 1 층간 절연막을 형성하되, 상기 스크라이브 레인에도 상기 플러그용 콘택홀을 형성하는 단계, 상기 플러그용 콘택홀을 매립하는 플러그를 형성하는 단계, 상기 플러그를 포함한 전면에 제 2 층간절연막을 형성하는 단계 및 배선 콘택용이며 상기 스크라이브 레인에 형성된 플러그의 인접 부위를 투광시키는 마스크를 사용하는 사진식각 공정에 의해 상기 제 2 층간 절연막을 식각하여 배선용 콘택홀을 형성하고 상기 제 1, 제 2 층간 절연막을 식각하여 상기 스크라이브 레인의 플러그를 노출시키는 단계를 포함하는 반도체 소자의 제조 방법을 제공하는 것을 특징으로 한다.The present invention for achieving the above object is to form a first interlayer insulating film provided with a plug contact hole on the substrate on which the main chip region and the scribe lane is defined, forming the plug contact hole in the scribe lane, Forming a plug filling the contact hole for the plug, forming a second interlayer insulating film on the front surface including the plug, and using a mask for wiring contacts and transmitting adjacent portions of the plug formed in the scribe lane. And forming a contact hole for wiring by etching the second interlayer insulating layer by an etching process, and etching the first and second interlayer insulating layers to expose a plug of the scribe lane. It features.

본 발명의 원리는 비트 라인용 콘택 형성 공정 시 스크라이브 레인에 형성된 플러그 주위의 층간 산화막도 식각하여 상기 스크라이브 레인의 플러그를 노출시키므로, 상기 노출된 스크라이브 레인의 플러그에 의해 정렬 정도(精度)를 측정하기 위한 키의 단차를 발생시기 때문에 정렬 정도(精度)의 계측이 용이한 발명이다.The principle of the present invention also exposes the plug of the scribe lane by etching the interlayer oxide film around the plug formed in the scribe lane during the bit line contact forming process, thereby measuring the degree of alignment by the plug of the exposed scribe lane. It is an invention that the measurement of the alignment accuracy is easy because the step of the key for the purpose is generated.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3d는 본 발명의 실시 예에 따른 스텝퍼 얼라인 키를 도시한 단면도이다.3A to 3D are cross-sectional views illustrating stepper alignment keys according to an exemplary embodiment of the present invention.

도 3a를 참조하면, 메인 칩 영역과 스크라이브 레인이 정의된 반도체 기판(도시하지 않음) 상에 형성된 게이트 전극을 포함한 하부 구조물(31) 상에 제 1 층간 산화막(33)을 형성한다.Referring to FIG. 3A, a first interlayer oxide layer 33 is formed on a lower structure 31 including a gate electrode formed on a semiconductor substrate (not shown) in which a main chip region and a scribe lane are defined.

그리고, 플러그용 마스크를 사용한 사진식각 공정에 의해 상기 제 1 층간 산화막(33)을 식각하여 플러그용 콘택홀(부호화 하지 않음)을 형성한다. 이때, 상기 스크라이브 레인에도 상기 플러그용 콘택홀을 형성한다.Then, the first interlayer oxide film 33 is etched by a photolithography process using a plug mask to form a plug contact hole (not encoded). In this case, the plug contact hole is formed in the scribe lane.

이어, 상기 콘택홀을 포함한 전면에 다결정 실리콘층을 형성한 후, 상기 제 1 층간 산화막(33)을 식각 방지막으로 사용하는 화학적 기계 연마 방법에 의해 상기 다결정 실리콘층을 평탄 식각하여 플러그(35)를 형성한다.Subsequently, after the polycrystalline silicon layer is formed on the entire surface including the contact hole, the polycrystalline silicon layer is flatly etched by a chemical mechanical polishing method using the first interlayer oxide layer 33 as an etch stop layer. Form.

도 3b를 참조하면, 상기 플러그(35)를 포함한 전면에 제 2 층간 산화막(37)을 형성한다.Referring to FIG. 3B, a second interlayer oxide film 37 is formed on the entire surface including the plug 35.

도 3c를 참조하면, 상기 제 2 층간 산화막(37) 상에 감광막을 도포하고, 상기 감광막을 상기 메인 칩 영역에 비트 라인 콘택이 형성될 부위와 상기 스크라이브 레인에 형성된 플러그(35)에 인접한 부위만 제거되도록 선택적으로 노광 및 현상하여 감광막 패턴(39)을 형성한다.Referring to FIG. 3C, a photoresist film is coated on the second interlayer oxide film 37, and the photoresist film is only a portion where a bit line contact is to be formed in the main chip region and a portion adjacent to a plug 35 formed in the scribe lane. It is selectively exposed and developed to be removed to form the photoresist pattern 39.

그리고, 상기 감광막 패턴(39)을 마스크로 상기 제 2 층간 산화막(37)을 식각하여 상기 메인 칩 영역에 비트 라인용 콘택홀(도시하지 않음)을 형성하고 상기 제 1, 제 2 층간 산화막(33,37)을 식각하여 상기 스크라이브 레인에 형성된 플러그(35)를 노출시킨다.The second interlayer oxide layer 37 is etched using the photoresist pattern 39 as a mask to form a bit line contact hole (not shown) in the main chip region, and to form the first and second interlayer oxide layers 33. , 37) is etched to expose the plug 35 formed in the scribe lane.

도 3d를 참조하면, 상기 노출된 플러그(35)를 포함한 전면에 비트 라인용 금속층(41)을 형성한다.Referring to FIG. 3D, the bit line metal layer 41 is formed on the entire surface including the exposed plug 35.

여기서, 상기 스크라이브 레인에 형성된 플러그(35)가 노출된 상태에서 상기 금속층(41)을 형성하기 때문에 키의 단차가 형성되어 각 단계의 정렬 측정이 용이하게 된다.Here, since the metal layer 41 is formed in a state in which the plug 35 formed in the scribe lane is exposed, a step of a key is formed to facilitate alignment measurement at each step.

본 발명의 반도체 소자의 제조 방법은 비트 라인용 콘택 형성 공정 시 스크라이브 레인에 형성된 플러그 주위의 층간 산화막도 식각하여 상기 스크라이브 레인의 플러그를 노출시키므로, 상기 노출된 스크라이브 레인의 플러그에 의해 정렬정도(精度)를 측정하기 위한 키의 단차를 발생시켜 정렬 정도(精度)의 계측이 용이하므로 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention, the interlayer oxide film around the plug formed in the scribe lane is also etched during the bit line contact forming process to expose the plug of the scribe lane, so that the alignment of the exposed scribe lane is achieved by the plug of the exposed scribe lane. Since a step of a key for measuring) is generated, the alignment accuracy can be easily measured, thereby improving the yield and reliability of the device.

Claims (1)

메인 칩 영역과 스크라이브 레인이 정의된 기판 상에 플러그용 콘택홀이 구비된 제 1 층간 절연막을 형성하되, 상기 스크라이브 레인에도 상기 플러그용 콘택홀을 형성하는 단계;Forming a first interlayer insulating layer including a plug contact hole on a substrate on which a main chip region and a scribe lane are defined, and forming the plug contact hole in the scribe lane; 상기 플러그용 콘택홀을 매립하는 플러그를 형성하는 단계;Forming a plug to bury the plug contact hole; 상기 플러그를 포함한 전면에 제 2 층간 절연막을 형성하는 단계;Forming a second interlayer insulating film on the entire surface including the plug; 배선 콘택용이며 상기 스크라이브 레인에 형성된 플러그의 인접 부위를 투광시키는 마스크를 사용하는 사진식각 공정에 의해 상기 제 2 층간 절연막을 식각하여 배선용 콘택홀을 형성하고 상기 제 1, 제 2 층간 절연막을 식각하여 상기 스크라이브 레인의 플러그를 노출시키는 단계를 포함하는 반도체 소자의 제조 방법.The second interlayer insulating film is etched by using a photolithography process using a mask for transmitting wiring adjacent to the adjacent portions of the plugs formed in the scribe lanes to form wiring contact holes, and the first and second interlayer insulating films are etched. Exposing the plug of the scribe lane.
KR1020010089119A 2001-12-31 2001-12-31 Method for manufacturing a semiconductor device KR20030058605A (en)

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