JPS5827335A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5827335A JPS5827335A JP12653081A JP12653081A JPS5827335A JP S5827335 A JPS5827335 A JP S5827335A JP 12653081 A JP12653081 A JP 12653081A JP 12653081 A JP12653081 A JP 12653081A JP S5827335 A JPS5827335 A JP S5827335A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- films
- sides
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000001020 plasma etching Methods 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 206010007559 Cardiac failure congestive Diseases 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000009563 continuous hemofiltration Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 210000003141 lower extremity Anatomy 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 101000617728 Homo sapiens Pregnancy-specific beta-1-glycoprotein 9 Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 102100021983 Pregnancy-specific beta-1-glycoprotein 9 Human genes 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法の改良に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a semiconductor device.
例えば半導体基板としてシリコン（Ｓｌ）基板を用い該
基板上に従来の方法を用い”ｃｗｏｓｍの半導体装置を
形成する場合、第１図に示すようにＰａｌのＳｔ基板１
に所定パターンの窒化シリコン（Ｓｉ３札）膜（図示せ
ず）をマスクとして素子閤分離用の二酸化シリコン（＄
１へ）膜２を熱酸化により廖戒する。For example, when using a silicon (Sl) substrate as a semiconductor substrate and forming a "cwosm" semiconductor device on the substrate using a conventional method, as shown in FIG.
Using a silicon nitride (Si3 card) film (not shown) with a predetermined pattern as a mask, silicon dioxide ($3) for device isolation is applied.
Step 1) The film 2 is oxidized by thermal oxidation.
その後前記８１３ Ｎ、膜をプラズマエツチング法で除
去したのち、該基板にゲート酸化膜形成用の５ｔｙｘ展
を熱酸化法で形成する。その後該ＳｉＱ膜上にゲート電
極となるポリシリコン膜を全面に化学蒸着（ＣＶＤ）法
を被着したのち、該基板上にホトレジスト膜を被着する
。その後該ホトレジスト膜を所定パターンにホトエツチ
ング法を用いて形成してから、該パターニングされたホ
トレジスト族をマスクとして四弗化メタン（ＣＦＪ）ガ
スでプラズマエツチングＬｍ記ポリシリコン展を所定パ
ターンに形成して図の３のポリシリコンゲート電極を形
成する。Thereafter, the 813N film is removed by plasma etching, and then a 5tyx film for forming a gate oxide film is formed on the substrate by thermal oxidation. Thereafter, a polysilicon film that will become a gate electrode is deposited on the entire surface of the SiQ film by chemical vapor deposition (CVD), and then a photoresist film is deposited on the substrate. Thereafter, the photoresist film is formed in a predetermined pattern using a photoetching method, and then, using the patterned photoresist as a mask, plasma etching is performed using tetrafluoromethane (CFJ) gas to form a polysilicon film in a predetermined pattern. A polysilicon gate electrode 3 in the figure is formed.
その後該パターニングされたポリシリコンゲート電極３
をマスクとして下部の５ｉＱＪＩをトリフオルオルメタ
ン（ＣＨＦｓ）のガスでプラズマエツチングしてゲート
酸化ｊ［４を形成する。After that, the patterned polysilicon gate electrode 3
Using as a mask, the lower 5iQJI is plasma etched with trifluoromethane (CHFs) gas to form gate oxide j[4.
その１１！該ポリシリコンゲート電極３をマスクとして
燐または砒素原子をイオン注入後基板を熟旭理しソース
領域５およびドレイン領域６を形成してＭＯ３１１半導
体装置を形成している。Part 11! After ion implantation of phosphorus or arsenic atoms using the polysilicon gate electrode 3 as a mask, the substrate is thoroughly polished to form a source region 5 and a drain region 6, thereby forming an MO311 semiconductor device.
その後該基板上にパッジベージ、ン膜としてＣＶＤ法で
９ん硅酸ガラス（ＰＳＧ）膜を形成し【から、前記ゲー
ト電極上、ソース領域上、ドレイン領域上のＰＳＧ膜を
窓開きして後で該ＰＳＧＩＩ上に形成するアルミニウム
（Ａｔ＞の配線族と接続を取るためのスルーホールを形
成し、その後該基板上にＡｔ配線展を蒸着によって形成
して半導体装置を形成している。After that, a 9-silicate glass (PSG) film is formed as a padding film on the substrate by CVD method [Then, the PSG film on the gate electrode, source region, and drain region is opened. A through hole is formed to connect with the aluminum (At> wiring group formed on the PSGII), and then an At wiring layer is formed on the substrate by vapor deposition to form a semiconductor device.
しかし上述した従来の方法においては、前記素子間分離
用Ｓｉ ＯＨ３Ｉ２勘よびソース、ドレイン領域の形成
用不純物を拡散するための拡散用マスクとなるボ９８１
膜等を形成する場合いずれも基板を熱処理するため、熱
処理後基板を次の工程へ移すために放冷する間に基板と
前記５１０□膜およびボ９Ｓｉ膜等の被膜等の熱膨張係
数が興なるため基板に一方向のみそりを生ずる問題点を
生ずる。However, in the conventional method described above, the hole 981 that serves as a diffusion mask for diffusing the impurity for forming the element isolation SiOH3I2 and source and drain regions is used.
When forming a film, etc., the substrate is heat-treated, so the thermal expansion coefficient of the substrate and the coatings such as the 510□ film and the Bo9Si film are Therefore, a problem arises in that the substrate is warped in one direction.
このようなそりは例えば４吋の基板において周辺と中央
部との閏で１５〜２５１ＩＩｍにも及ぶことがあり、マ
スク合せ等の工程で支障をきたす不都合を生じる。For example, in a 4-inch substrate, such warpage can reach as much as 15 to 251 IIm between the periphery and the center, causing problems such as interfering with processes such as mask alignment.
本発明は上述した欠点を除去し、５１基板にそりを生じ
ないような半導体装置の製造方法の提供を目的とするも
のである。The present invention aims to eliminate the above-mentioned drawbacks and to provide a method for manufacturing a semiconductor device that does not cause warpage in the 51 substrate.
かかる目的を達成するための半導体装置の製造方法は、
半導体基板表面に素子形成用の所定パターンの被膜を形
成し、該被膜を用いて該基板に半導体素子を形成する工
程を含む半導体装置の製造方法において、前記半導体基
板の裏面側にも該基板の表両側と同一パターンの被膜を
あらかじめ形成する工程を含むことを特徴とするもので
ある。A method for manufacturing a semiconductor device to achieve this purpose is as follows:
A method for manufacturing a semiconductor device including a step of forming a film with a predetermined pattern for forming an element on the surface of a semiconductor substrate, and using the film to form a semiconductor element on the substrate, wherein the film is also formed on the back side of the semiconductor substrate. This method is characterized by including a step of forming in advance a coating having the same pattern on both sides of the front surface.
以下図面を用いて本発明の一実施例につき詳細に脱刷す
る。An embodiment of the present invention will be described in detail below with reference to the drawings.
第２図より第５図までは本発明の半導体装置の製造方法
の工程を示す断面図である。2 to 5 are cross-sectional views showing the steps of the method for manufacturing a semiconductor device of the present invention.
まず第１図争こ示すようにＰ型の５１基板１１上に所定
パターンのＳｉｓ Ｎｓ膜νを該基板の表面および裏面
側に被着する。First, as shown in Figure 1, a Sis Ns film ν having a predetermined pattern is deposited on a P-type 51 substrate 11 on the front and back sides of the substrate.
このようなパターニングせるＳｉｓＮａＭを形成するに
は、まず基板の表面と裏面側に３１３Ｎ４膜の下敷層と
しての簿いｓ五〇、膜（図示せず）を熱酸化法により形
成したのちホトエツチング法を用いて所定のパターンに
形成する。その後肢基板の両面にＳｉ、Ｎ、膜をＣＶＤ
法により被着した後、該基板上の両面にホトレジスト族
を被着した後練ホトレジスト膜をホトエツチング法で所
定のパターンに形成し、その後練パターニングするホト
レジスト膜をマスクとして前記Ｓｔ、 Ｎ、膜をプラズ
マエツチング法で所定のパターンに形成する。To form such a patterned SisNaM, first, a 313N4 film (not shown) with a thickness of 50 mm as an underlying layer is formed on the front and back sides of the substrate by a thermal oxidation method, and then a photoetching method is applied. to form a predetermined pattern. CVD Si, N, and films on both sides of the hindlimb substrate
After the photoresist film is deposited on both sides of the substrate using a photoresist method, a pre-processed photoresist film is formed into a predetermined pattern using a photoetching method, and then the St, N, and N films are coated using the photoresist film to be prepared and patterned as a mask. A predetermined pattern is formed using a plasma etching method.
その後第３図に示すように前記パターニングせるＳ５
Ｎ、膜νをマスクとして熱酸化法により素子間分離用の
５１ｏ２暎ソな基板のＩに所定のパターンで形成する。After that, the patterning is performed as shown in FIG.
N and a predetermined pattern are formed on I of a 51.degree.
その後前記５ｉｌＮＪ１２をプラズマエツチング法で除
去したのち第４図に示すように該基板上に熱酸化法によ
りゲート酸化膜としてのＳｔ ｏｘ ［１４を基板の４
岨こ形成する。Thereafter, the 5ilNJ12 was removed by plasma etching, and then Stox [14] was deposited as a gate oxide film on the substrate by thermal oxidation, as shown in FIG.
Form a ridge.
更に該基板の両面にグテト電極とするためのポリＳｉ膜
１５をＣＶＤ法により被着する。Furthermore, a poly-Si film 15 to serve as a gate electrode is deposited on both sides of the substrate by CVD.
その後肢基板の両面普こホトレジスト膜を被着したのち
、該ホトレジスト膜を所定のパターン曇こホトエツチン
グ法を用いて形成したのち、該パターニングせるホトレ
ジスト族をマスクとしてポリＳｉ膜をＣＦガスを用いた
プラズマエツチング法にて所定パターンに形成する。第
５図の１５Ａはこのようにして形成したポ１７ Ｓｔの
ゲート電極である。After coating both sides of the hindlimb substrate with a poly-Si photoresist film, the photoresist film was formed using a predetermined pattern cloudy photoetching method, and then a poly-Si film was formed using CF gas using the photoresist group to be patterned as a mask. A predetermined pattern is formed using a plasma etching method. Reference numeral 15A in FIG. 5 is the gate electrode of the electrode 17St formed in this manner.
更に前記パターニングされたボＩＪ ５１膜１５Ａをマ
スクとして下部のＳｉＯ２膜をＣＨＦｓガスを用いたプ
ラズマエツチング法で所定パターンに形成しゲート酸化
ｊｌ１４Ａを形成する。Furthermore, using the patterned IJ 51 film 15A as a mask, the lower SiO2 film is formed into a predetermined pattern by plasma etching using CHFs gas to form a gate oxide film 14A.
このようにしてＳｔ基板の表面と裏面の両側に所定パタ
ーンの被膜を形成してから前記ボ９Ｓｉ膜１５その後肢
基板の１ｉｉｄＫｃｖＤ法ニヨリＰＳＧ膜ヲ／（ッシベ
ーシ、ン膜として形成したのち、該基板の表面側にのみ
ソース領域、ゲート電極、ドレイン領域から電極接続用
のスルーホールを開孔してからアルミニウム（Ａｔ）の
配線用被膜を蒸着によっ子間分離用５ｉｎ２膜を研磨し
て除去したのち所定のチップに切断して半導体素子を形
成する。After forming a film with a predetermined pattern on both the front and back surfaces of the St substrate in this way, a PSG film is formed on the rear substrate of the Si film 15 using the 1iidKcvD method as a film, and then the substrate is coated with a PSG film. Through-holes for connecting electrodes were made from the source region, gate electrode, and drain region only on the surface side of the substrate, and then an aluminum (At) wiring film was deposited by evaporation, and the 5in2 film for isolation between the members was removed by polishing. Thereafter, it is cut into predetermined chips to form semiconductor elements.
以上述べたようを二本発明の方法によって半導体装置を
形成すればＳｉ基板の両側に同一パターンの素子形成用
の被膜が形成されているので、熱処理工程−こよって基
板が一方向にそるようなことがなくなり、したがってマ
スク合せの工程が精度良〈実施できるので高信頼度の半
導体装置が高歩留で得られる利点がある１゜As described above, if a semiconductor device is formed by the method of the present invention, a film for forming elements with the same pattern is formed on both sides of the Si substrate, so the heat treatment process - thus preventing the substrate from warping in one direction. Therefore, the mask alignment process can be carried out with high precision, which has the advantage that highly reliable semiconductor devices can be obtained at a high yield.
第１図はＭＯ８型半導体装置の断面図、第２図より第５
図までは本発明の半導体装置の製造方法の一実施例の工
程を示す断面図である。
７ 図において、１．１１はＳｉ基板、２．１３．１
４は５ｔＯ１膜、３．１５Ａはゲート電極、４，１４Ａ
はゲート酸化６
膜、５４督はソース領域、６．１７はドレイン領域、１
２はＳｔ、 Ｎ、膜、ｂはポリＳｉ膜を示す。
第２ｎ
２
ｚ
第３図
第４［４
５Figure 1 is a cross-sectional view of the MO8 type semiconductor device, and Figure 2 shows 5.
The drawings are cross-sectional views showing steps of an embodiment of the method for manufacturing a semiconductor device of the present invention. 7 In the figure, 1.11 is a Si substrate, 2.13.1
4 is 5tO1 film, 3.15A is gate electrode, 4,14A
is the gate oxide film 6, 54 is the source region, 6.17 is the drain region, 1
2 indicates an St, N, film, and b indicates a poly-Si film. No. 2 n 2 z Fig. 3 No. 4 [4 5
Claims (1)
成し、該被膜を用いて該基板に半導体素子を形成する工
程を含む半導体装置の＃！造方法において、前記半導体
基板の裏ｗｌｌにも該基板の表面側と同一パターンの被
膜をあらかじめ形成する工程を含むことを特徴とする半
導体装置の製造方法。#! of a semiconductor device including a step of forming a film with a predetermined pattern for forming an element on the surface of a semiconductor substrate, and using the film to form a semiconductor element on the substrate. A method for manufacturing a semiconductor device, comprising the step of previously forming a film on the back side of the semiconductor substrate with the same pattern as on the front side of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12653081A JPS5827335A (en) | 1981-08-11 | 1981-08-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12653081A JPS5827335A (en) | 1981-08-11 | 1981-08-11 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5827335A true JPS5827335A (en) | 1983-02-18 |
Family
ID=14937479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12653081A Pending JPS5827335A (en) | 1981-08-11 | 1981-08-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827335A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4649087A (en) * | 1985-06-10 | 1987-03-10 | Reynolds Metals Company | Corrosion resistant aluminum brazing sheet |
| US4828794A (en) * | 1985-06-10 | 1989-05-09 | Reynolds Metals Company | Corrosion resistant aluminum material |
| JPH0234296A (en) * | 1988-07-22 | 1990-02-05 | Sky Alum Co Ltd | Brazing alloy for aluminum and brazing sheet for heat exchanger made of aluminum |
| JPH0234297A (en) * | 1988-07-22 | 1990-02-05 | Sky Alum Co Ltd | Brazing alloy for aluminum and brazing sheet for heat exchanger made of aluminum |
| US5278089A (en) * | 1989-10-27 | 1994-01-11 | Sony Corporation | Method for producing a read-only memory having a plurality of MISFET |
-
1981
- 1981-08-11 JP JP12653081A patent/JPS5827335A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4649087A (en) * | 1985-06-10 | 1987-03-10 | Reynolds Metals Company | Corrosion resistant aluminum brazing sheet |
| US4828794A (en) * | 1985-06-10 | 1989-05-09 | Reynolds Metals Company | Corrosion resistant aluminum material |
| JPH0234296A (en) * | 1988-07-22 | 1990-02-05 | Sky Alum Co Ltd | Brazing alloy for aluminum and brazing sheet for heat exchanger made of aluminum |
| JPH0234297A (en) * | 1988-07-22 | 1990-02-05 | Sky Alum Co Ltd | Brazing alloy for aluminum and brazing sheet for heat exchanger made of aluminum |
| US5278089A (en) * | 1989-10-27 | 1994-01-11 | Sony Corporation | Method for producing a read-only memory having a plurality of MISFET |
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