JPS59175726A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59175726A JPS59175726A JP5070383A JP5070383A JPS59175726A JP S59175726 A JPS59175726 A JP S59175726A JP 5070383 A JP5070383 A JP 5070383A JP 5070383 A JP5070383 A JP 5070383A JP S59175726 A JPS59175726 A JP S59175726A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- forming
- metal
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 238000006243 chemical reaction Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 32
- 229910052697 platinum Inorganic materials 0.000 description 15
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 9
- 229910021339 platinum silicide Inorganic materials 0.000 description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 101100381891 Botryotinia fuckeliana (strain B05.10) BOA3 gene Proteins 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 108010016828 adenylyl sulfate-ammonia adenylyltransferase Proteins 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
導体素子を形式したシリコン（Ｓｉ）基板上に二酸化シ
リコン膜のような絶縁膜を形成後、該絶縁膜を所定パタ
ーンに窓開き後、該基板上にアルミニウムＣＡｌ）のよ
うな配線用被膜を形成して、半導体素子間を接続してい
る。ところで、がくして製作、完成された半導体チップ
を気密封止組立てする際、チップうう付け工程にてかな
りの高温が加わることになる。即ち、前記ＡＩ配線膜を
形成してから熱処理工程が加わることになり、そのため
配線用のＡＩ！金属と接続を取っている半導体素子形成
領域の８１とが反応してＡ／とｓＩの合金が形成され、
そのため半導体装置の特性が変動する欠点を生じるいる
。Detailed Description of the Invention (a) Technical Field of the Invention After forming an insulating film such as a silicon dioxide film on a silicon (Si) substrate on which a conductive element is formed, opening the insulating film in a predetermined pattern, A wiring film such as aluminum (CAl) is formed on the substrate to connect semiconductor elements. By the way, when the semiconductor chips that have been manufactured and completed are hermetically sealed and assembled, considerable high temperatures are applied during the chip mounting process. That is, a heat treatment process is added after forming the AI wiring film, so that the AI! 81 in the semiconductor element forming region connected to the metal reacts to form an alloy of A/ and sI,
This has the disadvantage that the characteristics of the semiconductor device vary.
そこでこのような現象を防ぐため、絶縁膜を窓開きした
のち、基板上に白金（ｐｔ）のような金属膜を蒸着また
はスパッタ法により形成後、該基板を熱処理して窓開き
された部分の８１基板表面に白金シリサイド膜を形成後
、その後絶縁膜上に存在しているＰｔ膜を王水でエツチ
ング処理して除去し、該金属シリサイド膜上にＡＡｔの
ような配線膜を形成したり、あるいは窒化チタン被膜を
形成してからＡＩ絶縁膜を形成する方法をとっている。Therefore, in order to prevent this phenomenon, after opening the insulating film, a metal film such as platinum (PT) is formed on the substrate by vapor deposition or sputtering, and then the substrate is heat-treated to remove the windowed area. 81 After forming a platinum silicide film on the surface of the substrate, the Pt film existing on the insulating film is removed by etching with aqua regia, and a wiring film such as AAt is formed on the metal silicide film. Alternatively, a method is used in which a titanium nitride film is formed and then an AI insulating film is formed.
しかしこのような窓開きされだ部分に白金シリサイド膜
を介してＡｌ配線膜を形成する方法では、白金シリサイ
ド膜中の成分が窓開きした部分の８１基板の素子形成領
域に熱処理中拡散して、例えば窓開きした部分がトラン
ジスタのエミッタ形成領域であると、該領域の有効巾寸
法や有効深さ寸法が変動したりする欠点がある。However, in such a method of forming an Al wiring film via a platinum silicide film in the open window portion, components in the platinum silicide film diffuse into the element formation region of the 81 substrate in the window open portion during heat treatment. For example, if the windowed portion is an emitter formation region of a transistor, there is a drawback that the effective width and effective depth of the region vary.
また、金属シリサイド膜の種類によってはＳ ｉｏｚ膜
との密着性が悪く剥離するものもある。Further, depending on the type of metal silicide film, some may have poor adhesion with the Sioz film and may peel off.
そこで窓開きしたＳｉ基板表面に燐ＣＰ）等の不純物原
子を添加した低抵抗の多結晶Ｓｉ膜を形成し、該多結晶
ＳｉＭを介してその上に金属シリサイド膜を形成する方
法がとられている。Therefore, a method has been adopted in which a low-resistance polycrystalline Si film doped with impurity atoms such as phosphorus (CP) is formed on the surface of an Si substrate with an open window, and a metal silicide film is formed thereon via the polycrystalline SiM. There is.
（Ｃ） 従来技術と問題点
そこでこのような多結晶シリコン膜を介在させて、その
上に所定パターンの金属シリサイド膜、Ａｌ配線膜を形
成する従来の半導体装置の製造方法について金属シリサ
イドに白金（Ｐ４）を用いた領域近傍の窓開き箇所につ
いて第１図より第７図までの図面を用いて詳細に説明す
る。(C) Prior art and problems Regarding the conventional manufacturing method of semiconductor devices in which such a polycrystalline silicon film is interposed and a metal silicide film and an Al wiring film in a predetermined pattern are formed on the polycrystalline silicon film, platinum ( The window opening location near the area using P4) will be explained in detail using the drawings from FIG. 1 to FIG. 7.
まず第１図に示すようにＳｉ基板ｌ上にエミッタ領域２
上を窓開きした５ｈｏ２膜３を形成後、その上に多結晶
Ｓｉ膜４を化学蒸着（ＯＶＤ）法を用いて形成した後、
多結晶Ｓｉ膜を通しリン、ひ素などを熱拡散し、エミッ
タを形成する。First, as shown in FIG. 1, an emitter region 2 is placed on a Si substrate l.
After forming a 5ho2 film 3 with an open window on the top, and forming a polycrystalline Si film 4 thereon using a chemical vapor deposition (OVD) method,
Phosphorus, arsenic, etc. are thermally diffused through the polycrystalline Si film to form an emitter.
その後該基板上に所定パターンのレジスト膜（図示せず
うを形成後、該バターニングせるレジスト膜をマスクド
して四弗化炭素Ｃ０Ｆ４）ガスを反応ガスとしてプラズ
マエツチングで、多結晶Ｓ１膜４を所定パターンにエツ
チングする。第２図で４Ａはこのようにバターニングさ
れた多結晶Ｓ１膜である。After forming a resist film (not shown) in a predetermined pattern on the substrate, the resist film to be patterned is masked and the polycrystalline S1 film 4 is formed by plasma etching using carbon tetrafluoride C0F4 gas as a reaction gas. Etch into a predetermined pattern. In FIG. 2, 4A is a polycrystalline S1 film patterned in this manner.
次いで第３図に示すように白金（ｐＨ膜５を基板全面に
蒸着またはスパッタ法により形成する。Next, as shown in FIG. 3, a platinum (pH film 5) is formed over the entire surface of the substrate by vapor deposition or sputtering.
その後該基板を熱処理して白金膜５と多結晶Ｓ１摸とを
反応させると、第４図のように所定バターニングされた
多結晶Ｓ１膜の上層のみが、白金シリサイド膜６となり
他の領域の白金膜は反応せず白金膜５Ａのままである。Thereafter, when the substrate is heat-treated to cause a reaction between the platinum film 5 and the polycrystalline S1 sample, only the upper layer of the polycrystalline S1 film patterned in a predetermined pattern becomes the platinum silicide film 6 as shown in FIG. The platinum film does not react and remains as the platinum film 5A.
次いで該基板を王水で全面エツチングすると白金膜５Ａ
はエツチングされ、白金シリサイド膜６はそのまま残り
第５図のようになる。Then, when the entire surface of the substrate is etched with aqua regia, a platinum film 5A is formed.
is etched, and the platinum silicide film 6 remains as it is, as shown in FIG.
次いで第６図に示すように窒化チタン膜７およびＡｌ配
線膜８を順次スパッタ法、あるいは蒸着シリサイド膜と
の反応を阻＋ｈするための）くリヤとなる金属膜である
。Next, as shown in FIG. 6, a titanium nitride film 7 and an Al wiring film 8 are sequentially sputtered or a metal film is formed as a barrier to prevent reaction with the deposited silicide film.
次いで該基板上に所定パターンのホトレジスト膜（図示
せず）を形成後、該バター襲ングせるレジスト膜をマス
クとして、三塩化硼素（ＢＯＡ３）を反応ガスとして用
いてリアクテイブイオンエ゛ンチングにより、Ａｌ配線
膜８と窒化チタン膜７とを順次エツチングする。このよ
うにした状態を第７図に示す。Next, after forming a photoresist film (not shown) in a predetermined pattern on the substrate, reactive ion etching is carried out using boron trichloride (BOA3) as a reactive gas using the butter-baked resist film as a mask. The Al wiring film 8 and the titanium nitride film 7 are sequentially etched. This state is shown in FIG.
しかしこのような従来の方法においては、前述の白金膜
５Ａをエツチングするのに王水を用いたウェットエツチ
ングを行わねばならず、工程力（煩雑となる欠点を生じ
る。However, in such a conventional method, wet etching using aqua regia must be performed in order to etch the platinum film 5A described above, resulting in a drawback that the process is labor intensive (complicated).
また第２図に示すように多結晶シリコン膜４を所定パタ
ーン４Ａにエツチングする工程と、第６図に示す窒化チ
タン膜７およびＡ４配線膜８を所ターンの位置ずれを生
じる等間頭が多い。In addition, there are many problems such as etching the polycrystalline silicon film 4 into a predetermined pattern 4A as shown in FIG. 2, and the step of etching the titanium nitride film 7 and A4 wiring film 8 shown in FIG. .
（ｄ） ／Ａ明の目的
本発明は上述した欠点全除去し、前述した多結晶ｓｉ
膜を始走のノくターンむこ形成する工程と、後のＡｌ配
線膜を所定の／ぐターン（こ形成する工程とを一回のマ
スク合せで済むようにして、かつウェットエツチングの
ような複雑な工程を必要とせず工程を加重にして、かつ
形成される半導体装置のパターンの精度を向上きせる新
規な半導体装＋ｉの製造方法の提供を目的とするもので
ある。(d) OBJECT OF THE INVENTION The present invention eliminates all the above-mentioned drawbacks and
The process of forming the film in the first turn and the process of forming the subsequent Al wiring film in the predetermined turn can be done by one mask alignment, and it is possible to avoid complex processes such as wet etching. It is an object of the present invention to provide a novel method for manufacturing a semiconductor device +i that does not require the above steps, increases the process load, and improves the accuracy of the pattern of the formed semiconductor device.
（ｅ） 発明の構成
かかる目的を達成するための本発明の半導体装置の製造
方法は、シリコン基板上Ｇこ所定ノぐターンの絶縁膜を
形成後、該基板全面に多結晶シリコン膜を形成し、次い
で該基板上にシリコンと反応して、金属シリサイド膜を
形成するような第１の金属膜を形成後、該基板上に金属
シリサイド膜と配線用金属膜との反応を阻止する第２の
被膜及び配線用の第８の金属膜を順次積層形成し、第１
の金属膜を形成後に該基板を熱処理して、第１の金属膜
と多結晶シリコン膜とを反応させて金属シリサイド膜を
形成し、該金属シリサイド膜を含めて該積層形成した被
膜を絶縁膜に至るまで、所定のパターンにエツチングす
ることを特徴とするものである。(e) Structure of the Invention The method for manufacturing a semiconductor device of the present invention to achieve the above object comprises forming an insulating film with a predetermined number of turns on a silicon substrate, and then forming a polycrystalline silicon film on the entire surface of the substrate. Then, after forming a first metal film on the substrate that reacts with silicon to form a metal silicide film, a second metal film is formed on the substrate to prevent the reaction between the metal silicide film and the wiring metal film. A coating and an eighth metal film for wiring are sequentially laminated, and the first
After forming the metal film, the substrate is heat-treated to cause a reaction between the first metal film and the polycrystalline silicon film to form a metal silicide film, and the laminated film including the metal silicide film is formed into an insulating film. It is characterized by etching in a predetermined pattern until it reaches .
（ｆ） 発明の実施例
以下図面を用いなから本発明の一実施例につき詳細に説
明する。(f) Embodiment of the Invention An embodiment of the invention will be described below in detail with reference to the drawings.
第８図より第り図までが本発明の半導体装置の製造方法
の一実施例の工程を示す断面図である。FIGS. 8 to 8 are cross-sectional views showing steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.
まず第８図に示すようにトランジスタ等の半導体素子を
形成したＳｉ基板１１上に、所定パターンに窓開きした
５ｉＱ２膜稔をＳｉ基板の熱酸化法お等を用いて形成す
る。First, as shown in FIG. 8, on a Si substrate 11 on which semiconductor elements such as transistors are formed, a 5iQ2 film having windows in a predetermined pattern is formed using a Si substrate thermal oxidation method or the like.
次いで該基板１１上全面に多結晶Ｓｉ膜１３をＣＶＤ法
により形成する。Next, a polycrystalline Si film 13 is formed over the entire surface of the substrate 11 by CVD.
その後第９図に示すように該Ｓｉ基板１１上の全面に白
金膜１４をスパッタ法または蒸着法を用いて形成する。Thereafter, as shown in FIG. 9, a platinum film 14 is formed on the entire surface of the Si substrate 11 by sputtering or vapor deposition.
ここで前述した多結晶Ｓｉ膜１３を、後の工程で形成す
るＡｌ′電極の形にそうようにあらかじめエツチングし
ないで、該多結晶Ｓｉ膜１３上全面に白金膜１４を形成
するのが従来の方法と異なる点である。Here, it is conventional practice to form the platinum film 14 on the entire surface of the polycrystalline Si film 13 without etching the polycrystalline Si film 13 described above in advance in the form of an Al' electrode to be formed in a later step. This is different from the method.
その後、基板を約４５０°Ｃの温度で：幻分間望累ガス
零囲気中で熱処理して、前記白金膜１４と下部の一部の
多結晶Ｓｉ膜１３を反応させ白金シリサイド膜を形成す
る。Thereafter, the substrate is heat-treated at a temperature of about 450° C. in a zero atmosphere of phantom gas to cause the platinum film 14 and a portion of the lower polycrystalline Si film 13 to react to form a platinum silicide film.
次いで第１０図に示すようにこのようにして形成した該
白金シリサイド膜１５上に電化チタニウム膜１６を蒸老
またはスパッタ法で形成後、その上に配線膜となるＡＩ
膜１７を蒸着またはスパッタ法で形成する。Next, as shown in FIG. 10, an electrified titanium film 16 is formed on the platinum silicide film 15 formed in this manner by an evaporation method or a sputtering method, and then an AI film that will become a wiring film is deposited on top of the electrified titanium film 16.
The film 17 is formed by vapor deposition or sputtering.
その後、第１１図に示すように該基板上にホ） ＩＪソ
グラフイ法、プラズマエツチング法を用いて所定パター
ンのホトレジスト膜１８をマスクとしてまずＢＯＡ’３
ガスを反応ガスとしてプラズマエツチング法を用いて下
部のＡ［配線膜１７および窒化チタン膜１６を所定パタ
ーンに形成する。Thereafter, as shown in FIG. 11, BOA'3 is first etched onto the substrate using a predetermined pattern of photoresist film 18 as a mask using IJ lithography and plasma etching.
The lower A[wiring film 17 and titanium nitride film 16] are formed into a predetermined pattern using a plasma etching method using gas as a reactive gas.
次いで第臆図に示すように、白金シリサイド膜１５を数
１００ｅＶに加速されたＡｒイオンビームを用いてスパ
ッタ効果を利用したエツチングをし、最後にＯＦ４ガス
を用（ρて多結晶シリコン膜１３をエツチングする。Next, as shown in FIG. Etching.
このようにすれば従来の方法のように多結晶シリコン膜
と、その上の白金シリサイド膜、窒化チタン膜、Ａ、ｌ
配線膜の積層被膜とを２回に分けてマスク合せしていた
ものが、１回のマスク合せの工的
程でエツチングできるようになり、マスク合せの工程が
少なくなって製造に要する工数が低下する利点を有する
。In this way, unlike the conventional method, a polycrystalline silicon film, a platinum silicide film, a titanium nitride film, A, l
The wiring film and the laminated film, which used to be mask-aligned in two steps, can now be etched in a single mask-alignment process, reducing the number of mask-alignment steps and reducing the number of man-hours required for manufacturing. It has the advantage of
また従来の方法のように王水を用いて白金（Ｐｔ）膜を
あらかじめエツチングする工程が省略でき、エツチング
に薬品を導入することがなくなり、工程が簡略化できる
利点を生じる。Further, unlike the conventional method, the step of pre-etching the platinum (Pt) film using aqua regia can be omitted, and there is no need to introduce chemicals for etching, resulting in the advantage that the process can be simplified.
ここで本実施例においては、白金（ＰＢを例にチタン（
Ｔｉ ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）タン
グステンＣＷ）、ニッケル（ＮＩ）、ハフニウム（Ｈｆ
）、バナジウム（Ｖ）、などが挙げられる。In this example, platinum (PB is used as an example) and titanium (
Ti), molybdenum (Mo), tantalum (Ta) tungsten CW), nickel (NI), hafnium (Hf)
), vanadium (V), and the like.
この場合当然のことながら、金属シリサイド膜のエツチ
ング法は加速されたＡｒビームによるスパッタエツチン
グはかりでなく、金属シリサイドの種類により塩素系や
弗素系のガスを用いたり、リアクティブイオンエツチン
グを使用できる。In this case, as a matter of course, the method of etching the metal silicide film is not sputter etching using an accelerated Ar beam, but can use a chlorine-based or fluorine-based gas or reactive ion etching depending on the type of metal silicide.
きらに金属シリサイド膜の形成は、金属シリサイド膜を
形成する金属膜を形成した直後でも良く、バリア腺形成
後でも良く、また低温反応の可能なｐｔやｐｄなどはＡ
ｌ配線膜形成後でも良い。また配線用金属は金（Ａｕ
）でも良い。The metal silicide film may be formed immediately after forming the metal film that forms the metal silicide film, or after the formation of the barrier gland.
This may be done after the l wiring film is formed. The wiring metal is gold (Au).
) but that's fine.
（ｇ） 発明の効果
以北述べたように本発明の方法によれば、′電極形成に
おけるマスク合せの工程が短縮でき、パターンの微細化
が可能となる効果がある。(g) Effects of the Invention As described above, according to the method of the present invention, the process of mask alignment in electrode formation can be shortened, and the pattern can be made finer.
またウェットエツチングを用いなくてすむので工程が簡
略化できる。Further, since wet etching is not required, the process can be simplified.
第１図より第７図までは、従来の半導体装置の製造方法
の工程を示す断面図、第８図より第臣図までは本発明の
半導体装置の製造方法の工程を示す断面図である。
図において１，１１はＳｉ基板、２はエミッタ領域、３
，１２は５ｉＯｚ膜、４．４Ａ、１３は多結晶Ｓｉ膜５
．５Ａ、１４は白金膜、６，１５は白金シリサイド膜７
．１６は窒化チタニウム膜、８，１７はＡｌ配線膜１８
はレジスト膜を示す。
第１図
第２図
第６図
第Ｓ図 、３
第９ｆｆｌ1 to 7 are cross-sectional views showing the steps of a conventional semiconductor device manufacturing method, and FIGS. 8 to 7 are cross-sectional views showing the steps of the semiconductor device manufacturing method of the present invention. In the figure, 1 and 11 are Si substrates, 2 is an emitter region, and 3
, 12 is a 5iOz film, 4.4A, 13 is a polycrystalline Si film 5
．． 5A, 14 are platinum films, 6, 15 are platinum silicide films 7
．． 16 is a titanium nitride film, 8 and 17 are Al wiring films 18
indicates a resist film. Figure 1 Figure 2 Figure 6 Figure S, 3 9ffl
Claims (1)
板全面に多結晶シリコン膜を形成し、次いで該基板上に
シリコンと反応して、金属シリサイド膜を形成するよう
な第１の金属膜を形成後、該基板上に金属シリサイド膜
と配線用金属膜との反応を阻止する第２の被膜及び配線
用の第３の金属膜を順次積層形成し、第１の金属膜を形
成後に該基板を熱処理して、第１の金属膜と多結晶シリ
コン膜とを反応させて金属シリサイド膜を形成し、該金
属シリサイド膜を含めて該積層形成した被膜を絶縁膜に
到るまで所定のパターンにエツチングすることを特徴と
する半導体装置の製造方法。After forming an insulating film in a predetermined pattern on a silicon substrate, a polycrystalline silicon film is formed on the entire surface of the substrate, and then a first metal film that reacts with silicon to form a metal silicide film is formed on the substrate. After the formation, a second film for blocking the reaction between the metal silicide film and the metal film for wiring and a third metal film for wiring are sequentially laminated on the substrate, and after forming the first metal film, the substrate is heat-treated to cause the first metal film and polycrystalline silicon film to react to form a metal silicide film, and the laminated film including the metal silicide film is formed into a predetermined pattern up to the insulating film. A method of manufacturing a semiconductor device characterized by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5070383A JPS59175726A (en) | 1983-03-25 | 1983-03-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5070383A JPS59175726A (en) | 1983-03-25 | 1983-03-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59175726A true JPS59175726A (en) | 1984-10-04 |
Family
ID=12866258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5070383A Pending JPS59175726A (en) | 1983-03-25 | 1983-03-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59175726A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS625657A (en) * | 1985-07-01 | 1987-01-12 | Nec Corp | Semiconductor integrated circuit device |
| JPS6273711A (en) * | 1985-09-27 | 1987-04-04 | Nec Corp | Semiconductor device |
| JPS62132349A (en) * | 1985-11-27 | 1987-06-15 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | Improvement of stepped part |
| JPS62256455A (en) * | 1986-04-30 | 1987-11-09 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS62298167A (en) * | 1986-06-18 | 1987-12-25 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS6436023A (en) * | 1987-07-31 | 1989-02-07 | Sony Corp | Dry etching |
| JPH01289252A (en) * | 1988-02-22 | 1989-11-21 | Texas Instr Inc <Ti> | Improved method of forming local connection employing agent containing chlorine |
| US5453400A (en) * | 1990-06-28 | 1995-09-26 | International Business Machines Corporation | Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits |
| JPH07263556A (en) * | 1995-03-24 | 1995-10-13 | Hitachi Ltd | Semiconductor device |
-
1983
- 1983-03-25 JP JP5070383A patent/JPS59175726A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS625657A (en) * | 1985-07-01 | 1987-01-12 | Nec Corp | Semiconductor integrated circuit device |
| JPS6273711A (en) * | 1985-09-27 | 1987-04-04 | Nec Corp | Semiconductor device |
| JPS62132349A (en) * | 1985-11-27 | 1987-06-15 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | Improvement of stepped part |
| JPS62256455A (en) * | 1986-04-30 | 1987-11-09 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS62298167A (en) * | 1986-06-18 | 1987-12-25 | Hitachi Ltd | Semiconductor integrated circuit device |
| US5068710A (en) * | 1986-06-18 | 1991-11-26 | Hitachi, Ltd. | Semiconductor device with multilayer base contact |
| JPS6436023A (en) * | 1987-07-31 | 1989-02-07 | Sony Corp | Dry etching |
| JPH01289252A (en) * | 1988-02-22 | 1989-11-21 | Texas Instr Inc <Ti> | Improved method of forming local connection employing agent containing chlorine |
| US5453400A (en) * | 1990-06-28 | 1995-09-26 | International Business Machines Corporation | Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits |
| US5672901A (en) * | 1990-06-28 | 1997-09-30 | International Business Machines Corporation | Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits |
| JPH07263556A (en) * | 1995-03-24 | 1995-10-13 | Hitachi Ltd | Semiconductor device |
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