JPS62256455A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the Si substrate alloying reaction to Al due to unfavorable coating property of TiN from occuring by a method wherein a good junction layer is formed by burying a contact hole formed due to scraping with polycrystalline Si in a selfalignment manner and then inside of the contact hole that has come to have no excessive recession is coated with TiN. CONSTITUTION:An isolation region 2 comprising SiO2 is formed on the surface of P type Si substrate 1 and then an impurity region 3 is formed by ion implantation while a phosphorus silicate glass 4 is formed by chemical vapor growth. A contact hole reaching the surface of Si substrate is made using a resist 5 as a mask while a polycrystalline Si 6 is buried in the hole by low pressure chemical vapor growth and then phosphorus 7 is ion-implanted to form a phosphorus layer 8. Later, after annealing process, an excellent and deep N<+> diffused region 9 is formed in selfalignment below the contact hole using the rapid impurity diffusion peculiar to the polycrystalline Si and then the polycrystalline Si 6 is coated with a TiN 10 as a buffer layer to prevent Al and Si from combining with each other finally after coating with Al 11, three layers of Al, TiN and polycrystalline Si are etched.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a wiring structure that can make good contact with a diffusion layer formed on the surface of a semiconductor substrate, and a method for manufacturing the same.

[Conventional technology]

Conventional contact structures are described, for example, in Autumn 1985, p. 3.
As discussed in Section a-V-1, TiNt was deposited directly on top of the diffusion layer and then Al or A/compound was deposited thereon. The reason why it is sandwiched between TiNtk is that it acts as a barrier to alloying Al and Si.

[Problem that the invention seeks to solve]

The above conventional technology is a TiN deposition method (sputtering).
Due to this, insufficient consideration was given to poor coverage, resulting in small contact holes.

If the ratio of the depth to the opening area is large, the inside of the hole may not be completely covered with TiN. Furthermore, if the contact region 25 deviates from the diffusion layer 23 or 33 and enters the isolation Si0* 22, 33 as shown in the second crystal or FIG. Since the contact hole can be cut down to 5 inches, a deeper groove is formed inside the contact hole, and TiN cannot cover the inside of the hole.

Therefore, when AAl is buried on TiN, the IC, Si substrate and Al are directly connected! ! kA by contacting and subsequent annealing.
As the alloying of A/ and Si progresses, a defect may occur in which the alloyed A/, -Si passes through the diffusion layer and directly shorts with the Si substrate.

An object of the present invention is to provide a wiring that can make good contact with the diffusion layer without causing short-circuits between the Si substrate and the wiring even in the case where the contact region deviates from the diffusion layer and enters the isolation region as described above. The purpose is to provide a structure and its manufacturing method.

[Means for solving problems]

In order to achieve the above object, the present invention (1) deposits polycrystalline Si formed by low-pressure chemical vapor deposition, which has good coverage, in the contact hole, thereby creating a recess between the diffusion layer region and the isolation region; After filling the contact hole with polycrystalline Si′c, and forming a deep and good bond at the bottom of the contact hole by using the fast impurity diffusion characteristic of polycrystalline Si through ion implantation and annealing, ■ T1Ni deposition. death,
Finally, the method of ① Alt filling was used.

[Effect]

When the above method is used, since there is no extremely concave structure in the internal shape of the contact hole before TiNt is deposited, alloying of AA and 84 due to poor coverage of TiN and the resulting -! A
1 and the Si substrate shoot. Furthermore, TiN1
Since a deep and good bond is formed in the region, even if rationalization of Al and Si occurs, the alloyed region will hardly reach the Si substrate, which is effective in preventing short circuits.

〔Example〕

An embodiment of the present invention will be described below using a t-gt diagram.

FIG. 1 shows the manufacturing method of the present invention. First, in (1), an isolation region 2t using 5ins is formed on the surface of the p-type Si substrate 1, then a cine blunt region 3t is formed by ion implantation, and a silicic acid region 3t is formed by chemical vapor deposition. Glass 4 is formed. In (2), a contact hole extending to the surface of the Si substrate is formed using the anisotropic dry etching technique using the resist 5 as a mask. At this time, part of the isolation may be shaved off, creating a recess on the surface of the Si substrate, and the p-type Si substrate may be exposed. In order to fill this recess, in step (3), polycrystalline Si6 was filled using low-pressure chemical vapor deposition, and then a phosphor was ion-implanted.
Form a phosphorus layer 8t. (4) After that, annealing is performed to form a deep and good n0 diffusion layer region 9 in a self-aligned manner in the contact layer by utilizing the fast impurity diffusion of polycrystalline Si41F, and then to prevent the combination of Al and Si. After depositing 10t' of TiN as a barrier layer and then depositing AlII, the three layers of Al, TiN and polycrystalline Si are etched to form the structure shown.

In (4), if there is no polycrystalline Si6, the coverage of TiN is poor due to the deposition method (sputtering method), so TiN does not completely fill the recesses on the surface of the 8s substrate.
Therefore, an Al--Si compound 2 alloying may occur, resulting in a short circuit between Al and the substrate.

This short circuit is the conventional LOCO8 ([oc
al Qxtdatio of 5ilicon) was relatively less likely to occur. However, in embedded isolation (see Figure 3), silicon for isolation (
Since the slope of the H end portion is close to vertical, the diffusion layer 36 formed by ion implantation and single annealing is not substantially shallow, and short circuits are likely to occur. Therefore, there is a strong need to form a deep and good bond using the structure of this patent shown in FIG.

Figure 4 shows a slight variation of this patent. When the contact hole is relatively large and the diffusion layer 43 is also relatively deep as shown in FIG.

FIG. 5 shows the proportionality applied to a fully complementary integrated circuit according to the present invention. (1) is an n-type well 52pf on an n-type Si substrate 51.
fl well 53, isolation region 54, p0 type diffusion layer 55, n4'' diffusion layer 56. After forming phosphosilicate glass 57 and forming contact holes, polycrystalline 5i 58ft
A cross-sectional view formed by low-pressure chemical vapor deposition is shown. After that, in (2), the ln well is covered with a resist 59, and phosphorus 601 ions are implanted only onto the p well to form a phosphorus layer 61. Next, in (3), boron 763 is ion-implanted onto a region different from (2) to form a boron layer 6.
4 is formed. In (4), after forming the p+ diffusion layer 65 and the n* diffusion layer 66 by annealing, TiN6
A cross-sectional view of the result of depositing 7° A/6Si and forming wiring by etching is shown.

〔Effect of the invention〕

According to the present invention, when making contact with the diffusion layer on the surface of the BSS substrate, even if the contact region shifts and enters the isolation region and the isolation SiOmt is deeply cut, the cut hole is self-aligned with polycrystalline Si. Ti
This has the effect of preventing alloying reactions between Al and Si substrates caused by poor N coverage.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of the contact forming process and contact part using the present invention, Fig. 2 is a cross-sectional view of the contact part by the conventional process using LOCO8 for isolation, and Fig. 3 is a cross-sectional view of the contact part using the conventional process using LOCO8 for isolation. FIG. 4 is a cross-sectional view of an embodiment of the present invention without using a barrier layer, and FIG. 5 is a process 7 when the present invention is applied to a complementary integrated circuit.
0- and a cross-sectional view are shown. 1, 21. 31. 41...p-type Si substrate, 2,
22゜32.42.54...Si for isolation
αh3, 9. 23. 26. 33. 36. 4
3. 46°56.66...n1 diffusion layer, 55,65
...p11 diffusion, 4,24,34,44.57...
Phosphorsilicate glass, 5,59.62...Resist, 6
,45°58...Polycrystalline Si, 10.67...Ti
N, 11°27.37,47,6B...A, tl 7
,60...Lin. 8.61...Lymph m, 63...Boron, 64...
・Boron layer, 25...contact region, 51...n
Type Si substrate. Fist 1st day 2nd day 58 early,! ; Concave

Claims (1)

[Claims] 1. An impurity region 1 of the opposite conductivity type is provided on the surface of the Si semiconductor substrate containing impurities of the first conductivity type, and further an insulating region is provided on the region excluding at least a part of the surface of the Si substrate. Si substrate has a film layer, and the surface of the Si substrate without the insulating film has a self-aligned Si layer.
An impurity region 2 having a conductivity type opposite to that of the semiconductor substrate, and a polycrystalline S containing an impurity having a conductivity type opposite to that of the Si semiconductor substrate.
A semiconductor device characterized in that an i-layer, TiN, and Al are laminated in that order. 2. The semiconductor device according to claim 1, wherein a metal or a compound thereof that is less easily alloyed with Si than Al is used instead of TiN. 3. The semiconductor device according to claim 1, characterized in that an Al compound is used instead of Al. 4. The semiconductor device according to claim 1, which has Al directly on polycrystalline Si. 5. After forming an impurity region of the opposite conductivity type on the surface of the Si semiconductor substrate containing impurities of the first conductivity type by vapor phase diffusion or ion implantation, an insulating film is formed on the surface of the Si substrate by chemical vapor deposition. After forming a conductive hole extending to the surface of the Si substrate in at least a part of the insulating film, a polycrystalline Si region is formed on the entire surface by low pressure vapor phase epitaxy, and an impurity of the opposite conductivity type to that of the Si substrate is formed. 1. A method of manufacturing a semiconductor device, which comprises implanting ions into at least a region including the contact hole, forming a TiN region over the entire surface, and further forming an Al region thereon.