JPS60143648A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to form silicide electrodes even in shallow diffusion layers by a method wherein an impurity-added polycrystalline silicon layer is made to grow on the diffusion layers. CONSTITUTION:N type impurities are ion-implanted in a P type Si substrate 1 and diffusion layers 10 are formed. After that, oxide films 11 are removed and an N type impurity-added polycrystalline silicon layer 12 is made to grow on the whole surface by a CVD method in a film thickness of a degree that apertures 13 and 14 provided on the diffusion layers 10 are fully buried with the polycrystalline silicon layer 12. The polycrystalline silicon layer 12 is performed an etchback to the limit in such a way that the polycrystalline silicon layer 12 is left only in the apertures 13 and 14. Polycrystalline gates and the silicon nitride film 7 of the wiring part are removed, and after then, silicide layers 18, 16 and 17 are provided on N<+> type polycrystalline silicon layers 8, 13 and 14.

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

In the conventional Si (Si) MO8 process, wiring is patterned using polycrystalline 8i at the same time as gate formation, and then Al wiring is formed using polycrystalline 8i.
A two-layer wiring technology of aluminum and aluminum is used. However, this polycrystalline 8i wiring has the disadvantage that the step coverage of the step portion of the polycrystalline 8i wiring of the interlayer insulating film formed thereon by the CVD method is poor, and step breaks in the Al wiring occur. Further, impurities are usually included in the polycrystalline 8i in order to lower the resistance, but in reality, there are limits to lowering the resistance due to process problems and the like.

Recently, a technique has been used to reduce the resistance by depositing a specific metal on polycrystalline Si and forming a silicide compound with the polycrystalline Si.
As an application of this, attempts have been made to lower the resistance by forming a silicide electrode not only on the gate portion but also on the diffusion layer. However, to form a silicide compound,
A corresponding amount of silicon is consumed by the metal deposited, and
Because the metal has a large diffusion coefficient, it penetrates deeply into silicon and becomes alloyed when it is silicided. Therefore, there is no problem with deep diffusion layers, but if the diffusion layer is shallow, there is a risk that this metal will penetrate through the diffusion layer and become a Schottky diode. Recently, shallow diffusion layers have been required in response to shortened channels, so it is difficult to apply the conventional method as is for the reasons mentioned above.

In the present invention, the polycrystalline 84 doped with impurities on the diffusion layer is
The above problems are solved by growing the source using the D (chemical vapor deposition) method.

This provides a low-resistance semiconductor device using silicide electrodes for the drain and gate.

To put it simply, the essence of this invention is that polycrystalline silicon grown uniformly on a semiconductor substrate whose predetermined surface is covered with a field oxide film and which covers the device region in a predetermined portion is separated into the device region and the wiring region using a silicon nitride film. Then, by performing selective oxidation, a thick field oxide film is formed together with the underlying field oxide film, and the polycrystalline silicon wiring is separated by an oxide film, that is, it is buried in the oxide film. do. Thereafter, a gate portion is formed by anisotropic dry etching of polycrystalline silicon, a diffusion layer is formed by ion implantation, and then a diffusion layer is formed by ion implantation.

The mask oxide film on the diffusion layer is removed using anisotropic dry etching. After a predetermined process for dry etching, polycrystalline silicon doped with impurities is then processed by CVD.
The polycrystalline silicon is grown to a thickness that completely fills the openings above the diffusion layer, and is etched back by isotropic etching so that the impurity-doped polycrystalline silicon remains only on the diffusion layer.

Thereafter, the nitride film on the polycrystalline silicon of the gate portion and wiring portion is removed, and a conventional silicide electrode formation process is performed.

According to this method, it is possible to form a silicide electrode even in a shallow diffusion layer, and the electrode area can be made as large as the diffusion layer region, so that the contact resistance is small. Also,
Since impurity-doped polycrystalline silicon having a predetermined thickness is formed on the diffusion layer, there is little difference in level from the gate electrode, which is effective for burying the polycrystalline silicon wiring portion and for planarization.

Next, the present invention will be explained in more detail with reference to the drawings.

Examples in which the present invention is applied to an N-type conductivity type silicon (MO8) process are shown in FIGS. 1 to 6.

(1) As shown in FIG. 1, a p-type Si substrate 1 is used to perform selective oxidation to form an element region, and a gate oxide film 6 is formed in the element region. And CVD on the entire surface
Polycrystalline Si3 is grown by the method, and N-type impurities are diffused into it. Thereafter, a silicon nitride film is grown by the same CVD method, and the resist on the element region portion 5 and polycrystalline silicon interconnection portion 6 is left by photolithography.

Then, a silicon nitride film 5.6 is left by dry etching.

(2) After the silicon nitride film has been patterned as in step 1, selective oxidation of the polycrystalline silicon is performed as shown in FIG. It should be in contact with the oxide film 2. Polycrystalline silicon wiring 8 is thus formed, and the silicon nitride film on the diffusion layer is removed by photolithography.

(3) As shown in FIG. 3, the polycrystalline silicon on the diffusion layer is removed by anisotropic dry etching to expose the gate oxide film 6. Here, the side surfaces of the polycrystalline silicon in the gate portion are oxidized, and N-type impurity ions are implanted to form the diffusion layer 10.

(4) After annealing after ion implantation, Fig. 4
As shown in FIG. 3, the oxide film 11 on the diffusion layer is removed again by anisotropic dry etching. Next, polycrystalline silicon doped with N-type impurities is grown on the entire surface using the CVD method.
The film thickness is made so that the openings 13° and 14 on the diffusion layer are sufficiently filled. At this time, the smaller the openings 13, 14, the smaller the openings 13, 14.
It is easy to fill in 4.

(5) Etch back the polycrystalline silicon layer 6-12 by isotropic etching, as shown in FIG.
The polycrystalline silicon layer is left only in the openings 13 and 14. Then, the polycrystalline silicon gate and the silicon nitride film of the wiring part are removed, and the metal used for silicide is deposited.
A subsequent heat treatment forms silicide.

FIG. 6 shows an example of a completed drawing manufactured by applying the above method. That is, N+ type polycrystalline silicon 8, 13
．． Silicide layers 18, 16.degree. 17 are provided on 14, an interlayer insulating film 20 through which Al wiring passes is provided at a predetermined portion, and the top thereof is further covered with a cover oxide film 21.

The present invention is not limited to the above-mentioned embodiments, and for example, trench isolation methods can be applied instead of selective oxidation methods in element isolation methods.

As detailed above, according to the present invention, by growing an impurity-doped polycrystalline silicon layer on the diffusion,
A silicide electrode can be formed even in a shallow diffusion layer, and since there is little difference in level from the gate electrode, it is effective for planarization.

is a completed cross section of the semiconductor device according to the present invention (1...
P-type 8i substrate, 2...Field oxide film, 3.
...N-type polycrystalline silicon layer, 4,5...
Si3N4 film, 8402 film for 6-"K-), 7-
8i3N4 film, 8... polycrystalline silicon layer for wiring, 9... field 8i02 film, 10...
...N-type diffusion layer, 11...8i0. membrane, 12.
...N-type polycrystalline silicon layer, 13.14...
...Opening above the diffusion layer, 15...Field 8i0
．． Film, 16° 17.18 Old... Silicide layer, 19°
°°...Al wiring, 20...Interlayer insulating film (P
EG), 21...Cover oxide film.

Ftj, / F,! , Z f β- F; s, 4-F, j, Shio procedural amendment (formality) 60.2.12 Showa I6 Tow month Date Commissioner of the Japan Patent Office 1, Indication of case 1982 Patent application No. 153882
No. 2, Title of the invention Method for manufacturing semiconductor devices 3, Relationship to the amended person's case Applicant 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative Tadahiro Sekimoto 4, Agent Telephone Tokyo (03) 456-3111 (main representative) 6 Column 7 “Brief explanation of one drawing of the specification subject to amendment” 7 Line 2 of page 8 of the specification of contents of the amendment (”Fig, 1 to Fig. 5
J was corrected as “Figures 1 to 5” and “Fi” on the third line of the same page
g, 6 J is revised to “Figure 6”.

, m-″, Agent: Patent attorney Susumu Uchihara ・′

Claims (1)

[Claims] An insulating film is formed on a first conductivity type single crystal silicon substrate,
A first polycrystalline silicon is grown on the insulating film to form a MOS)
The first polycrystalline silicon other than the regions to be transistors and wiring is selectively oxidized to silicon dioxide, and MO
S) After removing the first polycrystalline silicon and the insulating film in the regions that will become the source and drain of the transistor, impurities of a second conductivity type are introduced to form a second polycrystalline silicon of the second conductivity type on the surface. The second polycrystalline silicon is left only in the source and drain regions, and the first and second polycrystalline silicon are silicided to form a second polycrystalline silicon between the source and drain regions and the silicide electrodes. 1. A method of manufacturing a semiconductor device, characterized in that silicide electrodes are formed in regions that will become sources and drains with silicon interposed therebetween.