JPH0580139B2 - - Google Patents
Info
- Publication number
- JPH0580139B2 JPH0580139B2 JP59240449A JP24044984A JPH0580139B2 JP H0580139 B2 JPH0580139 B2 JP H0580139B2 JP 59240449 A JP59240449 A JP 59240449A JP 24044984 A JP24044984 A JP 24044984A JP H0580139 B2 JPH0580139 B2 JP H0580139B2
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- wiring
- film
- low
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 230000006911 nucleation Effects 0.000 claims description 9
- 238000010899 nucleation Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 description 12
- 229910018125 Al-Si Inorganic materials 0.000 description 6
- 229910018520 Al—Si Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 229910021140 PdSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は超LSIにおける電極配線の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing electrode wiring in a VLSI.
（従来の技術）
256KDRAMで代表される従来のLSIの電極・
配線には拡散層深さが0.3μｍ以上と深いので、主
としてAl−Siが用いられてきた。(Conventional technology) Conventional LSI electrodes represented by 256KDRAM
Since the depth of the diffusion layer is as deep as 0.3 μm or more, Al-Si has been mainly used for wiring.
しかしながら、1MDRM以降の超LSIの場合、
拡散層深さが0.2μｍ以下と浅くなり、かつ段差も
微細化や反応性ドライエツチ（RIE）の全面採用
でますます急峻となるのは必至である。 However, in the case of ultra-LSIs after 1MDRM,
It is inevitable that the depth of the diffusion layer will become shallower, less than 0.2 μm, and that the steps will become even steeper due to miniaturization and the full adoption of reactive dry etching (RIE).
一方、Si拡散層から直接、Al−Siで電極を取
り出す方法は深い接合に対しては有効であつた
が、0.2μｍ以下の浅い接合の場合、電極形成後の
熱処理工程での温度、時間やAl−Si配線の幅、
厚さ、あるいはAl−Si中のSi含有量によりAlス
パイクが接合を破壊することが指摘されている。
したがつて、Al−Siは〜0.3μｍ接合がほぼ限界
で、浅い接合用電極としてはAl−Siに代わるメ
タルを使う必要がある。 On the other hand, the method of taking out Al-Si electrodes directly from the Si diffusion layer was effective for deep junctions, but in the case of shallow junctions of 0.2 μm or less, the temperature and time required in the heat treatment process after electrode formation Width of Al-Si wiring,
It has been pointed out that Al spikes can destroy the bond depending on the thickness or the Si content in Al-Si.
Therefore, the limit for Al-Si is approximately 0.3 μm junction, and it is necessary to use a metal instead of Al-Si as a shallow junction electrode.
（発明が解決しようとする問題点）
一方、従来の蒸着法やスパツタ法は等方向にメ
タル粒子が飛翔するので、1MDRAM以降の急峻
な、かつアスペクト比の大きい段差でのメタルの
ステツプカバレージ性は非常に悪く、配線の断切
れ、あるいはエレクトロマイグレーシヨンを起こ
す可能性が高い。(Problem to be solved by the invention) On the other hand, in the conventional vapor deposition method and sputtering method, metal particles fly in the same direction, so step coverage of metal at steep steps with a large aspect ratio after 1MDRAM is This is very bad, and there is a high possibility that the wiring will break or electromigration will occur.
このアスペクト比は第３図に示す窓幅（孔径）
Ｗ（μｍ）と高さＨの比、すなわちＨ／Ｗで定義
される。この比が高いと孔径に対して高さが高い
ことを意味する。 This aspect ratio is the window width (hole diameter) shown in Figure 3.
It is defined by the ratio of W (μm) to height H, that is, H/W. A high ratio means that the height is high relative to the pore diameter.
このアスペクト比が大きいと、ステツプカバレ
ージ性の一層の改善が不可欠となつている。 When this aspect ratio is large, further improvement in step coverage is essential.
この発明は前記従来技術がもつている問題点の
うち、浅い接合に対するAlスパイクによるリー
ク電流の発生と急峻な段差でのステツプカバレー
ジ性の悪化点について解決した電極配線の製造方
法を提供するものである。 This invention provides a method for manufacturing electrode wiring that solves the problems of the prior art described above, such as the occurrence of leakage current due to Al spikes in shallow junctions and the deterioration of step coverage due to steep steps. be.
（問題点を解決するための手段）
この発明は、中間絶縁膜にコンタクト孔を形成
し、該コンタクト孔底部に、Alに核生成密度が
前記中間絶縁膜より大のバリヤメタルを形成し、
その後低圧CVD法でAl配線材としてのAlを堆積
させるようにしたものである。(Means for Solving the Problem) This invention forms a contact hole in an intermediate insulating film, forms a barrier metal in Al with a higher nucleation density than the intermediate insulating film at the bottom of the contact hole,
After that, Al was deposited as an Al wiring material using a low-pressure CVD method.
（作用）
上記この発明においては、低圧CVD法でAl配
線材としてのAlを堆積させている。その際、コ
ンタクト孔においては、該コンタクト孔が形成さ
れた中間絶縁膜よりAlの核生成密度が大なバリ
ヤメタルを底部に形成してある。上記Alの低圧
CVD法は下地の表面状態に敏感で、核生成密度
の大きい下地膜上ではAlの堆積速度が大きく、
核生成密度が小さい下地膜の上では堆積速度が小
さくなる。したがつて、コンタクト孔底部に核生
成密度が大きい上記バリヤメタルを形成したこの
発明においては、コンタクト孔部分でのAlの堆
積速度が大きく、Alが厚く成長し、それ以外で
は薄く成長するもので、その結果として段差が急
峻で且つアスペクト比が大きいコンタクト孔でも
ステツプカバレージが向上し、平坦なAl配線を
形成できる。(Function) In the present invention described above, Al as an Al wiring material is deposited by a low-pressure CVD method. In this case, a barrier metal having a higher Al nucleation density than the intermediate insulating film in which the contact hole is formed is formed at the bottom of the contact hole. Low pressure of above Al
The CVD method is sensitive to the surface condition of the base, and the deposition rate of Al is high on the base film with a high nucleation density.
The deposition rate is low on the base film where the nucleation density is low. Therefore, in this invention, in which the barrier metal with a high nucleation density is formed at the bottom of the contact hole, the deposition rate of Al is high in the contact hole portion, and the Al grows thickly, and grows thinly in other areas. As a result, step coverage is improved even in a contact hole with a steep step and a large aspect ratio, and a flat Al wiring can be formed.
なおこのようなAlの堆積速度の下地依存性は、
Alの低圧CVD法特有な効果であり、プラズマ
CVD法では下地材質による堆積速度の差は現れ
ない。何故ならば、低圧CVD法が本質的に表面
反応型なのに対して、プラズマCVD法は気相反
応型であるからである。また、Alの蒸着法でよ
堆積速度の下地依存性が得られないことは周知で
ある。 The dependence of the Al deposition rate on the substrate is
This is an effect unique to the low-pressure CVD method for Al, and the plasma
With the CVD method, there is no difference in deposition rate depending on the underlying material. This is because the low-pressure CVD method is essentially a surface reaction type, whereas the plasma CVD method is a gas phase reaction type. Furthermore, it is well known that Al vapor deposition does not allow deposition rate to depend on the substrate.
（実施例）
以下、この発明の電極配線の製造方法の実施例
について説明する。(Example) Hereinafter, an example of the method for manufacturing an electrode wiring of the present invention will be described.
浅い接合用電極としてはTi、TiSi2、WSi2、ポ
リーSi、PtSi、PdSiなどが知られており、Al配
線と組み合せて、Ti／Al、Ti／Ｗ／Al、Pt／
Ti／Ｗ／Alなどが超LSI用電極配線として検討さ
れている。 Ti, TiSi 2 , WSi 2 , poly-Si, PtSi, PdSi, etc. are known as shallow bonding electrodes, and in combination with Al wiring, Ti/Al, Ti/W/Al, Pt/
Ti/W/Al etc. are being considered as electrode wiring for VLSI.
そこで、この発明はバリヤメタルとAl配線の
最適な組合せでステツプカバレージ性のすぐれた
浅接合用電極配線を製造する方法であり、Alの
低圧CVD法は下地材質の表面状態に敏感で、第
２図（低圧CVD Al膜の下地材質依存性）の堆積
時間対厚さ特性図に示すごとく、Alの核生成密
度の大きい単結晶Si、非結晶Si、Ti、Ｗは核生
成密度の小さいSiO2、PSGより堆積速度が大き
い。したがつて、堆積速度の差を利用して、ステ
ツプカバレージ性の良好な電極配線を形成できる
ようにしている。 Therefore, this invention is a method for manufacturing electrode wiring for shallow junctions with excellent step coverage using an optimal combination of barrier metal and Al wiring.The low-pressure CVD method for Al is sensitive to the surface condition of the underlying material, and as shown in Figure 2. As shown in the deposition time vs. thickness characteristic diagram (dependence on underlying material of low-pressure CVD Al film), single crystal Si, amorphous Si, Ti, and W, which have a high nucleation density of Al, are compared to SiO 2 , which has a low nucleation density, Deposition rate is higher than PSG. Therefore, by utilizing the difference in deposition rate, electrode wiring with good step coverage can be formed.
次に、この発明の電極配線の製造方法の実施例
について具体的に第１図ａ、第１図ｂにより説明
する。まず、第１図ａに示すように、Si基板１上
にLOCOS工程によりフイールドSiO2膜２を形成
した後、アクテイブ領域にゲート絶縁膜３および
ゲート電極４を形成する。 Next, an embodiment of the method for manufacturing electrode wiring according to the present invention will be specifically described with reference to FIGS. 1a and 1b. First, as shown in FIG. 1A, a field SiO 2 film 2 is formed on a Si substrate 1 by a LOCOS process, and then a gate insulating film 3 and a gate electrode 4 are formed in an active region.
次いで、As+をイオン注入し、ソース・ドレイ
ン拡散層５を形成する。その上に中間絶縁膜とし
てPSG膜６を堆積し、ソース・ドレインコンタ
クト孔７を開ける。 Next, As + ions are implanted to form source/drain diffusion layers 5. A PSG film 6 is deposited thereon as an intermediate insulating film, and source/drain contact holes 7 are opened.
しかる後に、リフトオフ法、Si上にのみメタル
を堆積させる選択CVD法、あるいはSi上のメタ
ルシリサイド層とPSG膜上のメタルのエツチレ
ート差を利用した選択エツチ法のいずれかの方法
によりコンタクト孔７底部に1000Å程度のバリヤ
メタル８、たとえばＷを形成する。 After that, the bottom of the contact hole 7 is etched by either a lift-off method, a selective CVD method that deposits metal only on the Si, or a selective etching method that utilizes the etching rate difference between the metal silicide layer on the Si and the metal on the PSG film. A barrier metal 8, for example W, is formed to a thickness of about 1000 Å.
次に、第１図ｂに示すように、トリイソブチル
アルミニウム（TIBA）ガスをArキヤリヤガス
で低圧CVD反応管内に導入し、ドープ温度270
℃、反応圧3Torrの条件でCVD Al配線９を60分
堆積させる。 Next, as shown in Figure 1b, triisobutylaluminum (TIBA) gas was introduced into the low-pressure CVD reaction tube using Ar carrier gas, and the doping temperature was 270.
CVD Al wiring 9 is deposited for 60 minutes at a temperature of 3 Torr and a reaction pressure of 3 Torr.
この場合、第２図より明らかなようにＷの方が
SiO2より堆積速度が大きいので、コンタクト孔
７部分には平坦部より厚くAl配線９が堆積する
ので、ステツプカバレージの良い電極配線が形成
される。 In this case, as is clear from Figure 2, W is better
Since the deposition rate is higher than that of SiO 2 , the Al wiring 9 is deposited thicker in the contact hole 7 area than in the flat area, so that an electrode wiring with good step coverage is formed.
一例として、PSG膜６に設けたSi底面のコンタ
クト孔７をもつ段差でのステツプカバレージ性を
従来のスパツタ法と比較して第３図に示す。 As an example, FIG. 3 shows a comparison of step coverage at a step with a contact hole 7 on the bottom surface of Si provided in a PSG film 6 with a conventional sputtering method.
この第３図より明らかなように、スパツタAl
よりかなりステツプカバレージがすぐれており、
同じCVD Al膜でもAl膜厚が大きい方がコンタ
クト孔７部分と平坦部上でのAl膜厚差が大きく
なるので、ステツプカバレージは一層良くなつて
いる。 As is clear from Fig. 3, sputtered Al
It has significantly better step coverage than
Even with the same CVD Al film, the larger the Al film thickness, the greater the difference in Al film thickness between the contact hole 7 portion and the flat portion, resulting in better step coverage.
したがつて、コンタクト孔底部の材質と平坦部
材質を適切に選び、これらの上に堆積するAl膜
厚差が段差高さに相当するだけ堆積させれば、コ
ンタクト孔７は完全にAlで埋まり、平坦なAl配
線９が形成されることになる。これをバイア・ホ
ール・フイル（Via hole fill）技術と言う。 Therefore, if the material for the bottom of the contact hole and the material for the flat member are appropriately selected, and the difference in thickness of the Al film deposited on these is equivalent to the height of the step, the contact hole 7 will be completely filled with Al. , a flat Al wiring 9 is formed. This is called via hole fill technology.
たとえばPSG膜６にSi底面の深さ1μｍのコン
タクト孔を有する場合のバイア・ホール・フイル
条件は堆積速度差が第２図より0.35μｍ／50分で
あるから
1.0μｍ÷（0.35μｍ／50分）150分
150分堆積させればよいことになる。 For example, when the PSG film 6 has a contact hole with a depth of 1 μm on the Si bottom surface, the via-hole-fill conditions are as follows: 1.0 μm ÷ (0.35 μm/50 minutes) since the deposition rate difference is 0.35 μm/50 minutes from Figure 2. ) 150 minutes 150 minutes is sufficient.
（発明の効果）
以上詳細に説明したようにこの発明によれば、
Alの核生成密度が中間絶縁膜より大のバリヤメ
タルをコンタクト孔底部に形成した後、Alの低
圧CVD法で、該低圧CVD法特有なAlの堆積速度
の下地依存性を利用してAlを堆積させるように
したので、段差が急峻で且つアスペクト比が大き
いコンタクトホールでもステツプカバレージが向
上し、平坦なAl配線を形成することができる。
また、前記バリヤメタルによりAlスパイクも防
止でき、浅い接合においてもリーク電流の発生を
防止できる。(Effect of the invention) As explained in detail above, according to this invention,
After forming a barrier metal with a higher Al nucleation density than the intermediate insulating film at the bottom of the contact hole, Al is deposited using a low-pressure CVD method that utilizes the dependence of Al deposition rate on the substrate, which is unique to the low-pressure CVD method. As a result, step coverage is improved even in a contact hole with a steep step and a large aspect ratio, and a flat Al wiring can be formed.
Furthermore, the barrier metal can prevent Al spikes, and can also prevent leakage current from occurring even in shallow junctions.
第１図はこの発明の電極配線の製造方法の一実
施例の工程断面図、第２図は低圧CVD Al膜の下
地材質依存性を示す図、第３図は従来のスパツタ
Al膜とCVD Al膜のステツプカバレージ性の比
較を示す図である。
１……Si基板、６……PSG膜、７……コンタク
ト孔、８……バリヤメタル、９……CVD Al配
線。
Fig. 1 is a process cross-sectional view of an embodiment of the electrode wiring manufacturing method of the present invention, Fig. 2 is a diagram showing the dependence of the low-pressure CVD Al film on the base material, and Fig. 3 is a diagram showing the dependence of the base material of the low-pressure CVD Al film.
FIG. 3 is a diagram showing a comparison of step coverage properties of an Al film and a CVD Al film. 1...Si substrate, 6...PSG film, 7...contact hole, 8...barrier metal, 9...CVD Al wiring.
Claims (1)
コンタクト孔を形成する工程と、 前期コンタクト孔底部に、Alの核生成密度が
前記中間絶縁膜より大のバリヤメタルを形成する
工程と、 前記コンタクト孔を含む前記中間絶縁膜上に
Al配線材としてのAlを低圧CVD法で堆積させる
工程とを具備してなる電極配線の製造方法。[Claims] 1. A step of forming an intermediate insulating film on a semiconductor substrate and forming a contact hole therein, and forming a barrier metal having a higher Al nucleation density than the intermediate insulating film at the bottom of the contact hole. on the intermediate insulating film including the contact hole.
A method for manufacturing an electrode wiring comprising a step of depositing Al as an Al wiring material by a low-pressure CVD method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24044984A JPS61120469A (en) | 1984-11-16 | 1984-11-16 | Manufacture of electrode wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24044984A JPS61120469A (en) | 1984-11-16 | 1984-11-16 | Manufacture of electrode wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61120469A JPS61120469A (en) | 1986-06-07 |
| JPH0580139B2 true JPH0580139B2 (en) | 1993-11-08 |
Family
ID=17059663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24044984A Granted JPS61120469A (en) | 1984-11-16 | 1984-11-16 | Manufacture of electrode wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61120469A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2554634B2 (en) * | 1986-09-29 | 1996-11-13 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPH031545A (en) * | 1989-05-29 | 1991-01-08 | Sony Corp | Mis transistor and manufacture thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57120370A (en) * | 1981-01-19 | 1982-07-27 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS5847464A (en) * | 1981-09-14 | 1983-03-19 | Yamaho:Kk | Seasoning and its preparation |
-
1984
- 1984-11-16 JP JP24044984A patent/JPS61120469A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57120370A (en) * | 1981-01-19 | 1982-07-27 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS5847464A (en) * | 1981-09-14 | 1983-03-19 | Yamaho:Kk | Seasoning and its preparation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61120469A (en) | 1986-06-07 |
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