JPS62132349A - Improvement of stepped part - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates generally to integrated circuit fabrication methods, and more particularly to:
A method for improving step coverage in very large scale integration (VLSI) semiconductor die fabrication.

DESCRIPTION OF RELATED ART Research and development of VLS technology in integrated circuit fabrication allows the geometries of individual components to be reduced to improve performance and save chip area for better manufacturing yields. A semiconductor chip was produced. One of the problems inherent in the extremely small dimensions of the die is that the interconnections of the individual components are formed on the individual active components in the layers where one or more contact holes per component are formed. This is because it requires filling. These holes, also known as "contact windows" and "holes," lead, typically through an insulator, to the contact area of each active element to be electrically coupled. That is,
Although a semiconductor die appears flat to the naked eye, it actually has a non-planar perimeter.

Currently, the reduction is done horizontally, and the vertical dimension is
It is not scaled proportionally.

This creates a very serious problem in the fabrication process, commonly referred to as "step covering." In VLSr, the horizontal dimension to the surface area of the component is currently approaching the 1 micron range, and submicron dimension measurements are considered as a breakthrough target. However, the vertical height or depth of the hole may not follow this scaling due to deleterious phenomena such as parasitic tolerance effects.

The standard electrical interconnect mechanism in the current state of the art is essentially a patterned thin film of metal. Method steps for forming interconnects are generally referred to as “metallization”
It is called. In particular, commonly used metallization methods include
To complete the desired interconnections between the various components, silicon dioxide (SiO2) is created throughout the chip area and etched holes leading to the substrate diffusion regions, polysilicon lines, and underlying metal lines. "
It is the sputtering of a metal layer onto an insulator layer (such as a metal oxide).

As shown in FIG. 1, the relatively deep contact holes in VLS I dice are not suitable for sputtered metal films that provide adequate step coverage.

The result is insufficient step coverage. Inadequate step coverage results in both poor reliability and many non-working devices formed on the wafer, ie, low manufacturing yield.

If the metallization is a layer of interstructure, the problem of step coverage is exacerbated in later produced layers unless planarization is performed on the metal layer.

One way to overcome insufficient step coverage is to attempt to planarize the metallization layer after it is formed. This method is a relatively high temperature method. High temperatures can have deleterious consequences for the semiconductor layers in which active components are formed. One such result is the lateral and vertical extent of the doped regions. In bipolar transistors, for example, the extrinsic base region may extend through the intrinsic base region and into the emitter region, or the junction depth may extend toward a buried collector region, resulting in lower breakdown. It may generate voltage. In both metal oxide semiconductor (MOS) and bipolar devices, impurity migration can occur during heating cycles.

Another method is to use high temperature after contact etching to create a relatively high phosphorus (P) focus in the oxide layer and smooth the corners of the contact hole. Again, a disadvantage is the undesired high temperature cycling after the formation of the source/drain of the MOS transistor. The entire structure retains a relatively poor surface contour for subsequent metallization methods. To overcome the high temperature requirements for P-type doped oxides, the oxides contain boron (B) and phosphorus (
P) can be doped with both. However, this introduces difficulties in method control of the composition of the oxide film.

Yet another method is to employ etching techniques that produce tapered holes. However, this method requires very delicate masking operations. Reproducibility of such techniques is difficult to achieve.

Still other methods have been developed to improve step coatings by employing gas phase reactions at low pressure, ie, low pressure chemical vapor deposition (LPGVD) methods. however,
LPGVD metals suffer from high resistivity and lack of film toughness uniformity.

Other ways to improve step coverage are described in 310 July 1985.
No. 761,206 (Sander), commonly assigned to the present application, doped polysilicon plug and etchback planarization techniques.

Generally, insufficient step coverage forces semiconductor chip manufacturers to use technology opposite to VLSI.

As an example, a p-type region may be provided in an n-type well,
and have internally sloped sidewalls, i.e. relatively wide, so that a high precision alignment of the holes is guaranteed, such as for complementary MOS (CMOS) devices where contacts have to be made only to the p-type region. Holes are designed to protect the counter and reduce spacing.

Due to the shallow junction depth of the doped region of the semiconductor substrate, a related problem of "spiking"
This can occur in LSI devices. When metals such as aluminum come into direct contact, atoms of the metal can migrate through the bond to lower layers of the component structure. This also results in yield and reliability losses.

Therefore, there is a need for improved step coverings that provide superior resistance contacts and have better shrinkability for integrated circuit fabrication technology.

SUMMARY OF THE INVENTION It is an object of this invention to provide improved step coverage for VLS I integrated circuits.

Another object of the invention is to improve integrated circuit reliability, performance and manufacturing yield.

Yet another object of the invention is to provide a relatively low temperature integrated circuit fabrication method for forming conductive hole plugs such that thermal effects in prefabricated die areas are minimized. be.

Yet another object of the invention is to provide better surface contours for subsequent metallization processes that alleviate masking operations for metal patterning processes.

In its basic aspects, the present invention provides an improved method for forming conductive plugs in contact holes overlying active component areas in semiconductor integrated circuit dice. A layer of amorphous semiconductor material, such as polysilicon for silicon-based chips, is formed to substantially fill the contact holes. In a preferred embodiment, the filler is doped to improve conductivity. A layer of refractory metal is formed over the polysilicon. The polysilicon and refractory metal are reacted by annealing, thereby creating a polycide material that substantially extends into the holes. The resulting structure is then removed to a predetermined extent leaving a conductive polycide plug in the hole.

Later metal interconnect layers thereby provide better step coverage. Various embodiments are disclosed in which conductive polysilicon or polycide plugs are formed.

An advantage of the invention is that the method provides substantially uniform hole plugs and can be used for contact windows of a wide variety of sizes.

Another advantage of this invention is that the fabrication nibs for the various layers are The objective is to minimize harmful consequences to

Yet another advantage of the present invention is that decision point detection for etching is more accurate because the polycide etch rate is selective on polysilicon or oxide.

Other objects, features and advantages of the invention will become apparent upon consideration of the following detailed description and accompanying drawings, in which like reference numerals indicate like features throughout the figures.

The drawings referred to in this description are to be understood as not being drawn to scale unless specifically noted. Furthermore, the drawings are intended to illustrate only a portion of an integrated circuit made in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to specific embodiments of this invention, which illustrate the best mode presently contemplated by the inventors for carrying out the invention. Alternative embodiments are also briefly described.

It should be appreciated that there are many publications detailing common techniques used in the fabrication of integrated circuit components. For example, Fairchild Corporation
) was copyrighted in 1979 by Reston Publishing e-Company.

Incoholated (Reston Publicis)
``Semiconductor and Integrated Circuit Manufacturing Technology J (Semiconductor
& Integrated C1rcuit F
See abduction techniques). Those techniques can generally be employed in fabricating the structures of this invention. Furthermore, individual steps of such methods may be performed using commercially available integrated circuit fabrication machinery. Exemplary technical data is set forth based on current technology, as it is particularly necessary for understanding this invention. Future developments in this technology may require appropriate adjustments as will be apparent to those skilled in the art.

Figure 2a shows a wafer substrate 10, for example a section of a commercially available lightly doped silicon wafer. For purposes of describing this invention, a wafer substrate 10 is defined as one or more integrated circuit chips having a number of active component areas and contact areas and electrical interconnections according to a circuit design. It should be assumed that the material has already been processed to the point where it is prepared for metallization to form.

One such component area 12 lies on the surface 14 of the substrate 10 . For example, substrate 10 may be a single crystal silicon substrate or an epitaxial layer grown on such a substrate lightly doped to have p-type conductivity. The component region 12 may be a silicon region heavily doped with n+ type conductivity, for example to act as a collector of a bipolar transistor or a drain region of a field effect transistor. Regardless of the functional nature of the contact area 12, the contact hole 1
6 has already been formed in a dielectric or insulating layer 18, such as silicon dioxide (“oxide”), overlying the substrate 10 so that electrical interconnections can be made to the contact regions 12. There is. Holes 16 may also be drilled, for example, on interconnect lines or gated bases of the chip.

A layer of amorphous semiconductor material, such as polysilicon 20, is formed. Although the width of hole 16 appears relatively narrow, it is easily filled using well-known techniques. Conventional production techniques such as chemical vapor deposition (CVD) or plasma enhanced CVD may be employed to form polysilicon layer 20. This layer can be doped to have a relatively low resistivity by diffusion after PH1 or POC (U3) in a CVD cycle. or doped with donor atoms by well-known ion implantation techniques.
selected to form a

A refractory metal layer 22 is formed over polysilicon 20.

Exemplary suitable refractory metals are titanium (T), tungsten (W), molybdenum (Mo), tantalum (Ta), and platinum (Pt).

Sputter generation is a common method technique.

Next, the formed polysilicon 20 and refractory metal 2
The layered structure of 2 is placed through a heat treatment cycle to allow polysilicon 20 and metal 22 to react to form polycide material 24. Typical cycle parameters are approximately 30 minutes to 1 hour at 600°C to 90°C under a nitrogen or argon atmosphere.
Heat in a furnace tube at 00°C. Short-term thermal annealing methods at elevated temperatures may also be employed.

The relative thicknesses of polysilicon 20 and refractory metal 22 depend on the reactivity properties of the selected materials and the dimensions of the hole in which the conductive plug is to be formed.

For example, it is well known that a 1 angstrom thick layer of titanium reacts with approximately 2.27 angstroms of polysilicon to form an approximately 2.51 angstroms of polycide titanium silicide layer. To form a polycide plug, it is desirable to select a thickness such that all or nearly all of the polysilicon 20 in hole 16 is reacted to form polycide 24, as shown in FIG. 2b.

FIG. 2b shows unreacted polysilicon 20, depending on the relative thicknesses of polysilicon 20 and refractory metal 22.
(The remaining layer of I is in the hole 1 of the surface 14 of the substrate 10
FIG. Since the polysilicon 2 (I) is doped and the residue can be made very thin, the resistance is low. Therefore, an ohmic contact between the contact region 12 and the polycide 24 is ensured.

If region 12 is a shallow junction region, to prevent erosion or "spiking" of the polycide through the junction of contact region 12 with substrate 10;
It may be desirable to calculate the relative thickness and thermal cycling parameters to intentionally leave a residue of this polysilicon 20°. For deeper junction regions or contact holes in metal interconnect layers, a reaction can be performed to completely convert the polysilicon to polycide.

An important aspect of this invention is the control afforded by the nature of the reaction. The thickness of the refractory metal 22 is the same as that of polysilicon 2.
0 and the known depth of the hole 16. Therefore, the thickness of metal 22 can be predetermined such that either polysilicon or polycide or a polysilicon plug on polycide remains in hole 16 depending on the nature of the chip structure being fabricated. . The examples described below also exhibit this feature.

A residual layer 22' of unreacted metal also remains regardless of the heat treatment cycle. Therefore, any unreacted pure refractory metal layer 22' is removed using conventional cleaning force A.

Polycide 24 is then partially etched such that it is removed from oxide 18 but remains in hole 16.

Etching can be performed using conventional chemical etchants such as buffered hydrofluoric acid or chlorine plasma etchants.

Thus, the conductive polycide plug substantially fills the hole as shown in FIG. 2C. The entire structure is already substantially planarized. A subsequently formed metallization layer, typically produced by masking and sputtering aluminum or forming a metal silicide interconnect structure (see, for example, the patent application filed September 30, 1982, and the present application). (see U.S. patent application Ser. No. 430,188 to Wallacen et al., assigned to Co., Ltd.) also becomes substantially planar.

Therefore, the creation of a metal layer provides better step coverage. Furthermore, such a metal layer automatically has a substantially planar shape. This, of course, becomes extremely important if the coating is constructed overlapping other layers or metal layers.・Polycide plug 24' is
It provides an additional advantage over a single polysilicon plug in that it has a much lower resistivity. For example, a titanium silicide plug formed in accordance with the present invention has a resistance approximately three orders of magnitude lower than a polysilicon plug.

EXAMPLE 1 A hole having dimensions of 1 x 1 x 1 micron (length x width x depth) was formed with a polysilicon layer filling the hole and rising 10.000 angstroms above the oxide. Titanium was sputtered onto the polysilicon to have a thickness of 0.85 microns. The structure was heated to 900°C for 30 minutes at 4F with a N2 ambient atmosphere. The remaining pure titanium was removed by NH,OH mixed with H20□. The polycide was chemically etched with a BOE of 10:1. This essentially fills the hole with Ti
The Si2 polycide plug was left in place.

As shown in FIG. 3a, for relatively narrow holes 16, the product of polysilicon 20 and refractory metal 22 can create a cusp 30 approximately over the center of the hole 16. At the tip, the thickness of the refractory metal can vary between 10 and 50% of the total sputter thickness. A first alternative set of method steps for handling this situation is shown in Figures 3b-3d. In the previously described technique, the required thickness of the refractory metal 22 to be reacted is:
Determined according to the depth of the hole to be filled. Instead, the thickness of metal 22 is determined by the thickness of polysilicon 20 produced over oxide 18. For some fabrication applications, the latter may be easier to determine. However, extra method steps are required. The heavily doped LPGVD polysilicon 20 is
The thickness t is approximately half the width of the hole 16.

The heat treatment cycle continues until polycide 24 is formed on the major surface 32 of oxide 18, as shown in FIG. 3b. Due to the varying thickness of refractory metal 22, the interface between polycide 24 and unreacted polysilicon 21 is substantially planar in the plane of surface 32 of insulator layer 18. The polycide 24 is then removed as already mentioned.

It may be noted again that in this step a polysilicon plug 21 has already been formed which essentially planarizes the main surface 32 of the structure. If the relatively high resistivity of doped polysilicon on polycide is not critical to the performance of the integrated circuit, the metallization process step can be performed immediately.

Referring now to Figure 3c, another refractory metal layer 34 is formed on the surface 32 of the structure. The thickness of layer 34 is
Determined by the depth of 6. Again, a heat treatment cycle is performed to cause metal 34 to react with polysilicon plug 21 in hole 16. After reaction, the plug 21 has been substantially converted into polycide 24'', as shown in Figure 3d.

Refractory metal residue 22 may then be removed or used in forming component interconnects.

As above, again a thin layer of polysilicon 20' is shown left in place between plug 21 and contact region 12.

Other alternative embodiments are shown in Figures 4a to 4d. This embodiment relates to a contact window that is not only relatively deep but also relatively wide.

As a result of the width and conformal prism of the polysilicon product,
The first layer 20 into the hole 16 may include a main recess as indicated by arrow 40 . Refractory metal formed after 2
2 follow the same general contour. After the first heat treatment cycle, a first conformal layer of polycide 24 is formed and a polysilicon hole lining 20' remains. A layer of second polysilicon 42 is formed to at least substantially fill recess 40 . This is most easily achieved by forming a blanket layer, as shown in dotted lines in Figure 4b. Alternatively, photoresist may be used to fill recess 40.

Etching is then carried out. A polysilicon plug 42' is left in the recess 40. This plug 42' can be electrically conductive, as described above.

Thus, by etching to the level of surface 32, the structure can become relatively planar, so that metallization can continue in this state, or plug 42' can be converted to polycide.

Referring now to Figure 4c, a second layer of refractory metal 34 is formed over the structure. The second heat treatment cycle
Then it is done.

After heat treatment as shown in Figure 4d, polycide 2
4' is formed and substantially fills the hole 16. refractory metal residue 22' and layer 24 from surface 32 of the structure;
A conventional etch can then be performed to remove the unwanted polycide portions.

A similar solution to the relatively deep and relatively shallow hole 16 problem is shown in Figures 5a through 5d. After the first heat treatment cycle polysilicon lining 2 (l
The first method steps are essentially the same in FIGS. 4a and 5a and 4b and 5b, respectively, except that an extra thickness of refractory metal 22 is formed to avoid residual is the same as Typically, the thickness of the refractory metal 22 is between 20 and 5096 times the total thickness of the sputtered layer depending on the width of the recess 40. A residue 22' of the refractory metal removed from the structure may remain.

Following this removal, a photoresist layer 44 is formed over the structure, as shown in dotted lines in Figure 5c.

Following development, only photoresist plug 44' remains in recess 40. Photoresist plug 44' acts as a shield for the underlying polycide during subsequent etching of the polycide layer. As shown in Figure 5d, this results in a polycide plug 24' in the hole 16 having a relatively smoothly curved upper surface 46. Therefore, the later formed metallization layer provides better step coverage.

Still other alternative embodiments for very deep and very wide hole structures, such as those that may be found in multilayer integrated circuits, are shown in Figures 6a through 6f. With such a hole 16 there is a risk of creating a void in the recess 40.

The first step of the method corresponds to the embodiment shown in FIGS. 4a and 4b, i.e. as shown in FIGS. A conformal polycide 24 is first formed. A layer of polycide 24 is then etched away. As a result, as shown in FIG. 6C,
This results in a recess 40' having a reduced aspect ratio and a smoother profile compared to the original recess 40.

A second layer of polysilicon 42 and a second overlapping layer of refractory metal 32 are formed. Since the recess 4 (I) is modified, this product is more brassy in nature.

A heat treatment is then performed to react the polysilicon 42 and the refractory metal 32 to form a layer of polycide 24' with the polysilicon plug 42' attached to the structure, as shown in FIG. 6d. A cycle is performed.

The second layer of polycide 24' is then removed from the structure.

Referring now to Figure 6e, a third layer of refractory metal 46 is formed over the structure. Because of the polysilicon plug 42', the surface 34 of the structure is now substantially planar and the thickness of the refractory metal 46 is approximately uniform. As a result, a heat treatment cycle may be performed to form a polycide plug 24' in the hole 16, as shown in Figure 6f.

This series of drawings also illustrates that, for example, if the contact region 12 is relatively deep, there is little chance of polycide spiking through the junction, regardless of variations according to method tolerances, as shown in the previous example. It is intended to indicate that a polysilicon residue layer 20'' such as Should have low overall resistance.

As is clear to those skilled in the art, the contact holes 16 are
In particular, it may be open to both the n-type surface area and the n-type surface area of the substrate 10 in complementary metal oxide semiconductor devices. Suitable conventional masking techniques may be used to achieve proper doping of the plug of polysilicon 21 to match the adjacent contact region 12.

The above description of preferred and alternative embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and changes will become apparent to those skilled in the art. Similarly, any of the method steps described above may be replaced with other steps to achieve similar results. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, so that those skilled in the art will be familiar with the various embodiments and specific applications contemplated. It makes it possible to understand this invention with various modifications adapted to it. It is intended that the scope of the invention be defined by the following claims and their equivalents.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of the problem of step cover by metallization layers of an integrated circuit. 2-6 are schematic cross-sectional views of idealized sequences of method steps according to various embodiments of the invention. Figure 2a shows a sub-layer with contact holes through superimposed layers such as dielectric or insulator materials in which an amorphous semiconductor material such as polysilicon and an overlapping refractory metal layer such as a titanium layer are sequentially formed. This shows the completion of the straight stepped section. Figure m2b shows the step completion after the polysilicon and metal have been reacted to create the polycide material as shown in Figure 2a. Figure 2C shows the step completion after the polycide and any residual metal has been removed to leave a polycide plug that substantially fills the contact hole, as shown in Figure 2b. FIG. 3a shows a sub-substrate with contact holes through superimposed layers, such as oxide layers, in which a polysilicon layer and a refractory metal layer are formed sequentially.・Indicates completion of the stepped section of the rate. Figure 3b shows the step completion after the polysilicon and refractory metal have been reacted to create the polycide material as shown in Figure 3a. Figure 3C shows the step completion after the polycide layer has been removed to leave a polysilicon plug and a second refractory metal layer has been formed, as shown in Figure 3b. The mad figure shows the step completion after the polysilicon plug and refractory metal of FIG. 3C have been reacted to form a polycide plug that substantially fills the contact hole. FIG. 4a shows the step completion of the substrate with contact holes through polysilicon and overlapping refractory metal layers or sequentially formed overlapping layers. FIG. 4b shows that the polysilicon and metal are reacted to form a polycide layer as shown in FIG. 4a;
and shows the completion of the step after the overlapping polysilicon layer is formed. Figure 4c shows the completion of the step after the overlying polysilicon layer has been etched and the second refractory metal layer has been formed, as shown in Figure 4b. Figure 4d shows the step completion after the second refractory metal has been reacted with the underlying layer as shown in Figure 4c. Figure 5a shows the completed step of the substray 1 with contact holes formed and overlapping layers of polysilicon and overlapping refractory metal layers formed sequentially. Figure 5b shows the step completion after the polysilicon and metal have been reacted to form a polycide layer leaving a metal residue as shown in Figure 5a. Figure 5c shows the completion of the step after the residue layer of Figure 5b has been removed and a photoresist layer has been formed over the polycide layer. Figure 5d shows the step completion after the photoresist and polycide layers have been etched to leave a polycide plug that substantially fills the contact hole, as shown in Figure 5c. FIG. 6a shows the step completion of the substrate with contact holes through sequentially produced superimposed layers of polysilicon and refractory metal layers. Figure 6b shows the step completion after the polysilicon layer and metal layer have been reacted to form the polycide material as shown in Figure 6a. Figure 6C shows the step completion after the polycide layer has been removed and a second polysilicon layer and a second refractory metal layer have been sequentially formed, as shown in Figure 6b. Figure 6d shows the step completion after the second polysilicon layer and the second refractory metal layer have been reacted to form the second polycide layer as shown in Figure 6c. . Figure 6e shows the completion of the step after the second polycide layer has been removed and the third refractory metal layer has been created, as shown in Figure 6d. Figure 1fflSf shows the step completion after the third refractory metal layer has been reacted with the polysilicon in the contact hole and any remaining refractory metal has been removed, as shown in Figure 6e. In the figure, 10 is a substrate, 12 is a contact area, 14, 23, 32 is a surface, 16 is a contact hole,
18 is an insulator layer, 20.2 (I. 42 is polysilicon, 21 is a polysilicon plug, 22
．． 22-. 34 and 46 are refractory metals, 24 is polycide, 24' is a polycide plug, 42' is a polysilicon plug, 44 is a photoresist, and 44' is a photoresist plug. Special, ;'FilfQ Advanced Micro Depines Erased Co., Ltd. Representative Patent Attorney Kube Fukami (and 2 others)・'□1'-□ --12

Claims (21)

[Claims] (1) A method for improving step coverage of a semiconductor integrated circuit structure, the method comprising forming a layer of amorphous semiconductor material having contact holes for electrical coupling and substantially filling the holes. forming a layer of refractory metal on the layer of amorphous semiconductor material; reacting at least some of the refractory metal with at least some of the amorphous semiconductor material; and forming the hole. removing said reacted material except within the range of
whereby a conductive plug remains and substantially fills the hole. 2. The method of claim 1, wherein said step of forming a layer of amorphous semiconductor material comprises: producing a layer of polysilicon material. (3) The step of forming a layer of amorphous semiconductor material includes the step of: producing a layer of doped polysilicon having the same conductivity type as the area of the structure in which the hole is formed. The method described in paragraph 1. (4) forming a layer of amorphous semiconductor material includes introducing a dopant into the material to cause the material to have the same conductivity type as the area of the perforated structure; 3. The method of claim 2, further comprising: (5) Forming a layer of refractory metal comprises: sputtering a refractory metal onto the structure selected from the group comprising titanium, tungsten, molybdenum, tantalum, and platinum. The method described in paragraph 1. (6) forming a layer of refractory metal following said reaction, such that said conductive plug is either a polysilicon plug or a polycide plug or a polycide plug on layered polysilicon; ,
5. The method of claim 4, further comprising the step of producing the metal to a predetermined thickness. (7) The step of reacting comprises the step of: heating the structure such that the refractory metal layer and the polysilicon layer react to form a substantially homogeneous polycide material. The method described in paragraph 4. (8) the step of heating causes the polysilicon and the refractory metal to react such that a thin film formed in the interstices of the polysilicon remains between the area of the structure and the polycide remaining in the hole; 8. The method of claim 7, further comprising the step of: 9. The method of claim 1, wherein the step of removing the reacted material further comprises the step of etching the major surface of the structure to a level where it becomes substantially planar. (10) prior to said etching, the step of removing said reacted material forms a layer of photoresist material on said structure so as to fill any recessed areas of said reacted material within said hole; 10. The method of claim 9, further comprising the step of: (11) A semiconductor integrated circuit fabrication method for forming a conductive plug in a contact hole of at least one partially completed integrated circuit die to facilitate step coverage by a metallization layer to be formed. forming polysilicon on the die to substantially fill the hole; forming a refractory metal on the polysilicon; and forming polycide in the hole. A method for manufacturing a semiconductor integrated circuit, comprising: heat treating the polysilicon and the refractory metal; and removing the die so as to leave polycide only in the hole. (12) prior to said step of producing said refractory metal, further comprising doping said polysilicon with conductivity to match the conductivity of an area of said die adjacent said hole. , the method according to claim 11. (13) In the fabrication of semiconductor integrated circuits, a method includes a structure including contact holes through a structural layer overlapping a substrate and improves step coverage by an electrical bonding layer formed therefrom. , forming a layer of an amorphous semiconductor material on the structure to substantially fill the hole; forming a layer of a refractory metal on the amorphous semiconductor material; reacting the semiconductor material layer and the refractory metal layer such that the metal forms a conductive polycide material, and removing the structure of the material, except for the hole, thereby forming a subsequently formed layer; providing a substantially improved step covering. (14) forming a layer of amorphous semiconductor material includes: producing a layer of doped polysilicon having the same conductivity type as the area of the structure in which the hole is formed;
A method according to claim 13. (15) the step of reacting comprises heat treating the structure until the semiconductor material and the refractory metal form a layer of polycide material overlying the structure and the substantially filled holes; , removing the polycide layer from the structure; forming a second refractory metal layer over the structure; and heat treating the structure to form a polycide plug that substantially fills the structure. (16) the step of reacting comprises heating the structure until the semiconductor material and the refractory metal form a layer of polycide material overlying the structure and partially filling the holes; , producing a second layer of amorphous semiconductor material on the layer of polycide material such that areas of unfilled holes are substantially filled; and producing a second layer of refractory metal on the structure. 14. The method of claim 13, comprising the steps of: producing a polycide; and heat treating the structure until substantially all of the unreacted semiconductor material is converted to polycide. (17) a step of reacting forms a polycide material in which the semiconductor material and the refractory metal overlap the structure and partially fill the hole such that a lining of the semiconductor material remains in the hole; heat treating the structure until the structure is heated; removing the polycide material layer; producing a second layer of amorphous semiconductor material on the structure; and forming a second refractory layer on the structure. heat treating the structure until the second semiconductor material layer and the second refractory metal layer form a polycide material layer overlying the structure; producing a third refractory metal layer over the structure until the semiconductor material remaining in the hole and the third refractory metal form a plug of polycide material substantially filling the hole; 14. The method according to claim 13, comprising the steps of: heating the structure. (18) A method for improving step coverage of electrical contact metallization in a semiconductor integrated circuit structure, the method comprising:
forming a first conformal amorphous semiconductor material layer over the structure, the contact hole having a relatively wide and relatively deep contact hole; forming a conformal refractory metal layer of at least partially filling the hole in the structure;
thermally reacting the first semiconductor material layer and the first metal layer to form a conformal polycide layer of forming a second layer of amorphous semiconductor material having an upper surface of the first polycide layer and the second polycide layer in the hole;
etching the second layer of semiconductor material until a substantially planar upper surface is formed after the layer of semiconductor material; and etching a second refractory metal on the rear planar surface. the second metal layer, the second semiconductor material layer, the first polycide layer, and the first semiconductor material layer to form a substantially homogeneous polycide layer; and removing the homogeneous polycide layer except for the hole so that a conductive plug substantially fills the hole and substantially planarizes the structure. A method comprising: 19. The method of claim 18, wherein said step of forming said first amorphous semiconductor material further comprises the step of introducing impurities into said material to render it electrically conductive. (20) A method for improving step coverage of electrical contact metallization in a semiconductor integrated circuit structure, the method comprising:
forming a first, conformal layer of amorphous semiconductor material on the structure, having a relatively wide and deep contact hole; a first, etc. layer on the first layer of semiconductor material; forming an angular refractory metal layer; heating the structure such that the semiconductor material and the refractory metal form a first conformal polycide material layer; and a lining of semiconductor material. forming a second layer of amorphous semiconductor material on the structure; and forming a second layer of amorphous semiconductor material on the second layer of semiconductor material. forming a second layer of refractory metal such that the second layer of semiconductor material and the second layer of refractory metal exclude the hole to form a second layer of polycide material; removing the second layer of polycide material; forming a third refractory metal layer over the structure; heating the structure to form a polycide plug that substantially fills the hole. 21. The method of claim 20, wherein the step of forming the first conformal amorphous semiconductor material layer further comprises: doping the material to make it conductive.