JPH0456222A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0456222A JPH0456222A JP16718090A JP16718090A JPH0456222A JP H0456222 A JPH0456222 A JP H0456222A JP 16718090 A JP16718090 A JP 16718090A JP 16718090 A JP16718090 A JP 16718090A JP H0456222 A JPH0456222 A JP H0456222A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon oxide
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 47
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 30
- 239000011574 phosphorus Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 13
- 239000001257 hydrogen Substances 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims description 25
- 238000007254 oxidation reaction Methods 0.000 claims description 25
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 6
- 230000008018 melting Effects 0.000 abstract description 5
- 238000002844 melting Methods 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract 2
- 238000007740 vapor deposition Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路の形成方法のうち、特に配線間
の層間絶縁膜の形成方法を含む半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming a semiconductor integrated circuit, and particularly to a method for manufacturing a semiconductor device including a method for forming an interlayer insulating film between wirings.
従来の技術
層間絶縁膜としては化学気相成長法による酸化シリコン
膜が用いられている。熱処理による平坦化を容易にする
ため、酸化シリコン膜にリンなどの不純物を混入させ酸
化シリコン膜の融点を下げたものが一般に用いられてい
る。A silicon oxide film produced by chemical vapor deposition is used as a conventional interlayer insulating film. In order to facilitate planarization by heat treatment, a silicon oxide film is generally used in which an impurity such as phosphorus is mixed in to lower the melting point of the silicon oxide film.
発明が解決しようとする課題
従来の技術では熱処理による平坦化の後でも酸化シリコ
ン膜中に含まれるリンの量は化学気相成長直後と比べて
もほとんど変化がない。多層配線構造の場合には複数の
層間絶縁膜を用いるため、上層の層間絶縁膜の平坦化を
熱処理により行う場合に下層の層間絶縁膜も変形すると
いう問題点を有していた。Problems to be Solved by the Invention In the conventional technology, even after planarization by heat treatment, the amount of phosphorus contained in a silicon oxide film hardly changes compared to immediately after chemical vapor deposition. In the case of a multilayer wiring structure, since a plurality of interlayer insulating films are used, there is a problem in that when the upper interlayer insulating film is planarized by heat treatment, the lower interlayer insulating film is also deformed.
課題を解決するための手段
上記課題を解決するために本発明では、リンを含む酸化
シリコン膜の形成において、化学気相成長法にてリンを
含む酸化シリコン膜を成長し平坦化処理を行った後に、
水素雰囲気にて８００℃〜１０００℃の熱処理を施した
。Means for Solving the Problems In order to solve the above problems, in the present invention, in forming a silicon oxide film containing phosphorus, a silicon oxide film containing phosphorus is grown by a chemical vapor deposition method and a planarization treatment is performed. later,
Heat treatment was performed at 800°C to 1000°C in a hydrogen atmosphere.
また、半導体基板上の所定領域に第１の絶縁膜を形成す
る工程と、前記第１の絶縁膜および前記半導体基板上の
所定領域に耐酸化性被膜を形成する工程と、前記第１の
絶縁膜と前記耐酸化性被膜と前記半導体基板上の所定領
域に第１の導電膜を形成する工程と、前記第１の導電膜
および前記耐酸化性被膜の所定領域に第２の絶縁膜を形
成する工程と、前記第２の絶縁膜および前記耐酸化性被
膜の一部に第２の導電膜を形成する工程を備えている。Further, the step of forming a first insulating film in a predetermined region on a semiconductor substrate, the step of forming an oxidation-resistant film in a predetermined region on the first insulating film and the semiconductor substrate, and the step of forming a first insulating film in a predetermined region on the semiconductor substrate; forming a first conductive film in a predetermined region on the film, the oxidation-resistant film, and the semiconductor substrate; and forming a second insulating film in a predetermined region of the first conductive film and the oxidation-resistant film. and forming a second conductive film on a portion of the second insulating film and the oxidation-resistant film.
また、半導体基板上の所定領域に第１の絶縁膜を形成す
る工程と、前記第１の絶縁膜および前記半導体基板上の
所定領域に耐酸化性被膜を形成する工程と、前記第１の
絶縁膜と前記耐酸化性被膜と前記半導体基板上の所定領
域に第１の導電膜を形成する工程と、前記第１の導電膜
および前記耐酸化性被膜の所定領域に第２の絶縁膜を形
成する工程と、前記第２の絶縁膜および前記耐酸化性被
膜の一部に第２の導電膜を形成する工程と、前記半導体
基板全面に第３の絶縁膜を形成する工程と、前記第３の
絶縁膜の所定領域をエツチングし、前記第２の導電膜を
露出する工程と、露出した前記第２の導電膜を酸化する
工程を備えている。Further, the step of forming a first insulating film in a predetermined region on a semiconductor substrate, the step of forming an oxidation-resistant film in a predetermined region on the first insulating film and the semiconductor substrate, and the step of forming a first insulating film in a predetermined region on the semiconductor substrate; forming a first conductive film in a predetermined region on the film, the oxidation-resistant film, and the semiconductor substrate; and forming a second insulating film in a predetermined region of the first conductive film and the oxidation-resistant film. a step of forming a second conductive film on a part of the second insulating film and the oxidation-resistant film; a step of forming a third insulating film on the entire surface of the semiconductor substrate; The method includes a step of etching a predetermined region of the insulating film to expose the second conductive film, and a step of oxidizing the exposed second conductive film.
作用
リンを含む酸化シリコン膜を水素雰囲気にて熱処理した
場合には、８００℃、６０分の条件で成長直後と比較し
て１割程度のリンが、１０００℃。When a silicon oxide film containing functional phosphorus is heat-treated in a hydrogen atmosphere, at 800°C for 60 minutes, about 10% of the phosphorus remains at 1000°C compared to immediately after growth.
６０分の条件では４割程度のリンが外方向拡散により、
膜中から除かれる。１０００℃を越えた温度では膜中に
気泡状のものが発生するため実使用に耐えない。また８
００℃より低い温度では外方向拡散の効果が低くやはり
実使用に耐えない。Under conditions of 60 minutes, about 40% of phosphorus is diffused outward,
removed from the membrane. If the temperature exceeds 1000°C, bubbles will form in the film, making it unusable. 8 again
At temperatures lower than 00° C., the effect of outward diffusion is low and it is not suitable for practical use.
本発明によれば、平坦化の効果を上げるために絶縁膜中
のリン濃度を高（しても、平坦化の後にリン濃度を減少
させるため従来の問題点を容易に解決できた。According to the present invention, even if the phosphorus concentration in the insulating film is increased in order to improve the planarization effect, the phosphorus concentration is reduced after planarization, making it possible to easily solve the conventional problems.
実施例
本発明の一実施例を第１図および第２図を用いて詳細に
説明する。Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.
第１図＜ａ＞は、シリコン基板１上に素子分離用シリコ
ン膜２及び配線材料３を形成した後、化学気相成長法に
てリンを含む酸化シリコン膜を成長した後に９００℃の
水蒸気雰囲気中で３０分の熱処理を加え平坦化して酸化
シリコン膜４を得たものである。本実施例では、配線材
料として多結晶シリコンを用い、リンを含む酸化シリコ
ン膜４としてはリン濃度７ 、０ ｗ ｔ％及びボロン
濃度３．０ｗｔ％のＢＰＳＧ膜を常圧化学気相成長法に
より形成する。この後、９００℃、３０分の水素雰囲気
中での熱処理を施し第１図（ｂ）が得られる。この処理
後に得られた酸化シリコン膜５のリン濃度は約４ｗｔ％
であり、ボロン濃度の変化はほとんどなかった。このよ
うに熱処理によってリンが膜外に放出されていることが
分かる。次いで、高融点材料の配線６を形成する（第１
図（（２））。本実施例ではタングステンシリサイドを
高融点材料として用いた。この後、第２のリンを含む酸
化シリコン膜７を成長する（第１図（ｄ））。次いで、
平坦化用熱処理を施し酸化シリコン膜８を得る（第１図
（ｅ））。FIG. 1 <a> shows a diagram in which a silicon film 2 for element isolation and a wiring material 3 are formed on a silicon substrate 1, and then a silicon oxide film containing phosphorus is grown by chemical vapor deposition in a water vapor atmosphere at 900°C. The silicon oxide film 4 was obtained by applying heat treatment for 30 minutes to flatten the film. In this example, polycrystalline silicon is used as the wiring material, and the phosphorus-containing silicon oxide film 4 is a BPSG film with a phosphorus concentration of 7.0 wt% and a boron concentration of 3.0 wt% by normal pressure chemical vapor deposition. Form. Thereafter, heat treatment was performed at 900° C. for 30 minutes in a hydrogen atmosphere to obtain the image shown in FIG. 1(b). The phosphorus concentration of the silicon oxide film 5 obtained after this treatment is approximately 4 wt%.
, and there was almost no change in boron concentration. It can be seen that phosphorus is released outside the film by heat treatment. Next, a wiring 6 made of a high melting point material is formed (first
Figure ((2)). In this example, tungsten silicide was used as the high melting point material. Thereafter, a second phosphorus-containing silicon oxide film 7 is grown (FIG. 1(d)). Then,
Heat treatment for planarization is performed to obtain a silicon oxide film 8 (FIG. 1(e)).
このとき第２の酸化シリコン膜の形成条件及び平坦化条
件は第１の酸化シリコン膜４を得たものと同等である。At this time, the conditions for forming the second silicon oxide film and the conditions for planarization are the same as those for obtaining the first silicon oxide film 4.
さらに酸化シリコン膜４を別の酸化シリコン膜５に変化
させて融点を上昇させているため、平坦化熱処理による
酸化シリコン膜５は変形しない。つまり、下地膜である
酸化シリコン膜５の形状に影響されることなく第２の酸
化シリコン膜７が平坦化された酸化シリコン膜８を得る
ことができる。この後、酸化シリコン膜８に９００℃、
３０分で水素雰囲気中で熱処理し、リン濃度の少ない酸
化シリコン９を形成する（第１図げ））。Further, since the silicon oxide film 4 is changed to another silicon oxide film 5 to increase the melting point, the silicon oxide film 5 is not deformed by the planarization heat treatment. In other words, the silicon oxide film 8 in which the second silicon oxide film 7 is planarized can be obtained without being affected by the shape of the silicon oxide film 5 serving as the base film. After this, the silicon oxide film 8 was heated to 900°C.
Heat treatment is performed in a hydrogen atmosphere for 30 minutes to form silicon oxide 9 with a low phosphorus concentration (Fig. 1)).
多層配線構造では、この後酸化シリコン膜９の上にさら
に配線１０を設ける（第１図（ｇ））。このため、第１
図（ｇ）の後工程として配線１０上に眉間絶縁膜形成と
その層間絶縁膜の平坦化処理が必要である。このために
第１図げ）において、水素雰囲気にて処理しリン濃度を
さげて酸化シリコン膜９を得た。本実施例では水素雰囲
気中で９００℃、３０分の処理を施してリン濃度を４割
程度減少させた。In the multilayer wiring structure, a wiring 10 is then further provided on the silicon oxide film 9 (FIG. 1(g)). For this reason, the first
As a post-process shown in FIG. 3(g), it is necessary to form an insulating film between the eyebrows on the wiring 10 and to planarize the interlayer insulating film. For this purpose, in FIG. 1), a silicon oxide film 9 was obtained by processing in a hydrogen atmosphere to lower the phosphorus concentration. In this example, treatment was performed at 900° C. for 30 minutes in a hydrogen atmosphere to reduce the phosphorus concentration by about 40%.
第２図にスタック型キャパシタを有するＤＲＡＭのコン
タクトホール形成時の実施例の工程断面図を示す。FIG. 2 shows a cross-sectional view of the process of forming a contact hole of a DRAM having a stacked capacitor.
シリコン基板１１上に素子分離領域１２を形成し、ゲー
ト酸化膜１３．ゲート電極１４および絶縁膜１５から成
るトランスファーゲートを形成したものが第２図（ａ）
である。以後の工程で形成されるキャパシタ下部電極用
コンタクト形成領域近傍以外に耐酸化性被膜１６を残す
（第２図（ｂ））。次にキャパシタ下部電極１７．キャ
パシタ絶縁膜１８およびキャパシタ上部電極１９から成
るスタック型キャパシタを形成する（第２図（（２））
。この後、リンを含む眉間絶縁膜２０を形成したものが
第２図ω）である。An element isolation region 12 is formed on a silicon substrate 11, and a gate oxide film 13. FIG. 2(a) shows a transfer gate formed of a gate electrode 14 and an insulating film 15.
It is. The oxidation-resistant film 16 is left in areas other than the vicinity of the capacitor lower electrode contact forming region which will be formed in the subsequent steps (FIG. 2(b)). Next, capacitor lower electrode 17. A stacked capacitor consisting of a capacitor insulating film 18 and a capacitor upper electrode 19 is formed (FIG. 2 (2))
. After this, a glabellar insulating film 20 containing phosphorus was formed, as shown in FIG. 2 ω).
ここで、リンを含む眉間絶縁膜２０は、化学気相成長法
によりリン濃度７ 、 Ｏｗ ｔ％、ボロン濃度３．０
％の酸化シリコン膜を成長した後に９００℃、６０分の
水蒸気雰囲気による平坦化処理を施すことにより得られ
る。Here, the glabellar insulating film 20 containing phosphorus is formed by chemical vapor deposition with a phosphorus concentration of 7 Owt% and a boron concentration of 3.0.
% by growing a silicon oxide film and then subjecting it to planarization treatment in a water vapor atmosphere at 900° C. for 60 minutes.
この後９００℃、３０分の水素雰囲気中での熱処理を加
えてリン含有量が４．Ｏｗｔ％程度の酸化シリコン膜２
１を形成したものが第２図（ｅ）である。After that, heat treatment was performed at 900°C for 30 minutes in a hydrogen atmosphere to reduce the phosphorus content to 4. Silicon oxide film 2 of about Owt%
1 is formed as shown in FIG. 2(e).
次いで公知のフォトリソグラフィーとエツチング技術を
用いてホール２２を形成した（第２図（ｒ））。Next, holes 22 were formed using known photolithography and etching techniques (FIG. 2(r)).
このとき、キャパシタ上部電極１９の端部２３が露出す
る。このため、熱酸化により端部２３を酸化することで
酸化シリコン膜２４を形成する（第２図（ｇ））。後の
工程で形成する配線と上部電極１９との絶縁を酸化シリ
コン膜２４は行う必要がある。このため下地に耐酸化性
被膜１６を形成しておかねばならない。At this time, the end portion 23 of the capacitor upper electrode 19 is exposed. Therefore, a silicon oxide film 24 is formed by oxidizing the end portion 23 by thermal oxidation (FIG. 2(g)). The silicon oxide film 24 needs to provide insulation between the upper electrode 19 and the wiring that will be formed in a later step. For this reason, an oxidation-resistant coating 16 must be formed on the base.
次に、ホール２２のシリコン基板上に形成された耐酸化
性被膜１６をエツチング除去してコンタクトホール２５
を形成する（図２図（）ｔ３）。Next, the oxidation-resistant film 16 formed on the silicon substrate in the hole 22 is removed by etching, and the contact hole 22 is removed by etching.
(Figure 2 () t3).
従来の技術であれば、第２図（ｄ）の直後にコンタクト
形成を行う。第３図に示すような不都合が生じる。第３
図（ａ）は層間絶縁膜２７を形成後、ホール２８を形成
し、熱処理した時の断面図である。In the conventional technique, contact formation is performed immediately after FIG. 2(d). Inconveniences as shown in FIG. 3 occur. Third
Figure (a) is a cross-sectional view when the interlayer insulating film 27 is formed, holes 28 are formed, and heat treatment is performed.
このように第３図（ａ）に示すごと（、酸化工程時の熱
処理によって層間絶縁膜２７が変形してしまいコンタク
ト上部が狭くなる。このため第３図（ｂ）に示すように
眉間絶縁膜２７上に配線２９を成長すると、配線２９が
コンタクト内に成長せずボイド３０と呼ばれるすき間が
発生してしまう。As shown in FIG. 3(a), the interlayer insulating film 27 is deformed due to the heat treatment during the oxidation process and the upper part of the contact becomes narrow. When the wiring 29 is grown on the contact 27, the wiring 29 does not grow within the contact, resulting in a gap called a void 30.
本実施例に示すように、化学気相成長法により酸化シリ
コン膜を成長し平坦化処理を施した後に、水素雰囲気中
での熱処理を加えることにより、酸化シリコン膜２４を
形成する酸化工程時でも眉間絶縁膜２０が変形すること
がない。従って、第２図（ｇ）のように眉間絶縁膜２１
の変形を伴わずに端部２３の熱酸化が可能となる。これ
により、コンタクト部の耐酸化性被膜１６のエツチング
も可能となる。最後に第２図（ｉ）に配線２６を堆積す
る。この時コンタクトホール２５は変形していないため
良好なコンタクト・配線形成ができた。As shown in this embodiment, a silicon oxide film is grown by chemical vapor deposition, planarized, and then heat treated in a hydrogen atmosphere, even during the oxidation process to form the silicon oxide film 24. The glabellar insulating film 20 is not deformed. Therefore, as shown in FIG. 2(g), the glabella insulating film 21
Thermal oxidation of the end portion 23 becomes possible without deformation. This also makes it possible to etch the oxidation-resistant film 16 in the contact area. Finally, wiring 26 is deposited as shown in FIG. 2(i). At this time, since the contact hole 25 was not deformed, good contacts and wiring could be formed.
発明の効果
本発明により、熱による平坦化が可能な同一種のリンを
含む酸化シリコン膜を下層膜の変形なしに、複数回用い
ることが可能となった。Effects of the Invention According to the present invention, it has become possible to use a silicon oxide film containing the same type of phosphorus, which can be flattened by heat, multiple times without deforming the underlying film.
また、コンタクト形成前に水素処理を施すことにより、
コンタクト形成時の熱処理による変形のない眉間絶縁膜
を形成できた。In addition, by performing hydrogen treatment before contact formation,
We were able to form a glabella insulating film that was not deformed by heat treatment during contact formation.
第１図および第２図は本発明の一実施例を説明するため
の図、第３図は従来法の問題を説明するための図である
。
１．１１・・・・・・シリコン基板、２，１２・・・・
・・酸化シリコン膜、３．６，１０．２６・・・・・・
配線、７・・・・・・酸化シリコン膜、４，８・・・・
・・酸化シリコン膜、５．９・・・・・・酸化シリコン
膜、１３・・・・・・ゲート酸化膜、１４・・・・・・
ゲート電極、１５・・・・・・絶縁膜、１６・・・・・
・耐酸化性被膜、１７・・・・・・下部電極、１８・・
・・・・絶縁膜、１９・・・・・・上部電極、２２．２
８・・・・・・ホール、２３・・・・・・端部、２４・
・・・・・酸化シリコン膜、２５・・・・・・コンタク
トホール、２６・・・・・・配線、２０゜２１．２７・
・・・・・層間絶縁膜、３０・・・・・・ボイド。
代理人の氏名 弁理士 粟野重孝 ほか１名総ａ−１
Ｚ２
爪−ｌし
７Ａ２図
＆
ｌ−２イεジノコンＩ−１FIGS. 1 and 2 are diagrams for explaining one embodiment of the present invention, and FIG. 3 is a diagram for explaining the problems of the conventional method. 1.11...Silicon substrate, 2,12...
...Silicon oxide film, 3.6, 10.26...
Wiring, 7... Silicon oxide film, 4, 8...
...Silicon oxide film, 5.9...Silicon oxide film, 13...Gate oxide film, 14...
Gate electrode, 15... Insulating film, 16...
- Oxidation-resistant film, 17...Lower electrode, 18...
... Insulating film, 19 ... Upper electrode, 22.2
8...Hole, 23...End, 24.
...Silicon oxide film, 25...Contact hole, 26...Wiring, 20°21.27.
...Interlayer insulating film, 30...Void. Name of agent: Patent attorney Shigetaka Awano and 1 other person Total a-1 Z2 Nail-17A2 Diagram & l-2iε Ginocon I-1
Claims (3)
成長法にてリンを含む酸化シリコン膜を成長する工程と
、前記酸化シリコン膜を平坦化する工程と、水素雰囲気
にて８００℃、１０００℃の熱処理を施す工程とを有す
ることを特徴とする半導体装置の製造方法。(1) When forming an interlayer insulating film on a semiconductor substrate, a step of growing a silicon oxide film containing phosphorus by chemical vapor deposition, a step of planarizing the silicon oxide film, and a step of growing a silicon oxide film containing phosphorus in a hydrogen atmosphere for 800 hrs. A method for manufacturing a semiconductor device, comprising the steps of: performing heat treatment at 1000°C and 1000°C.
る工程と、前記第１の絶縁膜および前記半導体基板上の
所定領域に耐酸化性被膜を形成する工程と、前記第１の
絶縁膜と前記耐酸化性被膜と前記半導体基板上の所定領
域に第１の導電膜を形成する工程と、前記第１の導電膜
および前記耐酸化性被膜の所定領域に第２の絶縁膜を形
成する工程と、前記第２の絶縁膜および前記耐酸化性被
膜の一部に第２の導電膜を形成する工程を備えたことを
特徴とする半導体装置の製造方法。(2) forming a first insulating film in a predetermined region on a semiconductor substrate; forming an oxidation-resistant film in a predetermined region on the first insulating film and the semiconductor substrate; a step of forming a first conductive film on a predetermined region of the insulating film, the oxidation-resistant film, and the semiconductor substrate; and a step of forming a second insulating film on the predetermined region of the first conductive film and the oxidation-resistant film. A method for manufacturing a semiconductor device, comprising the steps of forming a second conductive film on a portion of the second insulating film and the oxidation-resistant film.
る工程と、前記第１の絶縁膜および前記半導体基板上の
所定領域に耐酸化性被膜を形成する工程と、前記第１の
絶縁膜と前記耐酸化性被膜と前記半導体基板上の所定領
域に第１の導電膜を形成する工程と、前記第１の導電膜
および前記耐酸化性被膜の所定領域に第２の絶縁膜を形
成する工程と、前記第２の絶縁膜および前記耐酸化性被
膜の一部に第２の導電膜を形成する工程と、前記半導体
基板全面に第３の絶縁膜を形成する工程と、前記第３の
絶縁膜の所定領域をエッチングし、前記第２の導電膜を
露出する工程と、露出した前記第２の導電膜を酸化する
工程を備えたことを特徴とする半導体装置の製造方法。(3) forming a first insulating film in a predetermined region on a semiconductor substrate; forming an oxidation-resistant film in a predetermined region on the first insulating film and the semiconductor substrate; a step of forming a first conductive film on a predetermined region of the insulating film, the oxidation-resistant film, and the semiconductor substrate; and a step of forming a second insulating film on the predetermined region of the first conductive film and the oxidation-resistant film. a step of forming a second conductive film on a part of the second insulating film and the oxidation-resistant film; a step of forming a third insulating film on the entire surface of the semiconductor substrate; 3. A method for manufacturing a semiconductor device, comprising: etching a predetermined region of the insulating film to expose the second conductive film; and oxidizing the exposed second conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16718090A JPH0456222A (en) | 1990-06-25 | 1990-06-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16718090A JPH0456222A (en) | 1990-06-25 | 1990-06-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0456222A true JPH0456222A (en) | 1992-02-24 |
Family
ID=15844909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16718090A Pending JPH0456222A (en) | 1990-06-25 | 1990-06-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0456222A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012089802A (en) * | 2010-10-22 | 2012-05-10 | Toyota Motor Corp | Manufacturing method of semiconductor device |
| WO2018135541A1 (en) * | 2017-01-17 | 2018-07-26 | 株式会社デンソー | Semiconductor device and method for manufacturing same |
| JP2020181873A (en) * | 2019-04-24 | 2020-11-05 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method thereof |
-
1990
- 1990-06-25 JP JP16718090A patent/JPH0456222A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012089802A (en) * | 2010-10-22 | 2012-05-10 | Toyota Motor Corp | Manufacturing method of semiconductor device |
| WO2018135541A1 (en) * | 2017-01-17 | 2018-07-26 | 株式会社デンソー | Semiconductor device and method for manufacturing same |
| JP2018117016A (en) * | 2017-01-17 | 2018-07-26 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| CN110235229A (en) * | 2017-01-17 | 2019-09-13 | 株式会社电装 | Semiconductor device and its manufacturing method |
| US20190341308A1 (en) * | 2017-01-17 | 2019-11-07 | Denso Corporation | Semiconductor device and manufacturing method of semiconductor device |
| US10923395B2 (en) | 2017-01-17 | 2021-02-16 | Denso Corporation | Semiconductor device and manufacturing method of semiconductor device |
| CN110235229B (en) * | 2017-01-17 | 2022-08-12 | 株式会社电装 | Semiconductor device and method for manufacturing the same |
| JP2020181873A (en) * | 2019-04-24 | 2020-11-05 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method thereof |
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