JPS6365664A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS6365664A JPS6365664A JP21023386A JP21023386A JPS6365664A JP S6365664 A JPS6365664 A JP S6365664A JP 21023386 A JP21023386 A JP 21023386A JP 21023386 A JP21023386 A JP 21023386A JP S6365664 A JPS6365664 A JP S6365664A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon layer
- layer
- polysilicon
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 6
- 238000009826 distribution Methods 0.000 abstract description 5
- 238000000206 photolithography Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000003205 muscle Anatomy 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の製造方法に関し、特に回路抵
抗の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and particularly to a method of manufacturing a circuit resistor.
従来の半導体集積回路に形成される回路抵抗の製造方法
を第2図(a)〜(c)を用いて説明する。A method of manufacturing a conventional circuit resistor formed in a semiconductor integrated circuit will be described with reference to FIGS. 2(a) to 2(c).
まず、第2図(a)に示すようにP型半導体基板1表面
を熱酸化して第1の酸化膜2を形成した後、通常の気相
成長法により全面にポリシリコン層を形成する。次にP
型不純物を多量にイオン注入法によりポリシリコン層中
へ拡散させた後、通常の写真蝕刻法によりポリシリコン
層をパターニングし、抵抗体層3を形成する。First, as shown in FIG. 2(a), a first oxide film 2 is formed by thermally oxidizing the surface of a P-type semiconductor substrate 1, and then a polysilicon layer is formed over the entire surface by a normal vapor phase growth method. Then P
After a large amount of type impurity is diffused into the polysilicon layer by ion implantation, the polysilicon layer is patterned by ordinary photolithography to form resistor layer 3.
次に第2図(b>に示すように通常の気相成長法により
第2の酸化膜4を全面に形成する。 次に第2図(
c)に示すように、第2の酸化膜層4の一部をエツチン
グ除去し、抵抗体層3の一部を露出させる。続いて高温
熱処理(950〜1000℃)してポリシリコンからな
る抵抗体層3をアニールした後、特性引出し用電極6を
形成し回路抵抗を完成させる。Next, as shown in FIG. 2(b), a second oxide film 4 is formed on the entire surface by a normal vapor phase growth method.Next, as shown in FIG.
As shown in c), a portion of the second oxide film layer 4 is removed by etching to expose a portion of the resistor layer 3. Subsequently, the resistor layer 3 made of polysilicon is annealed by high-temperature heat treatment (950 to 1000° C.), and then an electrode 6 for extracting characteristics is formed to complete the circuit resistance.
しかしながら、上述した従来の回路抵抗の製造方法では
、ポリシリコン層のエツチングが、P型不純物をイオン
注入により導入した直後に行なわれるため、第3図のA
線で示したようにその不均一な不純物濃度分布により、
通常のプラズマエツチング法あるいは希弗硝酸系エツチ
ング法のいずれを用いてもポリシリコンからなる抵抗体
層3の側壁3Bが第2図(a)に示したようにオーバー
ハング形状に加工される。その結果後工程の写真蝕刻工
程におけるホトレジスト層や電極用の金属層が薄く形成
されたり、電極配線に断線を生じ、信頼性を低下させる
等の問題点があった。However, in the conventional circuit resistor manufacturing method described above, etching of the polysilicon layer is performed immediately after introducing P-type impurities by ion implantation.
As shown by the line, due to the uneven impurity concentration distribution,
By using either the ordinary plasma etching method or the dilute fluorinitrate etching method, the side wall 3B of the resistor layer 3 made of polysilicon is processed into an overhang shape as shown in FIG. 2(a). As a result, there are problems such as the photoresist layer and the metal layer for electrodes being formed thinly in the subsequent photolithography process, and disconnections occurring in the electrode wiring, resulting in a decrease in reliability.
本発明の目的は、信頼性の向上した回路抵抗を有する半
導体集積回路の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit having circuit resistance with improved reliability.
本発明の半導体集積回路の製造方法は、−導電型半導体
基板上に絶縁膜を形成する工程と、この絶縁膜上にポリ
シリコン層を形成する工程と、このポリシリコン層に一
導電型不純物をイオン注入したのち低温熱処理を行なう
工程と、熱処理されたポリシリコン層をパターニングし
抵抗体層を形成する工程と、この抵抗体層を高温熱処理
する工程とを含んで構成される。The method for manufacturing a semiconductor integrated circuit of the present invention includes the following steps: - forming an insulating film on a conductivity type semiconductor substrate; forming a polysilicon layer on the insulating film; and doping impurities of one conductivity type in the polysilicon layer. The method includes a step of performing low-temperature heat treatment after ion implantation, a step of patterning the heat-treated polysilicon layer to form a resistor layer, and a step of subjecting the resistor layer to high-temperature heat treatment.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(c)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
まず1、第1図(a)に示すように、P型半導体基板1
表面にS t 02からなる第1の酸化膜2を形成した
のち、気相成長法により全面にポリシリコン層を形成す
る。続いてP型不純物を多量にイオン注入によりポリシ
リコン層中に拡散させたのち、低温(650〜800℃
)で約10〜120分間熱処理を行ない、イオン注入法
で導入された不純物の濃度分布を第3図のB線で示すよ
うに均一化させる。次に、通常の写真蝕刻法を用いてポ
リシリコン層の一部をエツチング除去する。First, as shown in FIG. 1(a), a P-type semiconductor substrate 1
After forming the first oxide film 2 made of S t 02 on the surface, a polysilicon layer is formed on the entire surface by vapor phase growth. Next, a large amount of P-type impurity is diffused into the polysilicon layer by ion implantation, and then heated at a low temperature (650 to 800℃).
) for about 10 to 120 minutes to make the concentration distribution of impurities introduced by ion implantation uniform as shown by line B in FIG. Next, a portion of the polysilicon layer is etched away using conventional photolithography.
次に、第1図(b)に示すように、気相成長法により第
2の酸化膜4を全面に形成する。Next, as shown in FIG. 1(b), a second oxide film 4 is formed over the entire surface by vapor phase growth.
次に第1図(C)に示すように、従来の製造方法と同様
に高温熱処理(950〜1000℃)してポリシリコン
からなる抵抗体層3をアニールしたのち、特性引出し用
電極5を形成し回路抵抗を完成させる。Next, as shown in FIG. 1(C), the resistor layer 3 made of polysilicon is annealed by high-temperature heat treatment (950 to 1000°C) in the same way as in the conventional manufacturing method, and then the electrode 5 for extracting characteristics is formed. and complete the circuit resistance.
このように本実施例においては、ポリシリコン層のエツ
チングが、イオン注入後の低温熱処理により不純物濃度
分布の均一化後に行なわれるため、従来のように、抵抗
体層3の側壁3Aがオーバーハング形状になる恐れは全
くなくなる。その結果写真蝕刻工程におけるホトレジス
ト層や電極用金属層が薄く形成されたり、電極配線に断
線を生じたりすることがなくなり、信頼性を大幅に向上
させることができる。In this embodiment, the etching of the polysilicon layer is performed after the impurity concentration distribution is made uniform by low-temperature heat treatment after ion implantation, so that the sidewall 3A of the resistor layer 3 has an overhang shape as in the conventional etching process. There is no longer any fear of becoming As a result, the photoresist layer and the metal layer for electrodes are not formed thinly in the photolithography process, and the electrode wiring is not broken, so that reliability can be greatly improved.
尚、上記実施例では低温熱処理温度として650〜80
0℃を適用したが、抵抗体層の側壁の断面形状からいえ
ば850℃〜1000℃が最適である。しかしながら9
00℃以上の温度ではすでに形成されている諸拡散層、
特にバイポーラトランジスタのベース低温度拡散層の深
さが無視できない程変動するため、800℃以上の熱処
理は実際には不可能である。In the above example, the low temperature heat treatment temperature was 650 to 80.
Although 0°C was applied, 850°C to 1000°C is optimal considering the cross-sectional shape of the side wall of the resistor layer. However, 9
Various diffusion layers that are already formed at temperatures above 00°C,
In particular, since the depth of the base low-temperature diffusion layer of a bipolar transistor varies to a degree that cannot be ignored, heat treatment at 800° C. or higher is actually impossible.
以上説明したように本発明は、ポリシリコン層に不純物
を導入し、低温処理して不純物の分布濃度を均一にした
後パターニングして抵抗体層を形成することにより、電
極配線の断線がなく信頼性の向上した回線抵抗を有する
半導体集積回路が得られる。As explained above, the present invention introduces impurities into a polysilicon layer, performs low-temperature treatment to make the distribution concentration of the impurities uniform, and then patterns it to form a resistor layer, which eliminates disconnection of electrode wiring and provides reliability. A semiconductor integrated circuit having improved line resistance can be obtained.
第1図(a)〜(C)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図(a
)〜(C)は従来の半導体集積回路の製造方法を説明す
るための工程順に示した半導体チップの断面図、第3図
はポリシリコンからなる抵抗体層の深さと不純物濃度と
の関係を示す図である。
1・・・P型半導体基板、2・・・第1の酸化膜、3・
・・抵抗体層、3A、3B・・・側壁、4・・・第2の
酸化膜、5・・・特性引出し用電極。
筋1図1(a) to 1(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (C) are cross-sectional views of a semiconductor chip shown in the order of steps to explain a conventional method of manufacturing a semiconductor integrated circuit, and FIG. 3 shows the relationship between the depth and impurity concentration of a resistor layer made of polysilicon. It is a diagram. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... First oxide film, 3...
...Resistor layer, 3A, 3B... Side wall, 4... Second oxide film, 5... Characteristic extracting electrode. Muscle 1 diagram
Claims (1)
縁膜上にポリシリコン層を形成する工程と、該ポリシコ
ン層に一導電型不純物をイオン注入したのち低温熱処理
を行なう工程と、熱処理された前記ポリシコン層をパタ
ーニングし抵抗体層を形成する工程と、該抵抗体層を高
温熱処理する工程とを含むことを特徴とする半導体集積
回路の製造方法。A step of forming an insulating film on a semiconductor substrate of one conductivity type, a step of forming a polysilicon layer on the insulating film, a step of ion-implanting an impurity of one conductivity type into the polysilicon layer and then performing low-temperature heat treatment, and heat treatment. A method for manufacturing a semiconductor integrated circuit, comprising the steps of: patterning the polysilicon layer to form a resistor layer; and subjecting the resistor layer to high-temperature heat treatment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61210233A JPH061803B2 (en) | 1986-09-05 | 1986-09-05 | Method for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61210233A JPH061803B2 (en) | 1986-09-05 | 1986-09-05 | Method for manufacturing semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6365664A true JPS6365664A (en) | 1988-03-24 |
JPH061803B2 JPH061803B2 (en) | 1994-01-05 |
Family
ID=16585989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61210233A Expired - Fee Related JPH061803B2 (en) | 1986-09-05 | 1986-09-05 | Method for manufacturing semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH061803B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06318676A (en) * | 1993-05-07 | 1994-11-15 | Nec Corp | Manufacture of semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5916361A (en) * | 1982-07-19 | 1984-01-27 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1986
- 1986-09-05 JP JP61210233A patent/JPH061803B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5916361A (en) * | 1982-07-19 | 1984-01-27 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06318676A (en) * | 1993-05-07 | 1994-11-15 | Nec Corp | Manufacture of semiconductor device |
US5420053A (en) * | 1993-05-07 | 1995-05-30 | Nec Corporation | Method for manufacturing semiconductor device having bipolar transistor and polycrystalline silicon resistor |
Also Published As
Publication number | Publication date |
---|---|
JPH061803B2 (en) | 1994-01-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6187368A (en) | Self-matching metal silicide process for ic having self-matching polycrystalline silicon electrode | |
US4343080A (en) | Method of producing a semiconductor device | |
US4376664A (en) | Method of producing a semiconductor device | |
JPS6365664A (en) | Manufacture of semiconductor integrated circuit | |
JPS5878457A (en) | Manufacture of semiconductor device | |
JPS6220711B2 (en) | ||
JPS6068656A (en) | Manufacture of semiconductor device | |
JPS60258964A (en) | Manufacture of semiconductor device | |
JPH0456222A (en) | Manufacture of semiconductor device | |
JPS6188543A (en) | Manufacture of semiconductor device | |
JP2745946B2 (en) | Method for manufacturing semiconductor integrated circuit | |
JPH04142777A (en) | Forming method for gate electrode or wiring | |
JPH0247853B2 (en) | ||
JPS6115579B2 (en) | ||
JP2546650B2 (en) | Method of manufacturing bipolar transistor | |
JPH01108772A (en) | Manufacture of bipolar transistor | |
JPS5942979B2 (en) | Manufacturing method of semiconductor device | |
JPH01245560A (en) | Manufacture of semiconductor device | |
JPH04152531A (en) | Manufacture of semiconductor device | |
JPS5826177B2 (en) | Manufacturing method of semiconductor device | |
JPS6018935A (en) | Manufacture of semiconductor device | |
JPH01289165A (en) | Manufacture of semiconductor device | |
JPH04168764A (en) | Manufacture of semiconductor device | |
JPH04192335A (en) | Manufacture of semiconductor device | |
JPH01144679A (en) | Manufacture of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |