JPS6018935A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS6018935A
JPS6018935A JP12670383A JP12670383A JPS6018935A JP S6018935 A JPS6018935 A JP S6018935A JP 12670383 A JP12670383 A JP 12670383A JP 12670383 A JP12670383 A JP 12670383A JP S6018935 A JPS6018935 A JP S6018935A
Authority
JP
Japan
Prior art keywords
film
oxide film
silicon oxide
layer polysilicon
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12670383A
Other languages
Japanese (ja)
Inventor
Yoshitaka Narita
成田 宜隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12670383A priority Critical patent/JPS6018935A/en
Publication of JPS6018935A publication Critical patent/JPS6018935A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain double layer poly Si structure having high insulating properties by removing a thermal oxide film formed on the surface of a first layer poly Si film and forming a thermal oxide film on the surface of the first layer poly Si film again. CONSTITUTION:A Si oxide film 2 is grown on a semiconductor base body 1. A first layer poly Si film 3 is grown on the film 2, and phosphorus as an N type impurity is introduced. The film 3 is patterned to a desired shape to form a first layer poly Si film 3'. The film 3' is thermally oxidized in a high-temperature oxidizing atmosphere to form a Si oxide film 5. A film 4 is removed, and a final Si oxide film 5 between the first poly Si film-a second poly Si film is grown through second thermal oxidation in the high-temperature oxidizing atmosphere. Since a stepped section is reduced through the formation of the first oxide film and a removal by subsequent etching in the film 3' at that time, corner sections are rounded, and the film 5 shaped on the film 3' is formed in uniform thickness. A second layer poly Si film 6 is formed on the film 5. According to the method, the concentration of an electric field in the layer 3' section can be relaxed.

Description

【発明の詳細な説明】 〔発明の鵬する技術分野〕 本発明は、半導体装置の製造方法に関し、特に二層ポリ
シリコン構造を有する半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a two-layer polysilicon structure.

〔従来技術〕[Prior art]

一般に、ポリシリコンを熱酸化したときに得られるシリ
コン酸化膜は、単結晶シリコン酸化し次ときに得られる
シリコン酸化膜と比較して、絶縁性が悪く、これを改善
するには、高温酸化が効果があるということは、公知で
ある。
In general, the silicon oxide film obtained when polysilicon is thermally oxidized has poor insulation properties compared to the silicon oxide film obtained when monocrystalline silicon is oxidized, and to improve this, high-temperature oxidation is It is well known that it is effective.

しかし、第1層ポリシリコンに段差部分を持つ場合には
、この部分で電界集中が生じ、絶縁性の量素子等のよう
に薄いシリコン酸化膜が必要なときに段差部分で絶縁性
が低下するという欠点がある。
However, if the first layer polysilicon has a step part, electric field concentration occurs in this part, and when a thin silicon oxide film is required, such as in an insulating quantum element, the insulation property decreases at the step part. There is a drawback.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記欠点を除去し、第1層ポリシリコ
ン膜の段差部分での電界集中を緩和し、絶縁性の高い第
1層ポリシリコン−第2層ポリクリヨン間酸化膜を持っ
た二層ポリシリコン構造の半導体装置の製造方法を提供
することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks, alleviate electric field concentration at the stepped portion of the first layer polysilicon film, and provide a double layer with a highly insulating oxide film between the first layer polysilicon and the second layer polysilicon. An object of the present invention is to provide a method for manufacturing a semiconductor device having a layered polysilicon structure.

〔発明の構成〕 本発明の第1の発明の半導体装置の製造方法は、表面に
絶縁膜を有する半導体基体の上部表面に第1層ポリシリ
コン膜を成長する工程と、該第1層ポリシリコン膜を所
望の形状にバターニングする工程と、前記バターニング
された第1層ポリシリコン膜表面に高温酸化雰囲気中で
シリコン酸化膜を形成する工程と、該シリコン酸化膜を
除去する工程と、前記シリコン酸化膜を除去した第1層
ポリシリコン膜表面に高温酸化雰囲気中で再度クリコン
酸化膜を形成する工程と、前記シリコン酸化膜に扱われ
た全表面に第2層ポリシリコン膜を成長する工程とを含
んで構成される。
[Configuration of the Invention] A method for manufacturing a semiconductor device according to the first aspect of the present invention includes the steps of growing a first layer polysilicon film on the upper surface of a semiconductor substrate having an insulating film on the surface, and growing the first layer polysilicon film on the upper surface of a semiconductor substrate having an insulating film on the surface. a step of buttering the film into a desired shape, a step of forming a silicon oxide film on the surface of the buttered first layer polysilicon film in a high temperature oxidizing atmosphere, and a step of removing the silicon oxide film; A step of forming a silicon oxide film again in a high-temperature oxidizing atmosphere on the surface of the first layer polysilicon film from which the silicon oxide film has been removed, and a step of growing a second layer polysilicon film on the entire surface treated with the silicon oxide film. It consists of:

本発明の第2の発明の半導体装置の製造方法は表面に絶
縁膜を有する半導体基体2・の上部表面に第1層ポリシ
リコン膜を成長する工程と、該第1層ポリシリコン膜上
に耐酸化性材料膜を成長する工程と、該耐酸化性材料膜
と前記第1層ポリシリコン膜を順次所望する形状にパタ
ーニングする工程と、前記耐酸化性材料膜をマスクとし
高温酸化雰囲気中で酸化し前記第1層ポリシリコン膜側
面にシリコン酸化膜を成長する工程と、該7リコン酸化
膜をエツチング除去する工程と、前記耐酸化性材料膜を
エツチング除去する工程と、前記シリコン酸化膜及び耐
酸化性材料膜を除去した第1層ポリシリコン膜表面に高
温酸化雰囲気中でシリコン酸化膜を形成する工程と、前
記シリコン酸化膜に覆われた全表面に第2層ポリシリコ
ン膜を成長する工程とを含んで構成される。
The method for manufacturing a semiconductor device according to the second aspect of the present invention includes the steps of growing a first layer polysilicon film on the upper surface of a semiconductor substrate 2 having an insulating film on the surface, and forming an acid-resistant polysilicon film on the first layer polysilicon film. a step of growing an oxidation-resistant material film, a step of sequentially patterning the oxidation-resistant material film and the first layer polysilicon film into a desired shape, and oxidation in a high-temperature oxidation atmosphere using the oxidation-resistant material film as a mask. a step of growing a silicon oxide film on the side surface of the first layer polysilicon film; a step of etching away the silicon oxide film; a step of etching and removing the oxidation-resistant material film; a step of forming a silicon oxide film in a high-temperature oxidizing atmosphere on the surface of the first layer polysilicon film from which the oxidizing material film has been removed; and a step of growing a second layer polysilicon film on the entire surface covered with the silicon oxide film. It consists of:

〔実施例の説明〕[Explanation of Examples]

次に、本発明の実施例について、図面を参照して詳細に
説明する。
Next, embodiments of the present invention will be described in detail with reference to the drawings.

第1図(a)〜(d)は、本発明の第1の発明の詳細な
説明のための工程順に示した断面図である。
FIGS. 1(a) to 1(d) are cross-sectional views shown in order of steps for detailed explanation of the first invention of the present invention.

先ず、第1図(a)に示すように、半導体基体J上にク
リコン酸化膜2を500尤の厚さに成長させる。次にシ
リコン酸化膜2上に第1層ポリシリコン膜3をCVD法
により2000^の厚さに成長させ、次いで通常の気相
からの熱拡散法より、N型不純物であるリンを第1層ポ
リシリコン膜3に拡散する。このリンの導入はイオン注
入法によっ°Cもよい。
First, as shown in FIG. 1(a), a cricon oxide film 2 is grown on a semiconductor substrate J to a thickness of 500 mm. Next, a first layer polysilicon film 3 is grown on the silicon oxide film 2 to a thickness of 2000^ by the CVD method, and then phosphorus, which is an N-type impurity, is added to the first layer using a normal vapor phase thermal diffusion method. It diffuses into the polysilicon film 3. This phosphorus may be introduced by ion implantation at °C.

次に、第1図(b)に示すように、第1層ポリシリコン
膜3を通常のレジストをマスクとしたプラズマエツチン
グにより所望の形状にパターニングし第1層ポリシリコ
ン膜3′を形成後、該第1層ポリシリコン膜3′を11
00℃の高温酸素雰囲気中で熱酸化し、厚さ約80OA
のシリコン酸化膜4を形成する。
Next, as shown in FIG. 1(b), the first layer polysilicon film 3 is patterned into a desired shape by plasma etching using an ordinary resist as a mask to form a first layer polysilicon film 3'. The first layer polysilicon film 3' is 11
Thermal oxidation in a high-temperature oxygen atmosphere at 00°C to a thickness of approximately 80OA.
A silicon oxide film 4 is formed.

次に、第1図(C)に示すように、シリコン酸化膜4を
バッフアートフッ酸によりエツチング除去したのち、再
度1100℃の高温乾燥雰囲気中で熱酸化を行って、最
終的な第1ポリシリコン膜−第2ポリシリコン膜間のシ
リコン酸化膜5を40OAの厚さに成長させる。
Next, as shown in FIG. 1(C), after removing the silicon oxide film 4 by etching with buffered hydrofluoric acid, thermal oxidation is performed again in a dry atmosphere at a high temperature of 1100° C. to form the final first polyurethane. A silicon oxide film 5 between the silicon film and the second polysilicon film is grown to a thickness of 40 OA.

しかるときは、第1層ポリシリコン膜3′は最初の酸化
膜形成並びにその後のエツチング除去により段差が少く
なっているので第1図(C)のように角部は丸味を帯び
、その上に形成されたシリコン酸化膜5は均一な厚さに
形成されている。
In this case, the first layer polysilicon film 3' has fewer steps due to the initial oxide film formation and subsequent etching removal, so the corners are rounded as shown in FIG. The silicon oxide film 5 thus formed has a uniform thickness.

次に、第1図(d)に示すように、シリコン酸化膜5の
上にCVD法により第2層ポリシリコン膜6を500O
Aの厚さに成長させると二層ポリシリコン構造の容量素
子が形成できる。
Next, as shown in FIG. 1(d), a second layer polysilicon film 6 is formed on the silicon oxide film 5 at a film thickness of 500 nm by the CVD method.
When grown to a thickness of A, a capacitive element with a two-layer polysilicon structure can be formed.

以上により形成された二層ポリシリコン構造の半導体装
置、例えば容量素子は本発明のプロセスにより角部は丸
味を帯びて形成されているのでその上に形成された第1
層、第2層ポリシリコン間の絶縁膜は角部のないなめら
かな、しかも膜厚が均一に形成されているので絶縁性が
向上しリーク電流は小さくなる。また、第1層ポリシリ
コン膜3′にはN型不純物が拡散されているので、この
部分の抵抗が少くなり、容量素子の特性が大幅に向上す
る。
The semiconductor device with the two-layer polysilicon structure formed as described above, for example, the capacitor element, has rounded corners due to the process of the present invention.
The insulating film between the second polysilicon layer and the second polysilicon layer is smooth with no corners and has a uniform thickness, improving insulation and reducing leakage current. Furthermore, since N-type impurities are diffused into the first layer polysilicon film 3', the resistance of this portion is reduced, and the characteristics of the capacitive element are greatly improved.

第2図(a)〜(e)は本発明の第2の発明の詳細な説
明のだめの工程順に示した断面図である。
FIGS. 2(a) to 2(e) are cross-sectional views showing the process order of the second aspect of the present invention for detailed explanation.

先ず、第2図(a)に示すように、シリコン基体1上に
シリコン酸化膜2を50OAの厚さに成長させる。次い
でシリコン酸化膜2上に、第1層ポリシリコン膜3をC
V’D法により2000^の厚さに成長させ、通常気相
からの熱拡散法によって、N型不純物であるリンを拡散
する。なお本工程でポリシリコン膜成長方法はCVD法
以外の方法によってもよい。またリンの導入はイオン注
入法によってもよい。次に全面にCVD法によりシリコ
ン窒化膜7を400にの厚さ成長させる。
First, as shown in FIG. 2(a), a silicon oxide film 2 is grown on a silicon substrate 1 to a thickness of 50 OA. Next, a first layer polysilicon film 3 is deposited on the silicon oxide film 2.
It is grown to a thickness of 2000^ by the V'D method, and phosphorus, which is an N-type impurity, is diffused by a thermal diffusion method from the normal gas phase. Note that in this step, a method other than the CVD method may be used for growing the polysilicon film. Further, ion implantation may be used to introduce phosphorus. Next, a silicon nitride film 7 is grown to a thickness of 400 nm over the entire surface by CVD.

次に、第2・図(b)に示すように、シリコン窒化膜7
と第1層ポリシリコン膜3を通常のレジストをマスクと
したプラズマエツチングにより、順次所望の形状にパタ
ーニングし第1層ポリシリコン膜3′およびシリコン窒
化膜7′を形成する。
Next, as shown in FIG. 2 (b), the silicon nitride film 7
Then, the first layer polysilicon film 3 is sequentially patterned into a desired shape by plasma etching using an ordinary resist as a mask to form a first layer polysilicon film 3' and a silicon nitride film 7'.

次に、第2図(c)に示すようK、シリコン窒化膜7′
をマスクとして第1層ポリシリコン膜3′の側面に、1
100℃高温乾燥酸素雰囲気中で酸化し、シリコン酸化
膜8を形成する。このとき第1mのポリシリコン膜3′
の角部は酸化により丸味を帯びる。
Next, as shown in FIG. 2(c), K, silicon nitride film 7'
1 on the side surface of the first layer polysilicon film 3' using as a mask.
A silicon oxide film 8 is formed by oxidation in a dry oxygen atmosphere at a high temperature of 100°C. At this time, the first mth polysilicon film 3'
The corners become rounded due to oxidation.

次に、第2図(d)に示すように、第1層ポリシリコン
膜3′の側面に成長したシリコン酸化膜8をバッフアー
トフッ酸によりエツチング除去し、次いで耐酸化性マス
クとしたシリコン窒化膜7′を熱リン酸によって、順次
エツチング除去する。次いで、絽出された第1層ポリシ
リコン膜3′の表面を1100℃の高温乾燥酸素雰囲気
中で熱酸化を行い、シリコン酸化膜5を40OAの厚さ
に成長させる。
Next, as shown in FIG. 2(d), the silicon oxide film 8 grown on the side surface of the first layer polysilicon film 3' is removed by etching with buffered hydrofluoric acid, and then silicon nitride film 8, which is used as an oxidation-resistant mask, is removed. The film 7' is sequentially etched away using hot phosphoric acid. Next, the surface of the exposed first layer polysilicon film 3' is thermally oxidized in a high temperature dry oxygen atmosphere at 1100° C. to grow a silicon oxide film 5 to a thickness of 40 OA.

次に、第2図(e)に示すように、シリコン酸化膜5上
にCVD法により第2層ポリシリコン膜6を500OA
成長させると二層ポリシリコン’tlJ造の容量素子が
形成できる。
Next, as shown in FIG. 2(e), a second layer polysilicon film 6 is formed on the silicon oxide film 5 at a thickness of 500 OA by CVD.
When grown, a capacitive element made of two-layer polysilicon can be formed.

本発明の第2の発明による上記実施例では、前記実施例
と同じ効果を発揮すると共に一回目の高温酸化及びエツ
チング工程において、第1層ポリシリコン膜3′表面は
、耐酸化制料膜であるシリコン膜表面状態の悪化は起こ
らず、従来例と同様な第1層ポリシリコン膜の表面状態
を保っている。
The above embodiment according to the second aspect of the present invention exhibits the same effect as the above embodiment, and in the first high temperature oxidation and etching process, the surface of the first layer polysilicon film 3' is made of an oxidation-resistant control film. No deterioration of a certain silicon film surface condition occurs, and the surface condition of the first layer polysilicon film is maintained as in the conventional example.

このため第1層ポリシリコン膜段差のエッヂ鈍化による
絶縁性良化の効果が、第1層ポリシリコン膜表面状態の
悪化により低減されることがないので、第1層ポリシリ
コン膜段差のない平坦な構造の場合と同等の絶縁性を示
す。また本実施例においても第1層ポリシリコン膜にN
型不純物が添加されているので完成された容量素子の特
性を大幅に改善することができる。
Therefore, the effect of improving the insulation properties due to the edge blunting of the first layer polysilicon film is not reduced by deterioration of the surface condition of the first layer polysilicon film, so that the first layer polysilicon film is flat without any steps. It exhibits insulation properties equivalent to those with a similar structure. Also in this example, N is added to the first layer polysilicon film.
Since type impurities are added, the characteristics of the completed capacitive element can be greatly improved.

第3図は、第1層ポリシリコン膜に段差のない二層ポリ
シリコン構造の容量素子の断面図で比較のため引用した
FIG. 3 is a cross-sectional view of a capacitive element having a two-layer polysilicon structure in which there is no step in the first layer polysilicon film, and is cited for comparison.

第4図は上記した本発明の第1発明及び第2発明及び平
坦構造及び従来例の容量素子のリーク電流−電圧特性図
を示す。
FIG. 4 shows a leakage current-voltage characteristic diagram of the capacitive elements of the first and second aspects of the present invention, the flat structure, and the conventional example.

図より、明らかなように、本発明の第1発明の実施例は
従来例に比べ高い絶縁性を示すが、本発明の第2発明の
実施例では第1発明の実施例より更に高い絶縁性を示し
Cいる。そして第3図に示すような平坦構造の容量素子
と同等のI−V特性となっていることが明らかである。
As is clear from the figure, the embodiment of the first invention of the present invention exhibits higher insulation than the conventional example, but the embodiment of the second invention of the present invention has even higher insulation than the embodiment of the first invention. It shows C. It is clear that the IV characteristic is equivalent to that of a capacitive element having a flat structure as shown in FIG.

〔発明の効果〕〔Effect of the invention〕

以上説明したとおり、本発明によれば第1層ポリシリコ
ン膜の段差部分のエッチを鈍化し、その部分での電界集
中を緩和し、リークを抑制し、絶練性の高い第1層ポリ
シリコン膜−第2層ポリシリコン膜間の酸化膜を持った
二層ポリシリコン構造の半導体装置が得られる。
As explained above, according to the present invention, etching of the stepped portion of the first layer polysilicon film is slowed down, electric field concentration at that portion is alleviated, leakage is suppressed, and the first layer polysilicon film with high A semiconductor device having a two-layer polysilicon structure having an oxide film between the film and the second layer polysilicon film is obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の第1の発明の詳細な説
明のための工程順に示した断面図、第2図(a)〜(e
)は本発明の第2の発明の詳細な説明のための工程順に
示した断面図、第3図は第1層ポリシリコン膜に段差の
ない二層ポリシリコン構造の容量素子の断面図、第4図
は本発明の第1の発明及び第2の発明の一実施例並びに
従来例及び平坦構造の容量素子のリーク電流−電圧の特
性図である。 1°゛°°°°シリコン半導体基体、2・−・・・・シ
リコン酸化膜、3・・・・・・第1層ポリシリコン膜、
4・・・・・・シリコン酸化膜、5・・・・・・第1層
−第2層ポリシリコン膜間絶縁膜、6゛゛・°゛第第2
ポポリシリコン膜7・・。 ・・・マスク窒化膜、8・・・・・・シリコン酸化膜。 3 9 83区 第4図
FIGS. 1(a) to (d) are cross-sectional views shown in order of steps for detailed explanation of the first invention of the present invention, and FIGS. 2(a) to (e)
) is a cross-sectional view shown in the order of steps for detailed explanation of the second invention of the present invention, FIG. FIG. 4 is a leakage current-voltage characteristic diagram of an embodiment of the first invention and the second invention of the present invention, a conventional example, and a capacitor element with a flat structure. 1°゛°°°° silicon semiconductor substrate, 2... silicon oxide film, 3... first layer polysilicon film,
4...Silicon oxide film, 5...First layer-second layer polysilicon interlayer insulating film, 6゛゛・°゛second
Polysilicon film 7... ...Mask nitride film, 8...Silicon oxide film. 3 9 83 Wards Figure 4

Claims (3)

【特許請求の範囲】[Claims] (1) 表面に絶縁膜を有する半導体基体の上部表面に
第1層ポリシリコン膜を成長する工程と、該第1層ポリ
シリコン膜を所望の形状にバターニングする工程と、前
記バターニングされた第1層ポリシリコン膜表面に高温
酸化雰囲気中でシリコン酸化膜を形成する工程と、該シ
リコン酸化膜を除去する工程と、前記シリコン酸化膜を
除去した第1層ポリシリコン膜表面に高温酸化雰囲気中
で再度シリコン酸化膜を形成する工程と、前記シリコン
酸化膜に覆われた全表面に第2層ポリシリコン膜を成長
する工程とを含むことを特徴とする半導体装置の製造方
法。
(1) A step of growing a first layer polysilicon film on the upper surface of a semiconductor substrate having an insulating film on the surface, a step of patterning the first layer polysilicon film into a desired shape, and a step of A step of forming a silicon oxide film on the surface of the first layer polysilicon film in a high temperature oxidizing atmosphere, a step of removing the silicon oxide film, and a step of forming a silicon oxide film on the surface of the first layer polysilicon film from which the silicon oxide film has been removed in a high temperature oxidizing atmosphere. A method for manufacturing a semiconductor device, comprising the steps of: forming a silicon oxide film again; and growing a second layer polysilicon film on the entire surface covered with the silicon oxide film.
(2)表面に絶縁膜を有する半導体基体tの上部表面に
第1層ポリシリコン膜を成長する工程と、該第1層ポリ
シリコン膜上に耐酸化性材料膜を成長する工程と、該耐
酸化性材料膜と前記第1層ポリシリコン膜を順次所望す
る形状にバターニングする工程と、前記耐酸化性材料膜
をマスクとし高温酸化雰囲気中で酸化し前記第1層ポリ
シリコン模似面にシリコン酸化膜を成長する工程と、該
シリコン酸化膜をエツチング除去する工程と、前記耐酸
化性材料膜をエツチング除去する工程と、前記シリコン
酸化膜及び耐酸化性材1膜を除去した第1層ポリシリコ
ン膜表面に高温酸化雰囲気中でシリコン酸化膜を形成す
る工程と、前記シリコン酸化膜に櫟われた全表面に第2
層ポリシリコン膜を成長する工程とを含むことを特徴と
する半導体装置の製造方法。
(2) a step of growing a first layer polysilicon film on the upper surface of the semiconductor substrate t having an insulating film on the surface; a step of growing an oxidation-resistant material film on the first layer polysilicon film; and a step of growing an oxidation-resistant material film on the first layer polysilicon film; a step of sequentially patterning the oxidation-resistant material film and the first layer polysilicon film into a desired shape, and oxidizing the oxidation-resistant material film in a high temperature oxidizing atmosphere using the oxidation-resistant material film as a mask to form the first layer polysilicon simulated surface. A step of growing a silicon oxide film, a step of etching away the silicon oxide film, a step of etching away the oxidation-resistant material film, and a first layer from which the silicon oxide film and the first oxidation-resistant material film have been removed. A step of forming a silicon oxide film on the surface of the polysilicon film in a high-temperature oxidizing atmosphere, and a step of forming a second silicon oxide film on the entire surface defined by the silicon oxide film.
A method for manufacturing a semiconductor device, comprising the step of growing a layered polysilicon film.
(3)第1漸ポリシリコン膜にN型不純物が添加されて
いることを特徴とする特許請求の範囲第(1)項又は第
(2)項記載の半導体装置の製造方法。
(3) A method for manufacturing a semiconductor device according to claim (1) or (2), characterized in that an N-type impurity is added to the first polysilicon film.
JP12670383A 1983-07-12 1983-07-12 Manufacture of semiconductor device Pending JPS6018935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12670383A JPS6018935A (en) 1983-07-12 1983-07-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12670383A JPS6018935A (en) 1983-07-12 1983-07-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6018935A true JPS6018935A (en) 1985-01-31

Family

ID=14941758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12670383A Pending JPS6018935A (en) 1983-07-12 1983-07-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6018935A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269339A (en) * 1986-05-19 1987-11-21 Nec Corp Manufacture of semiconductor device
JPH0725388A (en) * 1993-09-06 1995-01-27 Kawasaki Heavy Ind Ltd Steering device for small planing boat

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269339A (en) * 1986-05-19 1987-11-21 Nec Corp Manufacture of semiconductor device
JPH0725388A (en) * 1993-09-06 1995-01-27 Kawasaki Heavy Ind Ltd Steering device for small planing boat

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