JPS6123363A - Semiconductor device and manufacture of the same - Google Patents
Semiconductor device and manufacture of the sameInfo
- Publication number
- JPS6123363A JPS6123363A JP14382784A JP14382784A JPS6123363A JP S6123363 A JPS6123363 A JP S6123363A JP 14382784 A JP14382784 A JP 14382784A JP 14382784 A JP14382784 A JP 14382784A JP S6123363 A JPS6123363 A JP S6123363A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- field oxide
- etching
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims description 41
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000004334 fluoridation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は素子分離性能のすぐれた半導体装置およびその
！ｌｌｌｌ法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a semiconductor device with excellent element isolation performance and its! Regarding the lllll method.
ＭＯ８型半導体装置においては素子分離のために厚い酸
化膜（フィールド酸化膜）を通常使用する。In MO8 type semiconductor devices, a thick oxide film (field oxide film) is usually used for element isolation.
これは第４図のｎチャネルＭＯＳトランジスタの各工程
を示す断面図に示される。まず、ｐ型シリ］ン基板１の
表面に熱酸化膜２を形成し、窒化シリコン膜３をＣＶＤ
法により形成し素子形成領域を残してエツチング除去し
く第４図（ａ））、この窒化シリコン膜３を酸化のマス
クとして約１０００℃の加熱酸素雰囲気中で酸化を行な
い、窒化シリコン膜を除去すると、素子形成領域以外の
領域に第４図（ｂ）に示すような厚いフィールド酸化膜
４が形成される。このように窒化シリコン膜をマスクと
してフィールド酸化膜を形成する方法は選択酸化法と称
される。なお、フィールド酸化膜４の下部にはホウ素等
を高ｍ瓜に拡散させたｐ＋反転領域５が形成され、素子
形成領域の半導体基板上には熱酸化によりゲート酸化膜
６が形成される（第４図（ｂ））。次に全面に多結晶シ
リコン層をＣＶＤ法により形成し、酸化膜と共にゲート
領域以外の部分を写真食刻法によりパターニングすると
ゲート電極７が得られる。このゲート電極７とフィール
ド酸化膜４をマスクとしてヒ素のイオン注入を行なうと
基板１中にはｎ＋領領域あるソース領域８およびドレイ
ン領域９が形成され、さらにソース領域８およびドレイ
ン領域９上の酸化膜を除去すると第４図（Ｃ）の状態が
得られる。最後にシリコン絶縁膜１０をＣＶ、 Ｄ法に
より形成し、ソース領域８、ゲート電極６、ドレイン領
域９にそれぞれ対応してシリコン絶縁膜１０に開孔を行
ない、全面にアルミニウムを蒸着した後写真型剣法によ
りバターニングを行なうとアルミニウム配線１１，１２
．１３が得られ、最後にリンシリケートガラス等の保護
膜１４を堆積形成することによりＭＯＳトランジスタが
完成する。This is shown in the cross-sectional view of FIG. 4 showing each step of the n-channel MOS transistor. First, a thermal oxide film 2 is formed on the surface of a p-type silicon substrate 1, and a silicon nitride film 3 is deposited by CVD.
The silicon nitride film 3 is etched away leaving the element formation region (FIG. 4(a)). Using this silicon nitride film 3 as an oxidation mask, oxidation is performed in a heated oxygen atmosphere at about 1000° C. to remove the silicon nitride film. A thick field oxide film 4 as shown in FIG. 4(b) is formed in a region other than the element forming region. This method of forming a field oxide film using a silicon nitride film as a mask is called a selective oxidation method. Note that a p+ inversion region 5 in which boron or the like is diffused to a high density is formed under the field oxide film 4, and a gate oxide film 6 is formed by thermal oxidation on the semiconductor substrate in the element formation region. Figure 4(b)). Next, a polycrystalline silicon layer is formed on the entire surface by the CVD method, and the portions other than the gate region are patterned together with the oxide film by the photolithography method to obtain the gate electrode 7. When arsenic ions are implanted using the gate electrode 7 and the field oxide film 4 as a mask, a source region 8 and a drain region 9 having n+ regions are formed in the substrate 1, and the oxidation on the source region 8 and the drain region 9 is formed. When the film is removed, the state shown in FIG. 4(C) is obtained. Finally, a silicon insulating film 10 is formed by CV and D methods, holes are made in the silicon insulating film 10 corresponding to the source region 8, gate electrode 6, and drain region 9, respectively, and aluminum is deposited on the entire surface, followed by a photo mold. When buttering is done using Kenpo, aluminum wiring 11, 12
．． 13 is obtained, and finally a protective film 14 of phosphosilicate glass or the like is deposited to complete the MOS transistor.
しかしながら、このような半導体装置の製造方法におい
ては途中工程においてフィールド酸化膜厚が減少するこ
とに起因して種々の問題が生じている。However, in such a method of manufacturing a semiconductor device, various problems arise due to the decrease in field oxide film thickness in the middle of the process.
すなわち、当初８５００八程度の膜厚で形成されたフィ
ールド酸化膜は素子形成領域の酸化膜をエツチング除去
する工程、ゲート電極をエツチング形成する工程、各工
程に対する前処理および後処理において行なわれるフッ
化水素（１１Ｆ ）処即により膜厚が減少して最終製品
では
４０００八程度まで減少する場合がある。このようなフ
ィールド酸化膜厚の減少はフィールド酸化膜のしきい値
電圧Ｖ□１の低下を招き、素子分離性能を悪化させ半導
体装置としての性能を損うことになる。このため、当初
のフィールド酸化膜厚を厚く形成しておく必要があるが
、ｉ ｏｏｏ℃の加熱酸素雰囲気中でのフィールド酸化
膜の形成は４０００人の場合７０分であるのに対し８５
００人の場合４００分と膜厚が厚くなるほど時間がかか
り、生産能率の低下を招くことになる。That is, the field oxide film, which was initially formed to a thickness of about 8,500 mm, was removed by fluoridation in the process of etching away the oxide film in the element formation region, the process of etching the gate electrode, and the pre-treatment and post-treatment for each process. The film thickness decreases due to hydrogen (11F) treatment, and may be reduced to about 40,000 mm in the final product. Such a decrease in the field oxide film thickness causes a decrease in the threshold voltage V□1 of the field oxide film, which deteriorates the element isolation performance and impairs the performance of the semiconductor device. For this reason, it is necessary to form the field oxide film thick at the beginning, but it takes 85 minutes to form the field oxide film in a heated oxygen atmosphere at 100°C, whereas it takes 70 minutes for 4000 people.
In the case of 00 people, it takes 400 minutes, and the thicker the film, the longer it takes, leading to a decrease in production efficiency.
また、フィールド酸化膜の厚さを厚く形成するほど窒化
シリコン膜下部にフィールド酸化膜が形成されて窒化シ
リコン膜が持上げられるバーズビークが生じやすく、集
積度向上の障害になる他、ストレスによるフィールド酸
化膜の結晶欠陥も発生しやすい。In addition, the thicker the field oxide film is formed, the more likely the field oxide film is to form under the silicon nitride film, causing bird's beaks where the silicon nitride film is lifted. Crystal defects are also likely to occur.
本発明は上記事情に鑑みてなされたもので、フィールド
酸化膜厚の減少が少なく、素子分離性能のすぐれた半導
体装置およびその製造方法を提供することを目的とする
。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, in which the field oxide film thickness is less reduced and the element isolation performance is excellent.
上記目的達成のため、本発明にかかる半導体装置におい
ては、半導体基板表面に形成され、素子分離を行なうフ
ィールド酸化膜と、このフィールド酸化膜で囲まれた素
子形成領域中の半導体基板上に形成された、酸化シリコ
ン膜および少なくとも１層の第１の耐エツチング性膜を
含むゲート絶縁膜と、少なくとも前記フィールド酸化膜
上に形成された少なくとも１層の第２の耐エツチング性
膜とを備えるようにしており、製造過程においてフィー
ルド酸化膜の厚さの変動が少なく十分な素子分離性能を
得ることができるものである。To achieve the above object, a semiconductor device according to the present invention includes a field oxide film formed on the surface of a semiconductor substrate for element isolation, and a field oxide film formed on the semiconductor substrate in an element formation region surrounded by the field oxide film. The gate insulating film includes a silicon oxide film and at least one first etching-resistant film, and at least one second etching-resistant film formed on at least the field oxide film. Therefore, there is little variation in the thickness of the field oxide film during the manufacturing process, and sufficient element isolation performance can be obtained.
また、本発明にかかる半導体装置の製造方法においては
、一導電型の半導体基板表面にフィールド酸化膜を形成
づ−る工程と、このフィールド酸化膜およびフィールド
酸化膜で囲まれた素子形成領域に形成されたゲート酸化
膜上に耐エツチング性膜を形成する工程と、前記素子形
成領域中のゲート領域に多結晶シリコン層をパターニン
グしてゲート電極を形成する工程と、このゲー１へ電極
の周囲の前記素子形成領域の半導体基板に逆導電型半導
体不純物を注入してソースおよびドレイン領域を形成す
る工程とを備えており、フィールド酸化膜の膜厚減少を
その上に形成された耐エツチング性膜にＪ：り防止し、
素子分離性能の良好な半導体装置を得ることができるも
のである。In addition, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a field oxide film on the surface of a semiconductor substrate of one conductivity type, and a step of forming a field oxide film on the surface of the semiconductor substrate of one conductivity type, and a step of forming a field oxide film on the field oxide film and an element formation region surrounded by the field oxide film. a step of forming an etching-resistant film on the gate oxide film, a step of patterning a polycrystalline silicon layer in the gate region in the element formation region to form a gate electrode, and a step of forming a gate electrode around the electrode on the gate 1. and forming source and drain regions by implanting opposite conductivity type semiconductor impurities into the semiconductor substrate in the element formation region, and reducing the thickness of the field oxide film to an etching-resistant film formed thereon. J: Prevents
A semiconductor device with good element isolation performance can be obtained.
以下、図面を参照しながら本発明の実施例のいくつかを
詳細に説明する。Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明にかかる半導体装置とそのｔ４１１■程
を示寸断面図であって、第１図（ｄ）が完成状態を示し
ている。これによれば、通常のｎヂャネルＭＯ８ｌ−ラ
ンジスタど同様にｐ型基板表面に形成されたフィールド
酸化膜４で囲まれた素子形成領域内に多結晶シリコンの
ゲート電極２３おＪニびその周囲にｎ十領域であるソー
ス領域２４およびドレイン領域２５が形成されているが
、ゲート絶縁膜は酸化膜６、窒化シリコン膜２１、酸化
膜２２ｉから成っており、この窒化シリコン幕２１はフ
ィールド酸化膜４およびソース領域２４、ドレイン領域
２５上にも連続して形成されている。FIG. 1 is a sectional view showing a semiconductor device according to the present invention and its sectional view at about t411■, and FIG. 1(d) shows the completed state. According to this, a gate electrode 23 of polycrystalline silicon is formed in the element formation region surrounded by a field oxide film 4 formed on the surface of a p-type substrate, and an n A source region 24 and a drain region 25 are formed, and the gate insulating film is made up of an oxide film 6, a silicon nitride film 21, and an oxide film 22i. It is also formed continuously on the source region 24 and drain region 25.
この窒化シリコン膜はフッ化水素（ＨＦ）に対する耐エ
ツチング性にすぐれている。例えばフッ化アンモニウム
（Ｎ８４Ｆ）の３０％水溶液に対するエツチング量は酸
化シリコン（Ｓｉ０２）は約８００人／分であるのに対
し、窒化シリコン（Ｓ１３Ｎ４）は約９八／分である。This silicon nitride film has excellent etching resistance against hydrogen fluoride (HF). For example, the etching rate for a 30% aqueous solution of ammonium fluoride (N84F) is approximately 800 per minute for silicon oxide (Si02), while it is approximately 98 per minute for silicon nitride (S13N4).
したがって、製造過程での膜厚減少が少なくて済むため
、フィールド酸化膜４の厚さは従来の膜厚減少分だ番プ
薄く形成されている。Therefore, since the reduction in film thickness during the manufacturing process is small, the thickness of the field oxide film 4 is made much thinner than in the conventional method.
このような半導体装置は次のような工程により製造され
る。・
まず、ｐ型シリコン基板１の表面に熱酸化膜２を約１０
００℃の加熱酸素雰囲気中で形成し、その上に窒化シリ
コン膜３をＣＶＤ法により形成し、素子形成領域を残し
てエツチング除去する（第１図（ａ））。−
このパターニングされた窒化シリコン膜３を酸化のマス
クとして約１０００℃の加熱酸素雰囲気中で酸化を行な
うと素子形成領域以外の領域に厚いフィールド酸化膜４
′が形成される。なお、このフィールド酸化膜４′の厚
さは従来のそれに比べ従来の膜厚減少分だけ薄く形成さ
れている。また、第１図（ａ）の段階で素子分離領域の
酸化膜２にホウ素イオンを注入しておくことによりフィ
ールド酸化膜４′の下部にはｐ＋反転防止領域５を形成
している。次に素子形成領域に残存している窒化シリコ
ン膜３と酸化シリコン膜２を除去し、改めて約１００人
の熱酸化膜６を形成し、フィールド酸化膜４′および熱
酸化膜６上の全面に窒化シリコン膜２１をＣＶＤ法によ
り約１００人の厚さで形成し、熱酸化により表面に薄い
酸化膜２２を形成する（第１図（ｂ））。Such a semiconductor device is manufactured by the following steps. - First, a thermal oxide film 2 is deposited on the surface of the p-type silicon substrate 1 for about 10 minutes.
A silicon nitride film 3 is formed thereon by a CVD method, and is removed by etching leaving an element formation region (FIG. 1(a)). - Using this patterned silicon nitride film 3 as an oxidation mask, oxidation is carried out in a heated oxygen atmosphere at approximately 1000°C, resulting in a thick field oxide film 4 in areas other than the element formation area.
' is formed. It should be noted that the thickness of this field oxide film 4' is made thinner than the conventional one by the same amount as the conventional film thickness. Further, by implanting boron ions into the oxide film 2 in the element isolation region at the stage shown in FIG. 1(a), a p+ inversion prevention region 5 is formed under the field oxide film 4'. Next, the silicon nitride film 3 and silicon oxide film 2 remaining in the element formation area are removed, and a thermal oxide film 6 of about 100 layers is formed again, covering the entire surface of the field oxide film 4' and the thermal oxide film 6. A silicon nitride film 21 is formed to a thickness of approximately 100 nm using the CVD method, and a thin oxide film 22 is formed on the surface by thermal oxidation (FIG. 1(b)).
次にこの酸化膜２２の上に多結晶シリコンをＣＶＤ法に
より堆積させ、ｎ型不純物であるリンを拡散させた後、
レジスト塗布してグー１〜電極部のみが残存するように
露光しプラズマエツチングによってグー１〜電極２３を
得る。このエツチングにおいては多結晶シリコンの酸化
シリコンに対する高い選択比があるため、窒化シリコン
膜２１はイのまま全面に残存する。さらにグー１へ電極
２３とフィールド酸化膜４′をマスクとしてｎ型不純物
であるヒ素をイオン注入するど、グー１〜電極の両側の
基板１中にｎ１領域であるソース領域２４およびドレイ
ン領域２５が形成される〈第１図（Ｃ））。なお、窒化
シリコン層２１はイオン注入を妨げるが、この場合非常
に薄いため、実際上はマスクにはならず、イオン注入が
行なわれる。Next, polycrystalline silicon is deposited on this oxide film 22 by the CVD method, and after diffusing phosphorus, which is an n-type impurity,
A resist is coated, exposed to light so that only the goo 1 to electrode portions remain, and goo 1 to electrode 23 are obtained by plasma etching. In this etching, since polycrystalline silicon has a high selectivity to silicon oxide, the silicon nitride film 21 remains as it is on the entire surface. Furthermore, by ion-implanting arsenic, which is an n-type impurity, into the goo 1 using the electrode 23 and the field oxide film 4' as a mask, a source region 24 and a drain region 25, which are n1 regions, are formed in the substrate 1 on both sides of the goo 1 and the electrode. is formed (Fig. 1(C)). Note that although the silicon nitride layer 21 hinders ion implantation, it is very thin in this case, so it does not actually serve as a mask, and ion implantation is performed.
最後に、全面にＣＶＤ法で酸化シリコン膜２６を形成し
、ゲート電極２２、ソース領域２４、ドレイン領域２５
の上から写真食刻技術を用いてコンタクトホールを形成
し、ざらに全面にアルミニウムを蒸着し、これをパター
ニングしてアルミニウム配線層２６，２７．２８を形成
した後、仝而にリンシリグー１−ガラス（ＰＳＧ）の保
護膜２９を形成することにより所望の半導体装置を得る
ことができる。Finally, a silicon oxide film 26 is formed on the entire surface by the CVD method, and the gate electrode 22, source region 24, drain region 25
Contact holes are formed from above using photolithography, aluminum is roughly vapor deposited over the entire surface, and this is patterned to form aluminum wiring layers 26, 27 and 28. By forming the protective film 29 of (PSG), a desired semiconductor device can be obtained.
第２図は本発明にかかる半導体装ｎおＪ：びその製造方
法の他の実施例を示す途中工程の断面図であって第１図
（Ｃ）に対応覆るものである。すなわち、窒化シリコン
膜２１はゲート電極の一部をなすためもともと厚く形成
することばできない上、ゲート電極２３のパターニング
の際に多少なりともエツチングされてさらに薄くなる。FIG. 2 is a sectional view showing an intermediate step in another embodiment of the method for manufacturing a semiconductor device according to the present invention, and corresponds to FIG. 1(C). That is, since the silicon nitride film 21 forms a part of the gate electrode, it cannot be formed thick to begin with, and it is etched to some extent during patterning of the gate electrode 23, making it even thinner.
そこでフィールド酸化膜がエツチングされることを防止
するため、ソース領域２４およびドレイン領域２５を形
成した後、ゲート電極部の多結晶シリコンの表面を低温
で酸化し窒化シリコン膜３０を全面に重ねて堆積形成し
たものである。この実施例ではフィールド酸化膜厚の減
少の危険がさらに少ない。To prevent the field oxide film from being etched, after forming the source region 24 and drain region 25, the surface of the polycrystalline silicon of the gate electrode portion is oxidized at a low temperature, and a silicon nitride film 30 is deposited over the entire surface. It was formed. In this embodiment there is even less risk of field oxide thickness reduction.
第３図は本発明にかかる半導体装置の他の実施例を示す
断面図であって、この例では窒化シリコン膜はフィール
ド酸化膜４′上に形成されｋもの２１′とゲート絶縁膜
の一部をなすもの２１″に分かれて形成されており、ソ
ース領域２４上およびドレイン領域２５上には形成され
ていない。このような構成を実現するには例えば第１図
（Ｃ）にお【プるゲート電極２３のパターニング後にソ
ース領域およびトレイン領域となる部分の上にある窒化
シリコン膜を反応性イオンエツチング等で除去すればよ
い。この結束イオン注入によるソース領域２４およびド
レイン領域２５の形成はより容易となる。FIG. 3 is a cross-sectional view showing another embodiment of the semiconductor device according to the present invention, in which the silicon nitride film is formed on the field oxide film 4' and a part of the gate insulating film 21'. 21", and is not formed on the source region 24 or the drain region 25. To realize such a structure, for example, as shown in FIG. After patterning the gate electrode 23, the silicon nitride film on the portions that will become the source region and the train region may be removed by reactive ion etching or the like.The formation of the source region 24 and the drain region 25 by this bundled ion implantation is easier. becomes.
以上の実施例においてはｎチャネルＭＯＳトランジスタ
を想定して説明したが、ｎチャネルＭＯＳトランジスタ
、０Ｍ０３等フィールド酸化膜およびゲート酸化膜を備
えたあらゆる半導体装置に適用するこができる。Although the above embodiments have been described assuming an n-channel MOS transistor, the present invention can be applied to any semiconductor device including an n-channel MOS transistor, 0M03, etc., and a field oxide film and a gate oxide film.
また、実施例においては耐エツチング性膜として窒化シ
リコンを用いたが、フッ化水素等の１ツヂングガスに対
して酸化シリコンとの間で選択比を有する材料であれば
使用することができる。Further, although silicon nitride is used as the etching-resistant film in the embodiment, any material can be used as long as it has a selectivity between silicon oxide and one etching gas such as hydrogen fluoride.
以上のように本発明にかかる半導体装置およびその製造
方法はゲート絶縁膜中およびフィールド酸化膜上に耐エ
ツチング性膜を備えているので製造過程でフィールド酸
化膜の膜厚減少がなく、このため最初から厚いフィール
ド酸化膜を形成する必要がないため、フィールド酸化膜
形成のための時間が短くなって生産能率が向上する。ま
たフィールド酸化膜厚が薄くて済むことからバーズビー
クが減少して素子領域を広くとることができ、高密度化
を実現できる。またストレスの減少による結晶欠陥の発
生を防止でき、さらにフィールド酸化膜厚が一定の厚さ
に維持されることから素子分離性能が向上し、半導体装
置の品質を向上させることができる。また耐エツチング
性膜は不純物の拡散も小さく、製造過程における汚染の
影響を減少させ半導体装置の特性をさらに向上させるこ
とができる。As described above, since the semiconductor device and the method for manufacturing the same according to the present invention are provided with the etching-resistant film in the gate insulating film and on the field oxide film, there is no reduction in the thickness of the field oxide film during the manufacturing process. Since there is no need to form a thick field oxide film, the time required to form the field oxide film is shortened and production efficiency is improved. Furthermore, since the field oxide film only needs to be thin, bird's beaks are reduced, the device area can be widened, and high density can be achieved. In addition, the occurrence of crystal defects due to the reduction in stress can be prevented, and since the field oxide film thickness is maintained at a constant thickness, element isolation performance can be improved, and the quality of semiconductor devices can be improved. Furthermore, the etching-resistant film has less diffusion of impurities, which reduces the influence of contamination during the manufacturing process and further improves the characteristics of the semiconductor device.
第１図は本発明にかかる半導体装置の￥Ｊ造方法の各工
程を示す断面図、第２図は本発明の他の実施例の途中工
程の状態を示す断面図、第３図は本発明の他の実施例に
かかる半導体装置の完成状態を示す断面図、第４図は従
来の半導体装置の？Ｊ造方法の各■程を示す断面図であ
る。
１・・・基板、４，４′・・・フィールド酸化膜、５・
・・フィールド反転防止層、６・・・ゲート酸化膜、７
゜２３・・・ゲート電極、８，２６・・・シリコン絶縁
膜、１１．１２，１３．２６．２７．２８．・・・アル
ミニウム配線、１４．２９・・・保護膜、２１．３０・
・・窒化シリコン膜、３１・・・多結晶シリコンゲート
電極酸化膜。FIG. 1 is a cross-sectional view showing each step of the JJ manufacturing method for a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view showing the state of an intermediate step in another embodiment of the present invention, and FIG. FIG. 4 is a sectional view showing a completed state of a semiconductor device according to another embodiment of the present invention. It is a sectional view showing each stage of the J construction method. 1...Substrate, 4,4'...Field oxide film, 5.
...Field inversion prevention layer, 6...Gate oxide film, 7
゜23... Gate electrode, 8, 26... Silicon insulating film, 11.12, 13.26.27.28. ...Aluminum wiring, 14.29...Protective film, 21.30.
...Silicon nitride film, 31...Polycrystalline silicon gate electrode oxide film.
Claims (1)
ルド酸化膜と、このフィールド酸化膜で囲まれた素子形
成領域中の半導体基板上に形成された、酸化シリコン膜
および少なくとも１層の第１の耐エッチング性膜を含む
ゲート絶縁膜と、少なくとも前記フィールド酸化膜上に
形成された少なくとも１層の第２の耐エッチング性膜と
、を備えた半導体装置。 ２、第１の耐エッチング性膜と第２の耐エッチング性膜
とが同一工程で形成されたものである特許請求の範囲第
１項記載の半導体装置。 ３、第２の耐エッチング性膜がソース領域およびゲート
領域上にも形成されたものである特許請求の範囲第１項
記載の半導体装置。 ４、耐エッチング性膜が窒化シリコン膜である特許請求
の範囲第１項ないし第３項のいずれか記載の半導体装置
。 ５、一導電型の半導体基板表面にフィールド酸化膜を形
成する工程と、このフィールド酸化膜およびフィールド
酸化膜で囲まれた素子形成領域に形成されたゲート酸化
膜上に耐エッチング性膜を形成する工程と、前記素子形
成領域中のゲート領域に多結晶シリコン層をパターニン
グしてゲート電極を形成する工程と、このゲート電極の
周囲の前記素子形成領域の半導体基板に逆導電型半導体
不純物を注入してソースおよびドレイン領域を形成する
工程と、を備えた半導体装置の製造方法。 ６、フィールド酸化膜の形成が選択酸化法で行なわれる
特許請求の範囲第５項記載の半導体装置の製造方法。 ７、ソースおよびドレイン領域上に形成された耐エッチ
ング性膜を除去する工程を含む特許請求の範囲第５項記
載の半導体装置の製造方法。 ８、ゲート電極を形成しその電極表面を酸化した後に少
なくともフィールド酸化膜上に耐エッチング性膜を重ね
て形成する工程を含む特許請求の範囲第５項記載の半導
体装置の製造方法。 ９、耐エッチング性膜が窒化シリコン膜である特許請求
の範囲第５項ないし第８項のいずれか記載の半導体装置
の製造方法。[Claims] 1. A field oxide film formed on the surface of a semiconductor substrate for element isolation, a silicon oxide film formed on the semiconductor substrate in an element formation region surrounded by the field oxide film, and at least A semiconductor device comprising: a gate insulating film including one layer of a first etching resistant film; and at least one second etching resistant film formed on at least the field oxide film. 2. The semiconductor device according to claim 1, wherein the first etching-resistant film and the second etching-resistant film are formed in the same process. 3. The semiconductor device according to claim 1, wherein the second etching-resistant film is also formed on the source region and the gate region. 4. The semiconductor device according to any one of claims 1 to 3, wherein the etching-resistant film is a silicon nitride film. 5. Forming a field oxide film on the surface of a semiconductor substrate of one conductivity type, and forming an etching-resistant film on this field oxide film and the gate oxide film formed in the element formation region surrounded by the field oxide film. a step of patterning a polycrystalline silicon layer in a gate region in the element formation region to form a gate electrode; and implanting an opposite conductivity type semiconductor impurity into the semiconductor substrate in the element formation region around the gate electrode. A method of manufacturing a semiconductor device, comprising: forming a source and a drain region. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the field oxide film is formed by a selective oxidation method. 7. The method of manufacturing a semiconductor device according to claim 5, which includes the step of removing the etching-resistant film formed on the source and drain regions. 8. The method of manufacturing a semiconductor device according to claim 5, which includes the step of forming an etching-resistant film over at least the field oxide film after forming the gate electrode and oxidizing the electrode surface. 9. The method of manufacturing a semiconductor device according to any one of claims 5 to 8, wherein the etching-resistant film is a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14382784A JPS6123363A (en) | 1984-07-11 | 1984-07-11 | Semiconductor device and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14382784A JPS6123363A (en) | 1984-07-11 | 1984-07-11 | Semiconductor device and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6123363A true JPS6123363A (en) | 1986-01-31 |
Family
ID=15347868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14382784A Pending JPS6123363A (en) | 1984-07-11 | 1984-07-11 | Semiconductor device and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123363A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5608252A (en) * | 1993-03-10 | 1997-03-04 | Sharp Microelectronics Technology, Inc. | Semiconductor with implanted dielectric layer having patched pin-holes |
| JP2007524992A (en) * | 2003-03-27 | 2007-08-30 | フリースケール セミコンダクター インコーポレイテッド | Method for forming a dual metal gate device |
| US8178401B2 (en) | 2005-08-25 | 2012-05-15 | Freescale Semiconductor, Inc. | Method for fabricating dual-metal gate device |
| US8382979B2 (en) | 2009-06-29 | 2013-02-26 | Shimadzu Corporation | Liquid chromatograph system |
-
1984
- 1984-07-11 JP JP14382784A patent/JPS6123363A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5608252A (en) * | 1993-03-10 | 1997-03-04 | Sharp Microelectronics Technology, Inc. | Semiconductor with implanted dielectric layer having patched pin-holes |
| JP2007524992A (en) * | 2003-03-27 | 2007-08-30 | フリースケール セミコンダクター インコーポレイテッド | Method for forming a dual metal gate device |
| US8178401B2 (en) | 2005-08-25 | 2012-05-15 | Freescale Semiconductor, Inc. | Method for fabricating dual-metal gate device |
| US8382979B2 (en) | 2009-06-29 | 2013-02-26 | Shimadzu Corporation | Liquid chromatograph system |
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