JP2007524992A - Method for forming a dual metal gate device - Google Patents

Abstract

A method for forming a MOS transistor (10) having a dual metal gate formed of dissimilar metals is provided. A gate dielectric (34) such as HfO ₂ is deposited on the semiconductor substrate (31). A sacrificial layer (35) is then deposited over the gate dielectric (34). The sacrificial layer (35) is patterned to expose the gate dielectric (34) over the first region (32) (eg, pMOS) of the substrate (31) and the second region (33) of the substrate (31). Ensure that the gate dielectric (34) over (eg nMOS) remains protected by the sacrificial layer (35). A first gate conductor material (51) is deposited over the remaining sacrificial region (35) and over the exposed gate dielectric (34). The first gate conductor material (51) is patterned so that the first gate conductor material (51) on the second region (33) of the substrate (31) is completely removed by etching. When removing the first gate conductor material (51), the sacrificial layer (35) on the second region (33) functions to prevent damage to the underlying dielectric material (34). it can.

Description

  The present invention relates generally to semiconductor device design and formation, and more particularly to metal oxide semiconductors having dual metal gates that can be formed such that damage to the dielectric material under the gates is mitigated. MOS) device design and formation.

  Semiconductor device technology must continue to improve in the submicron pattern size region. As a result of the reduced pattern size, device design and formation aspects that were once ignored due to the fact that only a secondary effect could be produced on long channel devices are now important, and conventional device designs and It has enabled a great many changes to the forming technology. For example, excessive reduction in channel length and gate oxide thickness of conventional MOS transistors can result in depletion of polysilicon gate, increase in gate resistance, increase in gate tunnel current, and device channel region of dopant (ie boron). Exacerbates the problem of punching through. In particular, the use of dual metal gate conductors and metal oxide (MeOx) gate dielectrics is currently being investigated in CMOS technology, which has previously used polysilicon as the gate conductor and silicon dioxide as the gate dielectric.

MeOx gate dielectric materials are advantageous because these materials exhibit fairly high dielectric constants (K) and thick gate dielectric layers can be deposited without adversely affecting the physical and electrical properties of the deposited dielectric layer. It is. For example, a thin oxide film is liable to break down when it is stressed by a large electric field. SiO ₂ can particularly withstand a maximum electric field of about 12 mv / cm. A number of transition metal oxides have been found to be suitable as an alternative to SiO ₂ in this application, such as zirconium, hafnium, aluminum, lanthanum, strontium, titanium, and The oxide of the combination of these metals is mentioned.

In addition to high performance gate dielectrics, techniques that use metal gates instead of polysilicon are attracting considerable attention. The metal gate not only prevents gate depletion and boron penetration, but also realizes a very low sheet resistance. In one approach, a monolithic gate structure can be incorporated into a CMOS design. This technique consistently uses a metal having a work function approximately in the middle between the valence band and the conduction band of silicon. However, when the metal work function is such a value, the resulting device threshold voltage V _T becomes too high to easily control channel doping. When counter doping is performed on the channel for lowering V _T , other problems such as deterioration of short channel characteristics and turn-off characteristics occur. Therefore, it has been proposed to apply one solution to CMOS design in a high density dual metal gate configuration. The expected CMOS transistor design for MeOx gate dielectric and high density dual metal gate conductor is described below.

  FIG. 1 is a simplified cross-sectional view of a prior art CMOS transistor 10 incorporating a MeOx gate dielectric 11 and a high density dual metal gate conductor 12. The CMOS transistor itself usually includes a pMOS transistor 101 formed in an n-well (not shown) and an nMOS transistor 102 formed in a p-well (not shown). The device designer knows a priori that the CMOS transistor 10 includes trench isolation (not shown in FIG. 1) in the substrate to isolate the pMOS transistor 101 from the nMOS transistor 102 (prior to logic and recognition). Known as absolute and obvious). The gate dielectric 11 is deposited on the surface of the semiconductor substrate so as to cover both the pMOS transistor 101 and the nMOS transistor 102. As suggested above, the CMOS transistor 10 also incorporates a dual metal gate conductor 12 in the form of a first metal gate conductor 121 and a second metal gate conductor 122. The first metal gate conductor 121 is formed by depositing on the gate dielectric 11 so as to cover the pMOS region 101. A second metal gate conductor 122 is deposited over the first metal gate conductor 121 and over the gate dielectric 11 so as to cover the nMOS region 102.

  As indicated above and for reasons that will now be described, the dual metal gate conductors 121 and 122 are formed of dissimilar metal materials. Specifically, the work function of the first metal conductor 121 (formed on the pMOS region 101) is close to the valence band of silicon, and the second metal conductor 122 (formed on the nMOS region 102) It has been found that favorable performance is obtained when the work function is close to the conduction band of silicon. In fact, for bulk CMOS with a gate length of less than 50 nanometers, it is quite likely that there are two different gate metals with their work functions within about 0.2 eV of the silicon band edge (valence band and conduction band). Well known. Thus, candidates for metal gate conductor 121 include rhenium, iridium, platinum, molybdenum, ruthenium, and ruthenium oxide, and candidates for metal gate conductor 122 include titanium, vanadium, zirconium, tantalum, aluminum, niobium, and nitride. Tantalum is mentioned. However, the materials listed above should not be considered exhaustive, and other metals, alloys, or compounds are known or suitable for use as gate conductors in dual metal gate structures. .

  Typically, the existing process for forming the gate structure of the CMOS transistor 10 proceeds as outlined in FIG. After depositing the MeOx gate dielectric 11 on the substrate surface, the first metal gate conductor 121 is deposited, preferably by chemical vapor deposition (CVD), although physical vapor deposition (PVD) or atomic layer deposition. Other deposition methods such as (ALD) can also be utilized. Next, the first metal material is patterned by photolithography to protect the first metal material on the pMOS region 101 with the photoresist 21. Next, as shown in FIG. 2, metal removal etching is performed to remove the first metal material covering the nMOS region 102 to the position of the dielectric layer 11. In one embodiment, metal removal can be performed by wet etching in a solution consisting of sulfuric acid, hydrogen peroxide, and water. Next, when a second metal material is deposited, the structure specifically shown in FIG. 1 is obtained.

  The above process may damage the gate dielectric 11 in the region above the nMOS region 102. A region susceptible to damage to the gate dielectric 11 is indicated by a broken line region 111 in FIG. The cause of this problem can be understood with reference to FIG. First, the gate dielectric 11 in the region covering the nMOS region 102 is sent to two metal deposition steps. That is, the first metal material is first deposited and then the second metal material is deposited. However, perhaps more detrimentally, the gate dielectric 11 of the nMOS portion is exposed to a metal removal etching process applied to the selective etching of the first metal material on the nMOS region. Removing the first metal 121 on the nMOS region 102 almost certainly damages the exposed gate dielectric.

While the above process has been shown to be applicable when using certain strong MeOx materials (eg, HfO ₂ ) as the gate dielectric material, other gate dielectrics have been described above for dual metal integration. You can expect to take damage if you carry out the process. Therefore, what is needed is a method of forming a dual metal gate device without damaging the MeOx dielectric layer.

As will become more apparent below, the present invention, in one aspect, is a method of forming a semiconductor device, such as a CMOS transistor, wherein the semiconductor device is formed of a high density formed of at least two different metal materials. Has a gate conductor. To date, in order to form MeOx gate dielectrics in CMOS devices with high density, a metal removal etch that stops at the MeOx layer is required, and this etch causes the first gate to deposit a second gate conductor material. Part of the conductor material can be removed. It has been found that etching to remove the first gate conductor material damages the underlying MeOx. The formation process described herein prevents damage that may be applied to the underlying gate dielectric, by protecting the gate dielectric with a sacrificial layer (eg, SiO ₂ ).

  The present method for forming a dual metal gate device will be more fully understood by those skilled in the art by referring to the figures shown in simplified form immediately below and attached hereto. Although many features, advantages and functions of the method will be apparent to those skilled in the art, the same reference number (if any) is the same or similar in several of these figures. Points to the element.

  For those skilled in the art, the components of the figures are shown for simplicity and clarity of illustration and are not necessarily drawn to scale (unless otherwise noted in the description). For example, the dimensions of some components in the figure can be exaggerated relative to other components to facilitate and deepen understanding of embodiments of the present invention.

For a full understanding of the present method for forming a dual metal gate device, reference is made to the detailed description, including the appended claims, in conjunction with the accompanying figures.
As will become more apparent below, the present invention, in one aspect, is a method of forming a semiconductor device, such as a CMOS transistor, wherein the semiconductor device is formed of a high density formed of at least two different metal materials. Has a gate conductor. To date, in order to form MeOx gate dielectrics in CMOS devices with high density, a metal removal etch that stops at the MeOx layer is required, and this etch causes the first gate to deposit a second gate conductor material. Part of the conductor material can be removed. It has been found that etching to remove the first gate conductor material damages the underlying MeOx. The formation process described herein prevents damage that may be applied to the underlying gate dielectric, by protecting the gate dielectric with a sacrificial layer (eg, SiO ₂ ).

  To understand the present invention, it is convenient to analyze FIGS. 3-6, all of which constitute a core aspect of the process flow that schematically illustrates the formation of a dual metal gate CMOS transistor. However, it should be understood here that, with respect to the invention described herein, the applicability of the invention is not limited to the formation of CMOS devices.

Turning now to FIG. 3, a semiconductor substrate 31 is provided according to a conventional method. A pMOS transistor 32 and an nMOS transistor 33 can be formed on the substrate 31. The method of forming the active device region on the substrate 31 is well known to those skilled in the art and is not shown in detail in FIG. In general, it is sufficient to describe that the substrate 31 comprises low impurity concentration n-type or p-type single crystal silicon. After introducing impurities into the substrate, an n-well (not shown) is formed in the substrate 31 to accommodate the pMOS transistor 32, and a p-well (not shown) is formed to accommodate the nMOS transistor 33. In general, the description associated with the twin well structure as proposed here is that the n-well is formed by selectively implanting the region of the substrate 31 where the pMOS transistor 32 is to be formed, and p The well is formed by selectively implanting the region of the substrate 31 where the nMOS transistor 33 is to be formed. In one embodiment, the n-well can confine itself within a tub having a p-type conductivity (tub: not shown). In another embodiment, the substrate 31 can include a low impurity concentration epitaxial layer, which is formed to cover the high impurity concentration bulk silicon. That is, the substrate 31 can actually be a P ⁻ epitaxial layer formed in P ⁺ bulk silicon. As is well known, the n-type conductive region can be formed by implanting phosphorus or arsenic, and the p-type conductive region can be formed by implanting boron or antimony. In practice, the pMOS and nMOS regions of the device are separated by an insulating structure (not shown). Various isolation methods are known and include LOCOS isolation, shallow trench isolation, deep trench isolation, and the like. Since the drawings and descriptions relating to the insulation isolation method are not considered to be shown again here, they are omitted for the sake of clarity and simplicity. Furthermore, since the silicon-on-insulator (SOI) structure can also be used to form CMOS devices, the present invention can be applied to SOI technology as well.

With continued reference to FIG. 3, it can be seen that the gate dielectric material 34 is formed on the surface 311 of the substrate 31. In a preferred embodiment, the dielectric material 34 is MeOx. In a preferred embodiment, MeOx34 may be a HfO _2. However, other suitable metal oxides include oxides or oxynitrides of zirconium, hafnium, aluminum, lanthanum, strontium, titanium, silicon, and combinations of these materials. The advantages of the MeOx gate dielectric have been listed above. Next, a sacrificial layer 35 is formed to cover the gate dielectric layer 34 to a thickness of 50 to 500 Angstroms in one embodiment. The sacrificial layer 35 can be SiO ₂ deposited by a known method. However, it is possible to organic polymers, photoresist, although other materials such as Si ₃ N ₄ used. It will become clear below that the layer 35 is important.

At this point, a photoresist layer 36 is formed on the sacrificial layer 35 and a portion 351 of the sacrificial layer 35 above the pMOS region is exposed and a portion 352 of the sacrificial layer 35 above the nMOS region. Is patterned so as to be protected by the photoresist 36. Please refer to FIG. In a preferred embodiment, a wet chemical etch process removes the portion 351 covering the dielectric material above the pMOS region of the sacrificial oxide. Specifically, when the sacrificial oxide layer 35 is SiO ₂ , the removal can be performed using an HF solution that does not attack the underlying MeOx layer 34. The results of performing this process step are shown in FIG. Note that the remaining portion 352 of the sacrificial layer 35 on the dielectric material 34 covers the nMOS region.

  When the residual sacrificial layer 352 is formed in the proper position, the first gate conductor material 51 is deposited on the dielectric material 34 covering the pMOS region and on the residual sacrificial layer 352. In one embodiment, the first gate conductor material 51 can be Ir, for example, and can have a thickness of 50-500 Angstroms. Other candidates for the first metal gate conductor material 51 include rhenium, platinum, molybdenum, ruthenium, and ruthenium oxide. The result obtained at this stage of the process is the initial gate structure shown in FIG.

  In the next process step, the first gate conductor material 51 is patterned using the photoresist 61. That is, the photoresist layer 61 is formed so as to cover a portion of the first gate conductor material located on the pMOS region. Next, a metal removal step is performed on the exposed portion of the first gate conductor 51 above the nMOS region of the device to remove the exposed portion to the position of the sacrificial layer, possibly to the sacrificial layer. The removal of the gate conductor is preferably performed by plasma dry etching using a gas. In the prior art, the lower MeOx layer is always attacked by plasma etching. Please refer to FIG. However, in the context of the present invention, the sacrificial layer 352 can eliminate such detrimental effects and completely remove the exposed gate conductor material without degrading the gate dielectric. The results obtained at this point are shown in FIG. Next, all of the remaining sacrificial layer 352 is removed by appropriate wet chemical etching, and the resist 61 is removed.

  In FIG. 7, the second gate conductor material 71 covers (i) the first gate conductor material 51 located on the dielectric 34 and on the pMOS region 32, and (ii) the dielectric on the nMOS region 33. The body material 34 is deposited so as to cover it. The second gate conductor material 71 can be TaSiN and can also have a thickness of 50-500 Angstroms. Other candidates for the second gate conductor material 71 include titanium, vanadium, zirconium, tantalum, aluminum, niobium, and tantalum nitride. The result is a high density dual metal gate (MOS) device with very good performance characteristics provided by a formation process that maintains the integrity of the gate dielectric.

  Thus, until now, it has been believed that the process for forming a high density dual metal gate CMOS transistor provides an opportunity for damage to the gate dielectric material. In one embodiment according to the prior art, damage will be primarily caused by the lack of selectivity in the metal etch process used to remove the first gate conductor covering the gate dielectric of the nMOS transistor. In particular, the underlying MeOx gate dielectric is also directly attacked by a gas plasma etch process commonly used to remove metal gate conductor material. The technique of providing a sacrificial layer covering this portion of the gate dielectric material to perform the metal removal step is a simple and easy to understand effective measure. The gate dielectric is easily resistant to erosion by wet chemical etching (eg, in HF solution) used to remove the sacrificial layer.

  Reference is now made herein to the specific embodiment in which the first gate conductor is first formed over the pMOS region of the CMOS transistor and then the second gate conductor is formed over the nMOS region. While have been described. In another embodiment, the first gate conductor can be formed over the nMOS region of the transistor. In this case, a metal (for example, TaSiN) that is more suitable for nMOS characteristics is first deposited. A second gate conductor is subsequently formed over the first gate conductor overlying the nMOS device and over the gate dielectric overlying the pMOS device in a manner that is exactly similar to the formation process described above. The second metal conductor of this example can also be Ir, for example. The important point here is that the present invention includes another process sequence in which a sacrificial layer is provided to protect the gate dielectric in order to form a high density dual metal gate conductor. However, regardless of the sequence in which the gate conductor is deposited, it is important that the appropriate gate conductor material must be matched to the conductivity type of the underlying device region for forming the conductor by the method specified above. It is.

In addition, many dry or wet etches or processes for metal removal can be used to remove the metal layer during the dual metal gate formation process. Similarly, although the present invention contemplates using SiO ₂ as the sacrificial layer, other materials may be used as the sacrificial layer 35, including but not limited to organic polymers, photoresists, Si ₃ N _4, etc. Good results will be obtained. In this regard, if the removal of the sacrificial layer itself is such that the process used to remove the sacrificial layer 35 does not cause appreciable degradation in the underlying dielectric, dry etching or wet etching or another available removal process. Can be done.

  Collecting experimental data obtained from dual metal CMOS devices formed according to the above description, it can be seen that device characteristics such as gate capacitance and gate leakage current are greatly improved by the present invention. In particular, the gate capacitance, particularly when a gate voltage of -1.0 to +1.0 volts is applied, is significantly greater than the gate capacitance exhibited by dual metal gate devices formed without using the advantages of the present invention. small. Similarly, it has been found that the gate leakage current is approximately two orders of magnitude smaller over the majority of the gate voltage range of 0-2.0 volts.

  In addition, sensible manufacturers suspect, for example, that the deposition of the sacrificial layer on the nMOS region and subsequent removal itself can result in damage to the underlying gate dielectric, but experimental analysis has shown that For example, it has been found that the gate characteristics are not degraded at all by removing the sacrificial layer. That is, the MeOx gate dielectric is not affected by sacrificial layer removal using wet chemical etching (eg, in HF solution). A configuration in which a single metal gate conductor is deposited over a MeOx gate dielectric, formed in accordance with the present invention as compared to a reference device formed according to a very simple configuration process with no intermediate steps to remove the sacrificial layer. It has been found that the resulting device has approximately the same gate capacitance and gate leakage characteristics.

  Thus, in the above description, the invention has been shown in connection with many specific embodiments in an illustrative manner and in a manner that provides a thorough understanding of the invention. However, one of ordinary skill in the art involved in the design and formation of semiconductor non-volatile memory devices will fall within the scope of the invention without departing from various modifications and changes to the specific embodiments described. It will be appreciated that can be added in Accordingly, the present invention should be construed as including not only all the main matters within the technical scope of the appended claims but also equivalents of these main matters. For example, the present invention should not be construed as limited to the particular materials and thicknesses specified herein. Similarly, those skilled in the art will understand that the conductivity types (P-type, N-type) can usually be reversed, assuming that the required consistency is maintained. Accordingly, the description and drawings are to be interpreted as illustrative rather than restrictive, and as a result, all modifications to the description and drawings, or wave forms of the description and drawings are within the scope of the invention. Is understood to be.

  Similarly, effects, advantages, functions, and operational issues, or solutions to other technical problems, have been listed with respect to specific embodiments of the invention as presented herein. However, effects, benefits, functions, and problem-solving, and all elements (groups) or restrictions that result in, or can make, or become more prominent, such effects, benefits, functions, and problem-solving ( Group) is an essential, necessary, or essential element or limitation of any claim or all claims, whether in explicit form or implied or estoppel. Should not be considered or interpreted. Further, as used herein, the terms “comprises”, “comprising”, or all other variations thereof are applied in an inclusive sense and comprise the set of elements cited. A process, method, product, or apparatus not only includes these citation elements, but is clearly not cited or listed but is otherwise not specific to such a process, method, product, or apparatus. Elements can also be included.

1 is a simplified cross-sectional view of a CMOS transistor incorporating a prior art MeOx gate dielectric (11) and high density dual metal gate (121, 122) conductors. FIG. 2 is a cross-sectional view illustrating a metal removal etching process performed in the process of forming the device of FIG. 1 and showing how damage is applied to a gate dielectric according to the prior art. FIG. 4 is a diagram showing a schematic process flow according to the present invention, and a cross-sectional view showing how damage to the gate dielectric can be avoided by using a sacrificial layer. FIG. 4 is a diagram showing a schematic process flow according to the present invention, and a cross-sectional view showing how damage to the gate dielectric can be avoided by using a sacrificial layer. FIG. 4 is a diagram showing a schematic process flow according to the present invention, and a cross-sectional view showing how damage to the gate dielectric can be avoided by using a sacrificial layer. FIG. 4 is a diagram showing a schematic process flow according to the present invention, and a cross-sectional view showing how damage to the gate dielectric can be avoided by using a sacrificial layer. FIG. 4 is a diagram showing a schematic process flow according to the present invention, and a cross-sectional view showing how damage to the gate dielectric can be avoided by using a sacrificial layer.

Claims (3)

Providing a semiconductor substrate having a surface and having a first region and a second region;
Forming a gate dielectric on a surface covering the first region and covering the second region;
Forming a sacrificial layer over the gate dielectric;
Patterning the sacrificial layer to expose the gate dielectric on the first region and the remaining sacrificial layer protecting the gate dielectric on the second region;
Depositing a first gate conductor material on the exposed gate dielectric and on the remaining sacrificial layer;
Patterning the first gate conductor material to expose the remaining sacrificial layer;
Removing the remaining sacrificial layer to expose the gate dielectric on the second region;
Depositing a second gate conductor material over the patterned first gate conductor material and overlying the gate dielectric exposed by patterning the first gate conductor material. Providing a semiconductor substrate having a surface and having a first region and a second region;
Forming a gate dielectric on a surface covering the first region and covering the second region;
Protecting the gate dielectric so that it is not affected by subsequent metal etching;
Depositing a first metal over the exposed gate dielectric on the first region;
Etching the first metal on the second region to remove all of the first metal. Providing a semiconductor substrate having a first region of a first conductivity type and a second region of a second conductivity type;
Forming a dielectric material on the surface of the substrate covering the first region and covering the second region;
Forming a sacrificial layer such that the dielectric material on the first region is exposed and the dielectric material on the second region is protected by the remaining sacrificial layer;
Depositing a first gate conductor material over the exposed dielectric material;
Removing the remaining sacrificial layer to expose the gate dielectric (first gate conductor material) on the second region;
Depositing a second gate conductor material on the exposed gate dielectric (first gate conductor material) overlying the second region.

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