JPS62265752A - Inverter - Google Patents
InverterInfo
- Publication number
- JPS62265752A JPS62265752A JP61110069A JP11006986A JPS62265752A JP S62265752 A JPS62265752 A JP S62265752A JP 61110069 A JP61110069 A JP 61110069A JP 11006986 A JP11006986 A JP 11006986A JP S62265752 A JPS62265752 A JP S62265752A
- Authority
- JP
- Japan
- Prior art keywords
- film
- fet
- protective film
- threshold voltage
- metal gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 6
- 229910008062 Si-SiO2 Inorganic materials 0.000 abstract 2
- 229910006403 Si—SiO2 Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003623 enhancer Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
Ｅ産業上の利用分野〕
本発明は半導体基板に形成されたＥ／ＤＭＯ８ＦＥＴに
よるインバータに関するものであり、特に金属ゲート雷
＋１Ｍ０３ＦＥＴによるインバータに関するものである
。Detailed Description of the Invention Field of Industrial Application] The present invention relates to an inverter using E/DMO8FETs formed on a semiconductor substrate, and particularly relates to an inverter using metal gate lightning+1M03FETs.
［従来の技術〕
Ｅ ／ Ｄ （Ｅｎｈａｎｃｅｍｅｎｔ／Ｄｅｐｌｅｔ
ｉｏｎＨＪｌ成のＭ Ｏ５ＦＥＴは第２図、第３図に示
すように構成されている。図はＮチャンネル型を示し、
Ｐ型半導体基板６には３つのＮ領域７．８．９が形成さ
れ、それぞれドレイン領域、島領域、及びソース領域に
対応する。領域７と島領域８との間、及びｖＩＩＯ２島
領ＩＩｉ！８との間の基板表面にはそれぞれエンハンス
メン１−Ｍ０８ＦＥ王のゲート酸化膜２、及びディプレ
ッションＭＯ８ＦＥＴのゲート酸化膜４が形成されてい
る。そして第２図にあっては、各ゲート酸化膜２．４上
にエンハンスメント、及びディプレッションＭＯ８Ｆ
Ｅ Ｔのゲート電１乍１．３が直接形成され、第３図に
あってはゲート酸化１漠２．４上にダメージ保護膜５．
６が形成され、その表面にゲート電極１．３が形成され
る。この保護膜５．６はゲート電極形成時のゲート耐１
ヒ腰を保護するために設けられている。またグーｌ−電
惜３．４はアルミニウム（Ａりを主成分とする金Ｒ？Ｉ
ｉであり、蒸着法、スパッタリング法などで同時に形成
される。[Conventional technology] E/D (Enhancement/Deplet
The ionHJ1 MO5FET is constructed as shown in FIGS. 2 and 3. The figure shows an N-channel type.
Three N regions 7.8.9 are formed in the P-type semiconductor substrate 6, corresponding to a drain region, an island region, and a source region, respectively. Between area 7 and island area 8, and vIIO2 island area IIi! A gate oxide film 2 of the enhancer 1-M08FE and a gate oxide film 4 of the depletion MO8FET are formed on the surface of the substrate between the transistors 8 and 8, respectively. In FIG. 2, enhancement and depletion MO8F are formed on each gate oxide film 2.4.
The gate electrodes 1 to 1.3 of the ET are directly formed, and in FIG. 3, a damage protection film 5.
6 is formed, and a gate electrode 1.3 is formed on the surface thereof. This protective film 5.6 has a gate resistance of 1 when forming the gate electrode.
It is provided to protect the lower back. In addition, Goo L-Dengai 3.4 is aluminum (gold R?I whose main component is A).
i, and are formed simultaneously by a vapor deposition method, a sputtering method, or the like.
このゲート電極３．４の形成工程において、シリコン基
板６とゲート酸化膜との境界、即らＳ。In the step of forming the gate electrode 3.4, the boundary between the silicon substrate 6 and the gate oxide film, ie, S.
一８ｉ○２界面に界面単位を発生させるので、第２図の
インバータにあっては、界面単位低減のために、一般に
△１を主成分とする金属膜（ゲート電極）１．３形成後
４５０℃以上、３０分以上のシンタ一工程を伴なう。ま
た第３図の溝成にあっては、ダメージ保護膜５．６はゲ
ート電極１．３形成時に６けるダメージ発生の保護膜で
あり、この保護膜５．６によりＳ、−８ｉＯ２界面での
界！
面単位の発生が抑制される。Since an interface unit is generated at the -8i○2 interface, in order to reduce the interface unit in the inverter shown in FIG. It involves a sintering process at a temperature of 30 minutes or more at a temperature of 30 minutes or more. In addition, in the groove formation shown in FIG. 3, the damage protection film 5.6 is a protection film for damage occurring during formation of the gate electrode 1.3, and this protection film 5.6 prevents damage at the S, -8iO2 interface. Kai! Occurrence on a per-plane basis is suppressed.
かかる従来のＭＯＳインバータの各ＦＥＴにおいては、
そのしきい値電圧は互いに異なる値である必要があるた
めに、何等かの方法により各ＦＥＴのチャンネル領域の
不純物密度を変化させている。例えば、Ｐ″基板よりエ
ンハンスメント型ＦＥＴの閾値電圧が決定される場合に
は、ディブレンジョン型ＦＥＴのチャンネル領域には、
ドナーとなるイオンをチアンネルドープすることにより
Ｐ型の不純物密度を下げるか、表面部分だけＮ型にして
いる。In each FET of such a conventional MOS inverter,
Since the threshold voltages need to be different values, the impurity density in the channel region of each FET is changed by some method. For example, when the threshold voltage of an enhancement type FET is determined from the P'' substrate, the channel region of the debension type FET is
Either the P-type impurity density is lowered by channel-doping donor ions, or only the surface portion is made N-type.
［発明が解決しようとする問題点］
かかる従来のインバータは、上述の如く閾値電圧が互い
に異なるように設定する必要があり、従って、例えばチ
ャンネルドープによって各トランジスタのチャンネル領
域の不純物密度を互いに異なるようにしなければならず
、プロセスか複雑になる。[Problems to be Solved by the Invention] In such conventional inverters, it is necessary to set the threshold voltages to be different from each other as described above, and therefore, for example, by channel doping, it is necessary to set the impurity density of the channel region of each transistor to be different from each other. The process becomes complicated.
［問題点を解決するための手段１
この光明はかかる従来の問題点に鑑み成されたものであ
り、金属ゲート下に保護膜を設けたり、ゲート絶縁膜に
直接ゲート金属膜を設けることにヨリ、Ｅ ／ Ｄ Ｍ
ＯＳ Ｖ４造ノインバータの各ＦＥＴのチャンネル部
分の不純物分布を異ならしめることなく、互いに異なる
閾値電圧かえられるインバータを提供することを目的と
している。[Means for solving the problem 1 This light was created in view of the problems of the conventional technology, and it does not involve providing a protective film under the metal gate or providing a gate metal film directly on the gate insulating film. ,E/DM
The object of the present invention is to provide an inverter in which different threshold voltages can be changed without making the impurity distribution in the channel portion of each FET of the OS V4 inverter different.
］発明の実施例； 以下この光明の実施例を図面と共に説明する。] Examples of the invention; Examples of this light will be described below with reference to the drawings.
第１図におけるこの発明の実施例はＮチアンネル型のＭ
ＯＳ Ｆ Ｅ Ｔによるインバータを示し、１はエン
ハンスメントＦＥＴの金属ゲート電極、２はエンハンス
メントＦＥＴのゲート酸化膜、５はエンハンスメントＦ
ＥＴの金属ゲート電極形成時のダメージ保護膜、３はデ
ィプレッションＦＥＴの金１属ゲート雷唖、４はディプ
レッションＦＥＴゲート酸化膜である。The embodiment of the invention shown in FIG.
This shows an inverter using OS FET, where 1 is the metal gate electrode of the enhancement FET, 2 is the gate oxide film of the enhancement FET, and 5 is the enhancement FET.
3 is a damage protection film when forming a metal gate electrode of an ET; 3 is a metal gate cap of a depletion FET; and 4 is a depletion FET gate oxide film.
かかる溝成において１．＼チアンネル型の場合、エンハ
ンスメントＦＥＴの金１属ゲート電橘の直下には、この
金属膜形成時のダメージを防止するための保護膜（例え
（ま２００Ａ程度のＳ１３＼４膜や多結晶シリコンＩＩ
り５が介在しているために、５ｉ−８ｉＯ２界面での大
きな界面単位の発生が抑制される。一方、ディプレッシ
ョンＦＥＴの金属ゲート電型３はその下に直接ゲート酸
化膜４が形成され、保護膜は存在しないのでＳ、−Ｓ、
Ｏ２覆
界面では大きな界面準位が発生し、正のキャリアがトラ
ップされて閾（直電圧を負の方向にシフ１−させる。こ
のため、チセンネル部の不純物分布が同じであっても、
エンハンスメンｌ−Ｆ Ｅ ＴとデイブレッシミンＦＥ
Ｔ戸の閾１直電圧を互いに異ならしめることができる。In such groove formation, 1. In the case of a channel type, a protective film (for example, S13\4 film of about 200A or polycrystalline silicon II
Because of the presence of the 5i-8iO2 interface, the generation of large interfacial units at the 5i-8iO2 interface is suppressed. On the other hand, in the metal gate type 3 of the depletion FET, the gate oxide film 4 is formed directly under it, and there is no protective film, so S, -S,
A large interface state is generated at the O2-covered interface, trapping positive carriers and shifting the threshold (direct voltage) in the negative direction.For this reason, even if the impurity distribution in the chisennel part is the same,
Enhancement l-FET and Day Blessingmin FE
The threshold 1 direct voltages of the T doors can be made different from each other.
なお、ゲート電極としての金属暎形成後４５０℃、３０
分以上程度の熱！１８浬を加えると、界面準位のほとん
どが消滅する恐れがあるので、金属税形成後の熱処理と
しては、４００〜４４０’Ｃ１１０分〜１８０分程度が
望ましい。In addition, after forming the metal layer as a gate electrode, it was heated at 450°C and 30°C.
Heat for more than a minute! If 18 min is added, most of the interface states may disappear, so the heat treatment after forming the metal layer is preferably about 400 to 440'C for 110 to 180 minutes.
また上記実施例では、Ｎチセンネル型ＭＯ８ＦＥＴによ
るインバータについて説明したが、Ｐチアンネル型であ
ってもよいこと（ま勿論である。この場合には、エンハ
ンスメント型ＦＥＴのゲーＩ・電極には保護膜を設けず
に、ディプレッジコン型ＦＥＴのゲート電極下に保護膜
を設ける。In addition, in the above embodiment, an inverter using an N channel type MO8FET was explained, but it is also possible to use a P channel type (of course. Instead, a protective film is provided under the gate electrode of the diplegcon type FET.
［発明の効果］
以上のようにこの発明によれは、Ｅ、’Ｄ〜１０８ＦＥ
Ｔの一方の全屈ゲート電り下のみに金冗配保形成時のダ
メージ保護膜を形成したので、各ＦＥ王のチャンネル部
分の不純物分布を変化させることなく閾値電圧を異なら
しめることができ、プロセスが簡単となる。[Effect of the invention] As described above, according to this invention, E, 'D~108FE
Since a damage protection film was formed only under the total gate voltage of one side of T, the threshold voltage can be made different without changing the impurity distribution in the channel part of each FE king. The process becomes easier.
第１図はこの発明にかかるインバータの実施例を示す断
面図、第２図、第３図はそれぞれ従来のインバータを示
す断面図である。
１．３・・・金属ゲーｊ−電極
２．４・・・ゲート酸化膜
５・・・ダメージ保護膜
６・・・基板
パイオニアビデフｒ体八云社
第１図
第２図
第３図FIG. 1 is a sectional view showing an embodiment of an inverter according to the present invention, and FIGS. 2 and 3 are sectional views showing conventional inverters. 1.3...Metal gate electrode 2.4...Gate oxide film 5...Damage protection film 6...Substrate Pioneer Bidefr Body Yaunsha Figure 1 Figure 2 Figure 3
Claims (1)
ＥＴにより構成されるインバータであって、閾値電圧が
より正なるＭＯＳＦＥＴには金属ゲートとゲート絶縁膜
間に保護膜を設け、閾値電圧がより負のＭＯＳＦＥＴに
は前記保護膜を設けないようにしたことを特徴とするイ
ンバータ。Multiple metal gate electrodes MOSF formed on a semiconductor substrate
In an inverter configured with an ET, a protective film is provided between the metal gate and the gate insulating film for MOSFETs whose threshold voltage is more positive, and the protective film is not provided for MOSFETs whose threshold voltage is more negative. An inverter characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61110069A JPS62265752A (en) | 1986-05-14 | 1986-05-14 | Inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61110069A JPS62265752A (en) | 1986-05-14 | 1986-05-14 | Inverter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62265752A true JPS62265752A (en) | 1987-11-18 |
Family
ID=14526264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61110069A Pending JPS62265752A (en) | 1986-05-14 | 1986-05-14 | Inverter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62265752A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02164755A (en) * | 1988-12-16 | 1990-06-25 | Tokuhito Shibata | Concrete improver and improvement of concrete |
| WO2007004258A1 (en) * | 2005-06-30 | 2007-01-11 | Spansion Llc | Semiconductor device and fabrication method thereof |
| JP2007524992A (en) * | 2003-03-27 | 2007-08-30 | フリースケール セミコンダクター インコーポレイテッド | Method for forming a dual metal gate device |
| WO2010018070A1 (en) * | 2008-08-12 | 2010-02-18 | International Business Machines Corporation | Metal-gate high-k reference structure |
| US8178401B2 (en) | 2005-08-25 | 2012-05-15 | Freescale Semiconductor, Inc. | Method for fabricating dual-metal gate device |
-
1986
- 1986-05-14 JP JP61110069A patent/JPS62265752A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02164755A (en) * | 1988-12-16 | 1990-06-25 | Tokuhito Shibata | Concrete improver and improvement of concrete |
| JP2007524992A (en) * | 2003-03-27 | 2007-08-30 | フリースケール セミコンダクター インコーポレイテッド | Method for forming a dual metal gate device |
| WO2007004258A1 (en) * | 2005-06-30 | 2007-01-11 | Spansion Llc | Semiconductor device and fabrication method thereof |
| JPWO2007004258A1 (en) * | 2005-06-30 | 2009-01-22 | スパンション エルエルシー | Semiconductor device and manufacturing method thereof |
| US8076753B2 (en) | 2005-06-30 | 2011-12-13 | Spansion Llc | Semiconductor device and method of manufacturing the same |
| US8642422B2 (en) | 2005-06-30 | 2014-02-04 | Spansion Llc | Method of manufacturing a semiconductor device |
| US8698280B2 (en) | 2005-06-30 | 2014-04-15 | Spansion Llc | Capacitive element using MOS transistors |
| US8178401B2 (en) | 2005-08-25 | 2012-05-15 | Freescale Semiconductor, Inc. | Method for fabricating dual-metal gate device |
| WO2010018070A1 (en) * | 2008-08-12 | 2010-02-18 | International Business Machines Corporation | Metal-gate high-k reference structure |
| US7951678B2 (en) | 2008-08-12 | 2011-05-31 | International Business Machines Corporation | Metal-gate high-k reference structure |
| US8513739B2 (en) | 2008-08-12 | 2013-08-20 | International Business Machines Corporation | Metal-gate high-k reference structure |
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