JPH0740607B2 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistorInfo
- Publication number
- JPH0740607B2 JPH0740607B2 JP59207862A JP20786284A JPH0740607B2 JP H0740607 B2 JPH0740607 B2 JP H0740607B2 JP 59207862 A JP59207862 A JP 59207862A JP 20786284 A JP20786284 A JP 20786284A JP H0740607 B2 JPH0740607 B2 JP H0740607B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- polycrystalline silicon
- silicon thin
- thickness
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 39
- 239000010408 film Substances 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000000969 carrier Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 108091006146 Channels Proteins 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000003949 trap density measurement Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、チャネルが形成される活性層を多結晶シリコ
ン薄膜により構成した薄膜トランジスタを製造する方法
に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a thin film transistor in which an active layer in which a channel is formed is composed of a polycrystalline silicon thin film.
従来の技術 従来、この種の薄膜トランジスタとして、例えば第３図
に示すようなMOS型の薄膜トランジスタ（以下MOS TFTと
称する）が知られている。このMOS TFTにおいては、石
英基板１上に多結晶シリコン薄膜２が形成されている。
またこの多結晶シリコン薄膜２の両端には、所定のｎ型
不純物が高濃度にドープされた低抵抗のn+層から成るソ
ース領域３、ドレイン領域４がそれぞれ形成されてい
る。なおMOS TFTの動作時においては、多結晶シリコン
薄膜２中のソース領域３とドレイン領域４との間の部分
にチャネルが形成されるようになっているので、この多
結晶シリコン薄膜２の中間部分が活性層2aを構成してい
る。2. Description of the Related Art Conventionally, as this type of thin film transistor, for example, a MOS type thin film transistor (hereinafter referred to as a MOS TFT) as shown in FIG. 3 has been known. In this MOS TFT, a polycrystalline silicon thin film 2 is formed on a quartz substrate 1.
Further, on both ends of this polycrystalline silicon thin film 2, a source region 3 and a drain region 4 are formed, each of which is a low resistance n + layer doped with a predetermined n-type impurity at a high concentration. During operation of the MOS TFT, a channel is formed in the portion between the source region 3 and the drain region 4 in the polycrystalline silicon thin film 2, so that the middle portion of this polycrystalline silicon thin film 2 is formed. Constitute the active layer 2a.
また上記多結晶シリコン薄膜２上には、SiO2から成るゲ
ート絶縁膜５が形成され、このゲート絶縁膜５上には不
純物がドープされた多結晶シリコン（DOPOS）から成る
ゲート電極６が形成されている。さらに上記多結晶シリ
コン薄膜２及びゲート電極６上には、SiO2から成る絶縁
膜７が形成されている。この絶縁膜７には開口7a,7bが
形成されていて、これらの開口7a,7bを通じてソース領
域３及びドレイン領域４のためのAlから成る取り出し電
極8,9がそれぞれ形成されている。なおゲート電極６に
も取り出し電極（図示せず）が形成されている。A gate insulating film 5 made of SiO 2 is formed on the polycrystalline silicon thin film 2, and a gate electrode 6 made of polycrystalline silicon (DOPOS) doped with impurities is formed on the gate insulating film 5. ing. Further, an insulating film 7 made of SiO 2 is formed on the polycrystalline silicon thin film 2 and the gate electrode 6. Openings 7a and 7b are formed in the insulating film 7, and lead electrodes 8 and 9 made of Al for the source region 3 and the drain region 4 are formed through the openings 7a and 7b, respectively. An extraction electrode (not shown) is also formed on the gate electrode 6.
なお上述の従来のMOS TFTにおいては、チャネルが形成
される活性層2aを構成している多結晶シリコン薄膜２の
膜厚は通常例えば1500Å程度である。In the conventional MOS TFT described above, the thickness of the polycrystalline silicon thin film 2 forming the active layer 2a in which the channel is formed is usually about 1500Å, for example.
上述の従来のMOS TFTは、次のような欠点を有してい
る。即ち、第１に、活性層2a中の不純物トラップ密度が
大きいため、MOS TFTのしきい値電圧Vthが大きい。第２
に、多結晶シリコン薄膜２の膜厚が例えば1500Å程度の
場合、キャリヤ（本実施例では電子）の実効移動度μ
effは0.01cm2/Vsec以下であって小さい。第３に、ソー
ス領域３及びドレイン領域４と活性層2aとの間に接合に
おけるリーク電流が大きい。第４に、活性層2aの抵抗が
低いばかりでなく膜厚が大きいので、MOS TFTのオフ時
において、外部光によるソース領域３、ドレイン領域４
間のリーク電流が大きい。The conventional MOS TFT described above has the following drawbacks. That is, first, since the impurity trap density in the active layer 2a is high, the threshold voltage V th of the MOS TFT is high. Second
In addition, when the thickness of the polycrystalline silicon thin film 2 is, for example, about 1500 Å, the effective mobility μ of the carrier (electrons in this embodiment) is
eff is less than 0.01 cm 2 / Vsec, which is small. Thirdly, the leak current at the junction between the source region 3 and the drain region 4 and the active layer 2a is large. Fourth, since the active layer 2a has a low resistance and a large film thickness, the source region 3 and the drain region 4 are exposed to external light when the MOS TFT is off.
The leak current between them is large.
本発明者は、上述の欠点を是正したTFTとして、特願昭5
8−251813号において、活性層を100〜750Åの膜厚の多
結晶シリコン薄膜で構成したMOS TFTを提案した。このM
OS TFTによれば、特にμeffを従来に比べて極めて大き
くすることができた。しかしこの特願昭58−251813号に
おいては、活性層の膜厚が100Å以下の場合の特性につ
いては明らかではなかった。The present inventor has proposed a Japanese Patent Application No.
In 8-251813, we proposed a MOS TFT whose active layer is composed of a polycrystalline silicon thin film with a thickness of 100 to 750Å. This M
According to OS TFT, in particular, μ eff could be made extremely large as compared with the conventional one. However, in this Japanese Patent Application No. 58-251813, the characteristics when the thickness of the active layer is 100 Å or less were not clear.
発明が解決しようとする問題点 本発明は、上述の問題にかんがみ、従来のMOS TFTが有
する上述のような欠点を特に膜厚が100Å以下の多結晶
シリコン薄膜から成る活性層を用いて是正した薄膜トラ
ンジスタを製造する方法を提供することを目的とする。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In view of the above problems, the present invention has rectified the above-mentioned drawbacks of a conventional MOS TFT by using an active layer made of a polycrystalline silicon thin film having a film thickness of 100 Å or less. It is an object to provide a method for manufacturing a thin film transistor.
問題点を解決するための手段 本発明は、チャネルが形成される活性層が絶縁基板上に
形成された多結晶シリコン薄膜により構成された薄膜ト
ランジスタを製造する方法において、上記絶縁基板上に
20〜100Åの膜厚で上記多結晶シリコン薄膜を形成して
この多結晶シリコン薄膜により上記活性層を構成すると
共に、上記多結晶シリコン薄膜上にプラズマ窒化シリコ
ン膜のカバーを設けた状態において熱処理してキャリヤ
の実効移動度を向上させるようにしたものである。Means for Solving the Problems The present invention provides a method for manufacturing a thin film transistor in which an active layer in which a channel is formed is composed of a polycrystalline silicon thin film formed on an insulating substrate, wherein
The polycrystalline silicon thin film having a film thickness of 20 to 100 Å is formed, and the polycrystalline silicon thin film constitutes the active layer, and heat treatment is performed in a state in which the plasma silicon nitride film cover is provided on the polycrystalline silicon thin film. It is intended to improve the effective mobility of the carrier.
実施例 以下本発明に係る薄膜トランジスタの製造方法をMOS TF
Tの製造方法に適用した一実施例につき第１図及び第２
図を参照しながら説明する。EXAMPLES Hereinafter, a method for manufacturing a thin film transistor according to the present invention will be described with MOS TF.
1 and 2 for one embodiment applied to the manufacturing method of T
Description will be given with reference to the drawings.
第１図に示す本実施例によるMOS TFTは、活性層を構成
する多結晶シリコン薄膜２の膜厚が60Åと極めて小さい
点と、多結晶シリコン薄膜２上にプラズマ窒化シリコン
膜（図示せず）のカバーが設けられている点とで、第３
図に示す従来のMOS TFTと相違している。なお多結晶シ
リコン薄膜２の膜厚を60Åに選定したのは、次のような
理由による。In the MOS TFT according to this embodiment shown in FIG. 1, the thickness of the polycrystalline silicon thin film 2 constituting the active layer is as small as 60Å, and a plasma silicon nitride film (not shown) is formed on the polycrystalline silicon thin film 2. With the point that the cover of is provided,
This is different from the conventional MOS TFT shown in the figure. The reason why the thickness of the polycrystalline silicon thin film 2 is selected to be 60Å is as follows.
即ち、本発明者等は、多結晶シリコン薄膜２の膜厚を特
に従来のMOS TFTにおいて用いられているよりも小さい
膜厚範囲（20〜900Å）内で種々に変えてμeffの膜厚依
存性を詳細に測定した結果、第２図に示すように、膜厚
の減少と共にμeffが急激に上昇し、ある膜厚において
極大値をとった後、さらに膜厚が減少するとμeffが再
び減少するという極めて特徴的な変化を示すことを見出
した。なお第２図において、曲線ＡはCVD法により多結
晶シリコン薄膜を被着形成した後、この多結晶シリコン
薄膜の表面を熱酸化して、所定膜厚の多結晶シリコン薄
膜２を形成した本発明の参考例の場合のデータを示し、
曲線Ｂは曲線Ａに示す参考例の場合の試料にプラズマ窒
化シリコン膜のカバーを設けた状態において400℃で４
時間アニールした本発明の実施例の場合のデータをそれ
ぞれ示す。なお実効移動度μeffは、曲線Ａの場合、膜
厚約140Åにおいて極大値7.5cm2/Vsecをとり、また曲線
Ｂの場合、膜厚約180Åにおいて極大値15.0cm2/Vsecを
とる。That is, the inventors of the present invention have variously changed the film thickness of the polycrystalline silicon thin film 2 within a film thickness range (20 to 900Å) smaller than that used in the conventional MOS TFT, and the film thickness dependence of μ eff . As a result of the detailed measurement of the property, as shown in FIG. 2, μ eff rapidly rises with the decrease of the film thickness, reaches a maximum value at a certain film thickness, and when the film thickness is further reduced, μ eff is again measured. It has been found that it shows a very characteristic change of decreasing. In FIG. 2, the curve A indicates that a polycrystalline silicon thin film 2 having a predetermined thickness is formed by depositing a polycrystalline silicon thin film by the CVD method and then thermally oxidizing the surface of the polycrystalline silicon thin film. The data for the reference example of
Curve B is 4 ° C. at 400 ° C. when the sample of the reference example shown in curve A is provided with a plasma silicon nitride film cover.
The data in the case of the Example of this invention which annealed for a time is shown, respectively. Incidentally effective mobility mu eff is the curve A, thickness takes the maximum value 7.5 cm 2 / Vsec at about 140 Å, and if the curve B, takes a maximum value 15.0 cm 2 / Vsec in the film thickness of about 180 Å.
第２図に示す本発明の参考例及び実施例においては、多
結晶シリコン薄膜２の膜厚を上述のように60Åに選定し
ているため、第２図から明らかなように、μeffを曲線
Ａの場合には約6.5cm2/Vsec、また曲線Ｂの場合には約1
1.0cm2/Vsecと極めて大きい値にすることができる。In Reference Examples and Examples of the present invention shown in FIG. 2, since the selected thickness of the polycrystalline silicon thin film 2 to 60Å as described above, it is clear from Figure 2, the mu eff curve Approximately 6.5 cm 2 / Vsec for A, and approximately 1 for curve B
It can be set to an extremely large value of 1.0 cm 2 / Vsec.
さらに第２図に示す曲線Ｂのデータの測定に用いたと同
様な多結晶シリコン薄膜２により活性層を構成したMOS
TFTにつき、トランジスタのオフ時におけるソース領域
３、ドレイン領域４間のリーク電流Ioff及びしきい値電
圧Vthを測定した結果、表Ｉに示すような結果が得られ
た（μeffの値も併せて示す）。なおこのMOS TFTにおい
ては、W/L＝100μm/10μｍ（W:チャネル幅、L:チャネル
長）、ゲート絶縁膜５の膜厚＝1000Åである。Further, a MOS having an active layer composed of the same polycrystalline silicon thin film 2 as that used for measuring the data of the curve B shown in FIG.
For the TFT, the leakage current I off and the threshold voltage V th between the source region 3 and the drain region 4 when the transistor was off were measured, and the results shown in Table I were obtained (the value of μ eff is also Also shown). In this MOS TFT, W / L = 100 μm / 10 μm (W: channel width, L: channel length), and the film thickness of the gate insulating film 5 = 1000Å.
この表Ｉから明らかなように、上述の実施例のように多
結晶シリコン薄膜２の膜厚を60Åに選定した場合、μ
effが11.0cm2/Vsecと極めて大きいのみならず、Ioff及
びVthをそれぞれ４×10-12Ａ、4.3Vと従来に比べて極め
て小さくすることができる。なお上述のように実効移動
度μeffが大きくなると共にしきい値電圧Vthが低くなる
のは、活性層2aの膜厚が、MOS TFTのゲート電極６に通
常の大きさのゲート電圧を印加した場合にこの活性層2a
に誘起されるチャネルの厚さよりも小さくなっているた
めであると考えられる。またIoffが従来に比べて小さく
なったのは、多結晶シリコン膜厚２の膜厚が小さくなっ
た分だけ活性層2aの抵抗を見かけ上大きくすることがで
きると共に、この活性層2aの体積を小さくすることがで
きるので、外部光によるソース領域３、ドレイン領域４
間のリーク電流を小さくすることができるためであると
考えられる。のみならず、上述の実施例によれば、多結
晶シリコン薄膜２の膜厚が従来に比べて極めて小さいの
で、ソース領域３及びドレイン領域４と活性層2aとの間
の接合の面積が従来に比べて小さくなり、この分だけ接
合リーク電流を小さくすることができる。 As is clear from Table I, when the thickness of the polycrystalline silicon thin film 2 is selected to be 60Å as in the above-mentioned embodiment, μ
Not only is eff extremely large at 11.0 cm 2 / Vsec, but I off and V th can also be made extremely small at 4 × 10 −12 A and 4.3 V, respectively, compared to the conventional case. As described above, the effective mobility μ eff is increased and the threshold voltage V th is decreased because the thickness of the active layer 2a is such that a gate voltage of a normal magnitude is applied to the gate electrode 6 of the MOS TFT. If this active layer 2a
It is thought that this is because the thickness is smaller than the thickness of the channel induced by. Further, I off is smaller than that of the conventional one because the resistance of the active layer 2a can be increased apparently by the amount of the film thickness of the polycrystalline silicon film 2 being reduced, and the volume of the active layer 2a is increased. Can be made smaller, so that the source region 3 and the drain region 4 are exposed to external light.
It is considered that this is because the leak current between them can be reduced. In addition, according to the above-mentioned embodiment, since the thickness of the polycrystalline silicon thin film 2 is extremely smaller than that of the conventional one, the area of the junction between the source region 3 and the drain region 4 and the active layer 2a is not the conventional one. Compared with this, the junction leak current can be reduced by this amount.
なお上述の実施例においては、多結晶シリコン薄膜2aの
薄膜を60Åに選定したが、これに限定されるものでは勿
論なく、20〜100Åの範囲の薄膜であればよい。Although the thin film of the polycrystalline silicon thin film 2a is selected to be 60Å in the above-mentioned embodiment, the thin film is not limited to this and may be a thin film in the range of 20 to 100Å.
発明の効果 本発明に係る薄膜トランジスタによれば、活性層を構成
する多結晶シリコン薄膜の膜厚を20〜100Åに構成して
いるので、しきい値電圧Vthを極めて低くすることがで
きると共に、実効移動度μeffを極めて大きくすること
ができ、またソース領域及びドレイン領域の接合のリー
ク電流並びにソース領域、ドレイン領域間のリーク電流
Ioffを極めて小さくすることができる。Effects of the Invention According to the thin film transistor of the present invention, since the thickness of the polycrystalline silicon thin film forming the active layer is configured to be 20 to 100Å, the threshold voltage V th can be made extremely low, and The effective mobility μ eff can be made extremely large, and the leak current at the junction between the source region and the drain region and the leak current between the source region and the drain region can be increased.
I off can be made extremely small.
また、活性層を構成する多結晶シリコン薄膜の膜厚を20
〜100Åに構成するだけでなく、多結晶シリコン薄膜上
にプラズマ窒化シリコン膜のカバーを設けた状態におい
て熱処理してキャリアの実効移動度を向上させるように
したので、しきい値電圧Vthをさらに小さくすることが
でき、また、実効移動度μeffをさらに大きくすること
ができ、しかも、高温BT試験などにおいてトラップ密度
が変化して特性の変化を生じることがなく、さらに、外
部からの不純物により多結晶シリコン薄膜が汚染されて
特性の劣化を生じることもない。In addition, the thickness of the polycrystalline silicon thin film that constitutes the active layer is set to 20
The threshold voltage V th can be further improved by not only configuring it up to 100 Å, but also performing heat treatment with the plasma silicon nitride film cover provided on the polycrystalline silicon thin film to improve the effective mobility of carriers. In addition, the effective mobility μ eff can be further increased, the trap density does not change in a high temperature BT test, and the characteristics do not change. The polycrystalline silicon thin film is not contaminated and the characteristics are not deteriorated.
第１図は本発明に係る薄膜トランジスタをMOS TFTに適
用した一実施例を示す断面図、第２図は第１図に示すMO
S TFTにおいて活性層を構成する多結晶シリコン薄膜の
膜厚と実効移動度μeffとの関係を示すグラフ、第３図
は活性層を多結晶シリコン薄膜により構成した従来のMO
S TFTの構造を示す断面図である。 なお図面に用いられた符号において、 １……石英基板 ２……多結晶シリコン薄膜 2a……活性層 ３……ソース領域 ４……ドレイン領域 ５……ゲート絶縁膜 ６……ゲート電極 8,9……取り出し電極 である。FIG. 1 is a sectional view showing an embodiment in which the thin film transistor according to the present invention is applied to a MOS TFT, and FIG. 2 is a MO shown in FIG.
A graph showing the relationship between the effective mobility μ eff and the thickness of the polycrystalline silicon thin film that constitutes the active layer in S TFT, and Fig. 3 shows the conventional MO film in which the active layer is composed of the polycrystalline silicon thin film.
FIG. 3 is a cross-sectional view showing the structure of S TFT. In the reference numerals used in the drawings, 1 ... Quartz substrate 2 ... Polycrystalline silicon thin film 2a ... Active layer 3 ... Source region 4 ... Drain region 5 ... Gate insulating film 6 ... Gate electrode 8,9 ...... It is an extraction electrode.
Claims (1)
に形成された多結晶シリコン薄膜により構成された薄膜
トランジスタを製造する方法において、 上記絶縁基板上に20〜100Åの膜厚で上記多結晶シリコ
ン薄膜を形成してこの多結晶シリコン薄膜により上記活
性層を構成すると共に、 上記多結晶シリコン薄膜上にプラズマ窒化シリコン膜の
カバーを設けた状態において熱処理してキャリヤの実効
移動度を向上させるようにしたことを特徴とする薄膜ト
ランジスタの製造方法。1. A method of manufacturing a thin film transistor in which an active layer in which a channel is formed is composed of a polycrystalline silicon thin film formed on an insulating substrate, wherein the polycrystalline film has a thickness of 20 to 100Å on the insulating substrate. A silicon thin film is formed to form the active layer by the polycrystalline silicon thin film, and heat treatment is performed with the plasma silicon nitride film cover provided on the polycrystalline silicon thin film to improve the effective mobility of carriers. A method of manufacturing a thin film transistor, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207862A JPH0740607B2 (en) | 1984-10-03 | 1984-10-03 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207862A JPH0740607B2 (en) | 1984-10-03 | 1984-10-03 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6185868A JPS6185868A (en) | 1986-05-01 |
| JPH0740607B2 true JPH0740607B2 (en) | 1995-05-01 |
Family
ID=16546769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59207862A Expired - Lifetime JPH0740607B2 (en) | 1984-10-03 | 1984-10-03 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0740607B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100309934B1 (en) * | 1992-06-24 | 2002-06-20 | 구사마 사부로 | Method of manufacturing thin film transistor, solid state device, display device, and thin film transistor |
| US6337232B1 (en) | 1995-06-07 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabrication of a crystalline silicon thin film semiconductor with a thin channel region |
| JPH07335906A (en) * | 1994-06-14 | 1995-12-22 | Semiconductor Energy Lab Co Ltd | Thin film semiconductor device and fabrication thereof |
| JP3955409B2 (en) * | 1999-03-17 | 2007-08-08 | 株式会社ルネサステクノロジ | Semiconductor memory device |
| JP3992976B2 (en) | 2001-12-21 | 2007-10-17 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4030758B2 (en) | 2001-12-28 | 2008-01-09 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182272A (en) * | 1982-04-19 | 1983-10-25 | Seiko Epson Corp | Thin film transistor |
-
1984
- 1984-10-03 JP JP59207862A patent/JPH0740607B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6185868A (en) | 1986-05-01 |
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| EXPY | Cancellation because of completion of term |