JPH0244734A - Manufacture of mis transistor - Google Patents

Abstract

PURPOSE:To improve punchthrough-breakdown strength by forming a third region with a gate electrode as a mask, then forming a first thin mask layer at least on the sidewall of the electrode in a direction for extending a semiconductor region forms a second mask layer to form a first region, and then forming a second region. CONSTITUTION:An SiO2 film 22 is deposited on a whole Si substrate 11, and P<-> ions are implanted to form an n<-> type region 16 in a p<-> type region 21. In this case, since the film 22 exists, the length of the mask for the ion implantation is longer by the thickness of the film 22 than that of only a gate electrode 13 of a mask at the time of forming the region 21 at both sides of the electrode 13. Then, an SiO2 film 23 is again deposited on the whole substrate 11, the films 22, 23 are etched by RIE, sidewalls 14 of the films 22, 23 are formed, and with the electrode 13 and the sidewall 14 as masks P<-> ions are implanted to form an n<+> type region 15. Thus, the width of a third region can be effectively obtained in a direction for extending a semiconductor region to enhance punchthrough-breakdown strength.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides at least a drain region having a first region having a relatively high concentration of impurities of the first conductivity type and a second region having a relatively low concentration of impurities of the first conductivity type. The present invention relates to a method for manufacturing an MIS transistor comprising:

[Summary of the invention]

The present invention provides a method for manufacturing an MIS transistor as described above, in which a third region is formed using the gate electrode as a mask, and then the surface of the semiconductor region is lower than the second mask layer for forming the first region. By forming a thin first mask layer on at least the sidewalls of the gate electrode in the direction in which the gate electrode spreads, and then forming the second region, it is possible to manufacture M■S transistors with high punch-through breakdown voltage and high reliability at a high yield. Ma
It was made so that it could be done with t.

[Conventional technology]

LDD transistors are considered to reduce the hot carrier effect caused by short channel MIS transistors. However, if an attempt is made to make the channel of this LDD transistor even shorter, the depletion layer from the drain region tends to reach the source region, which tends to cause punch-through.

As one of the countermeasures, a pocket LD as shown in Figure 2 is available.
A transistor having a D (PLDD) structure has been proposed (for example, Japanese Patent Laid-Open No. 191070/1983).

In this n-channel PLDDI transistor, p-type Si
SiO□ film 12 film type 2 which is a gate insulating film on base 11
A gate electrode 13 made of polycrystalline Si and a side wall 14 made of 5iOz are formed on this SiO□11U12. In addition, in the Si substrate ll, there is a n゛ region 1.
A source region 17 and a drain region 18 are formed of an n-region 16 and an n-region 16.

The structure described above is the same as that of a normal LDDI transistor, but in the PLDD transistor, an Il region 21 is further formed around the n region 16.

Therefore, in such a PLDD transistor, the spread of depletion N (not shown) from the drain region 18 is suppressed by the p- region 21, and the punch-through breakdown voltage is higher than that of the LDD transistor.

[Problem to be solved by the invention]

By the way, in the above-mentioned PLDD transistor, the total amount of impurities in the portion of the p-region 21 directly below the data electrode 13 affects the dark value voltage V7H; 16 is determined only by the difference in their respective diffusion depths.

Since the depth of these diffusions is influenced by subtle variations in the process, controllability of the dark voltage VT)I is low, and as a result, the manufacturing yield is not high.

Further, when the width of the p'' region 21 directly under the gate electrode 13 becomes narrower due to the above-mentioned variation in the diffusion depth, the punch-through breakdown voltage decreases, reducing the effectiveness of the PLDD structure.

Conversely, if the total amount of impurities in the p-81 region 21 is increased so that the punch-through withstand voltage does not decrease even if the width of the p-region 21 becomes narrow, the controllability of the dark voltage VTH becomes even lower, and The total amount of impurities No. 16 must also be increased, which increases the hot carrier effect and reduces reliability.

[Means to solve the problem]

The method for manufacturing a MISI-transistor according to the present invention includes the second
forming a third region 21 containing impurities of a second conductivity type in the semiconductor region 11 using the gate electrode 13 on the semiconductor region 11 of the conductivity type as a mask; A first mask layer 22 is formed, and a second region 16 is formed in the third region 21 and on the surface of the semiconductor region 11 using the first mask layer 22 and the gate electrode piA13 as a mask. forming a second mask layer 14 thicker in the direction in which the surface spreads than the first mask layer 22 on at least the side wall portion of the gate electrode 13; 13 as a mask to form the first region 15 in the semiconductor region 11, respectively.

[Effect]

In the method for manufacturing a MISI transistor according to the present invention, after forming the third region 21 using the gate electrode 13 as a mask, the second mask layer 1 for forming the first region 15 is formed.
4, which is thinner in the direction in which the surface of the semiconductor region 11 spreads.
Since the second region 16 is formed after the mask layer 22 is formed on at least the side wall portion of the gate electrode 13, the width of the third region 21 is ensured in the direction in which the surface extends.

In addition, since this width is ensured, the third area 21
The total amount of impurities in the second region 16.21 is not easily affected by the difference in diffusion depth between the second and third regions 16.21.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG.

In this embodiment, as shown in FIG. 1A, a p region 21 is first formed by implanting B ions using the gate electrode 13 as a mask.

Next, as shown in FIG. 1B, a SiO□ film 22 having a thickness of about 500 to 1000 layers is deposited over the entire surface of the Si substrate 11 by CVD. Note that this Sin film 22 may be formed by thermal oxidation.

Thereafter, in this state, P- ions are implanted to form n- region 16 in p-region 21. At this time, since the 5iOz film 22 is present, the length of the mask for ion implantation is longer than that of the 5i02 film 22 compared to the length of only the gate electrode 13, which is the mask when the p- region 21 is formed. The gate electrode 13 is longer on both sides of the gate electrode 13 by its thickness.

Therefore, the width of the p-FiJt region 21 on the side below the gate electrode 13 is ensured to correspond to the thickness of the 1.5 iOz film 22.

Next, as shown in FIG. 1C, a SiO□ film 23 having a thickness of about 3000 layers is deposited again on the entire surface of the Si substrate 11 by CVD. Then, RIE the SiO□ film 23,22.
As a result, the side wall 14 made of the 5iOz film 22, 23 is formed as shown by the dashed line.

Next, as shown in FIG. 1D, the gate electrode 13 and the side wall 14 are
Using this as a mask, P- ions are implanted to form an n'' region 15.

〔Effect of the invention〕

In the MISI transistor manufacturing method according to the present invention, the width of the third region is reliably secured in the direction in which the surface of the semiconductor region spreads, so that the punch-through breakdown voltage is high.

In addition, since the above width is reliably secured, the total amount of impurities in the third region can be reduced without significantly reducing the punch-through breakdown voltage, and furthermore, this total amount of impurities can be reduced in the second and third regions. Since it is not easily affected by the difference in diffusion depth, the controllability of the dark value voltage VTH is high and the manufacturing yield is high.

Furthermore, since the total amount of impurities in the third region can be reduced, the total amount of impurities in the second region can also be reduced, resulting in a small hot carrier effect and high reliability.

It is.

Claims (1)

[Claims] A method for manufacturing an MIS transistor, wherein at least the drain region includes a first region in which the concentration of impurities of the first conductivity type is relatively high and a second region in which the concentration of impurities of the first conductivity type is relatively low. forming a third region containing impurities of the second conductivity type in the semiconductor region using the gate electrode on the semiconductor region of the second conductivity type as a mask; and applying a first mask to at least a sidewall portion of the gate electrode. forming the second region in the third region and on the surface of the semiconductor region using the first mask layer and the gate electrode as a mask; A second mask layer is formed on the side wall portion to be thicker than the first mask layer in the direction in which the surface spreads, and the second mask layer and the gate electrode are used as masks to form the first mask layer in the semiconductor region. A method for manufacturing an MIS transistor, comprising the steps of forming a region.