JPH0346980B2 - - Google Patents
Info
- Publication number
- JPH0346980B2 JPH0346980B2 JP60232252A JP23225285A JPH0346980B2 JP H0346980 B2 JPH0346980 B2 JP H0346980B2 JP 60232252 A JP60232252 A JP 60232252A JP 23225285 A JP23225285 A JP 23225285A JP H0346980 B2 JPH0346980 B2 JP H0346980B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- gate
- well region
- insulating film
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 15
- 230000000295 complement effect Effects 0.000 claims description 12
- 238000002844 melting Methods 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 230000008018 melting Effects 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000012535 impurity Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000010354 integration Effects 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、相補型半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to complementary semiconductor devices.
従来、相補型半導体装置は、例えば第２図に示
すような構造を有している。図中１は、Ｎ型の半
導体基板である。半導体基板１の所定領域には、
Ｐ−Well領域２が形成されている。Ｐ−Well領
域２とこれに隣接する半導体基板１の領域間に
は、素子分離絶縁膜３が介在されている。半導体
基板１の主面及びＰ−Well領域２の主面には、
薄肉のゲート絶縁膜４，５が夫々形成されてい
る。ゲート絶縁膜４，５及び素子分離絶縁膜３上
にはLPCVD（LoW Pressure Chemical Vapor
Deposition）法等にて多結晶シリコンからなるゲ
ート電極６が形成されている。半導体基板１の主
面側のゲート電極６ａには、Ｂ或はBF2等のＰ型
不純物が注入され、P+ゲートを構成している。
Ｐ−Well領域２の上方のゲート電極６ｂには、
As或はＰ等のＮ型不純物が注入され、N+ゲート
を構成している。ゲート電極６上にはMo、Ti等
からなる高融点金属膜７が形成されている。
Conventionally, a complementary semiconductor device has a structure as shown in FIG. 2, for example. In the figure, 1 is an N-type semiconductor substrate. In a predetermined area of the semiconductor substrate 1,
A P-well region 2 is formed. An element isolation insulating film 3 is interposed between the P-well region 2 and an adjacent region of the semiconductor substrate 1 . On the main surface of the semiconductor substrate 1 and the main surface of the P-well region 2,
Thin gate insulating films 4 and 5 are formed, respectively. LPCVD (LoW Pressure Chemical Vapor
A gate electrode 6 made of polycrystalline silicon is formed using a deposition method or the like. A P type impurity such as B or BF 2 is implanted into the gate electrode 6a on the main surface side of the semiconductor substrate 1 to form a P + gate.
In the gate electrode 6b above the P-well region 2,
N-type impurities such as As or P are implanted to form an N + gate. A high melting point metal film 7 made of Mo, Ti, etc. is formed on the gate electrode 6.
このように構成された相補型半導体装置１０で
は、高融点金属膜７を形成する際の熱処理によつ
て、ゲート電極６中のＮ型不純物及びＰ型不純物
が高融点金属膜７を介して相互に拡散する。この
ためN+ゲート及びP+ゲート中の不純物濃度が変
動し、しきい値電圧の制御性が悪くなると共に、
所定のトランジスタ特性が得られない。また、ゲ
ート電極６上の高融点金属膜７の存在によりゲー
ト耐圧の劣化を招く問題があつた。
In the complementary semiconductor device 10 configured as described above, the N-type impurity and the P-type impurity in the gate electrode 6 are mutually bonded to each other via the high-melting point metal film 7 through the heat treatment when forming the high-melting point metal film 7. spread to. As a result, the impurity concentration in the N + gate and P + gate fluctuates, making it difficult to control the threshold voltage.
Predetermined transistor characteristics cannot be obtained. Further, the presence of the high melting point metal film 7 on the gate electrode 6 caused a problem of deterioration of gate breakdown voltage.
本発明は、しきい値電圧の制御性及びトランジ
スタ特性の向上を図ると共に、ゲート抵抗の低減
を図つて高性能でかつ、高集積度の相補型半導体
装置を提供することをその目的とするものであ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a high-performance, highly integrated complementary semiconductor device that improves controllability of threshold voltage and transistor characteristics, and reduces gate resistance. It is.
本発明は、ゲート電極上にトンネル電流が生じ
る程度の厚さのチツ化シリコン膜を介して高融点
金属膜を設けたことにより、しきい値電圧の制御
性及びトランジスタ特性の向上を図ると共に、ゲ
ート抵抗の低減を図つて、高性能かつ高集積度を
有する相補型半導体装置である。
The present invention improves controllability of threshold voltage and transistor characteristics by providing a high melting point metal film on the gate electrode via a silicon oxide film having a thickness sufficient to generate a tunnel current. This is a complementary semiconductor device that aims to reduce gate resistance and has high performance and high integration.
以下、本発明の実施例について図面を参照して
説明する。第１図は、本発明の一実施例の断面図
である。図中２０は、Ｎ型の半導体基板である。
半導体基板２０の所定領域には、Ｐ−Well領域
２１が形成されている。Ｐ−Well領域２１とこ
れに隣接する半導体基板２０の領域間には、素子
分離絶縁膜２２が介在されている。半導体基板２
０の主面及びＰ−Well領域２１の主面上には、
薄肉のゲート酸化膜２３，２４が形成されてい
る。ゲート酸化膜２３，２４及び素子分離絶縁膜
２２上には、LPCVD法等により厚さ約4000Åの
多結晶シリコンからなるゲート電極２５が形成さ
れている。半導体基板２０の主面側のゲート電極
２５ａには、、Ｂ或いはBF2等のＰ型不純物が注
入され、P+ゲートを構成している。Ｐ−Well領
域２１の上方のゲート電極２５ｂいは、As或い
はＰ等のＮ型不純物が注入され、N+ゲートを構
成している。ゲート電極２５上には、厚さ10〜50
Åのチツ化シリコン膜２６が形成されている。こ
のチツ化シリコン膜２６の膜厚は、トンネル電流
が生じる程度の膜厚である。チツ化シリコン膜２
６には、Mo、Ti等からなる高融点金属膜２７が
形成されている。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention. In the figure, 20 is an N-type semiconductor substrate.
A P-well region 21 is formed in a predetermined region of the semiconductor substrate 20 . An element isolation insulating film 22 is interposed between the P-well region 21 and an adjacent region of the semiconductor substrate 20 . Semiconductor substrate 2
On the main surface of 0 and the main surface of the P-Well region 21,
Thin gate oxide films 23 and 24 are formed. A gate electrode 25 made of polycrystalline silicon and having a thickness of about 4000 Å is formed on the gate oxide films 23 and 24 and the element isolation insulating film 22 by LPCVD or the like. A P-type impurity such as B or BF 2 is implanted into the gate electrode 25a on the main surface side of the semiconductor substrate 20 to form a P + gate. The gate electrode 25b above the P-well region 21 is implanted with an N-type impurity such as As or P to form an N + gate. The gate electrode 25 has a thickness of 10 to 50 mm.
A silicon nitride film 26 of .ANG. The thickness of this silicon oxide film 26 is such that a tunnel current is generated. Silicon dioxide film 2
6, a high melting point metal film 27 made of Mo, Ti, etc. is formed.
このように構成された相補型半導体装置３０に
よれば、ゲート電極２５ａ，２５ｂ上にトンネル
電流が生じる程度の厚さのチツ化シリコン膜２６
が形成されているので、ゲート抵抗を低減させる
ことができる。また、チツ化シリコン膜２６を形
成した後に高融点金属膜２７を形成することにな
る。つまり、チツ化シリコン膜２６によつてゲー
ト電極２５ｂから高融点金属膜２７への不純物が
拡散するのを完全に阻止できる。これにより、高
融点金属膜２７とゲート電極２５ａ，２５ｂ間の
不純物拡散を回避して、例えば、第２図に示す従
来の相補型半導体装置の場合に、0.05〜0.5Vであ
つたしきい値電圧のシフトを、実施例の相補型半
導体装置では0Vのしきい値電圧シフトまで改善
できることが確酸された。このようにしきい値電
圧の制御性を向上させて、トランジスタ特性、素
子の性能及び集積度を著しく向上させることがで
きる。 According to the complementary semiconductor device 30 configured in this way, the silicon nitride film 26 is thick enough to generate a tunnel current on the gate electrodes 25a and 25b.
is formed, gate resistance can be reduced. Further, after forming the silicon dioxide film 26, the high melting point metal film 27 is formed. In other words, the silicon nitride film 26 can completely prevent impurities from diffusing from the gate electrode 25b to the high melting point metal film 27. This avoids impurity diffusion between the high melting point metal film 27 and the gate electrodes 25a and 25b, and reduces the threshold voltage, which was 0.05 to 0.5V in the conventional complementary semiconductor device shown in FIG. 2, for example. It was confirmed that the voltage shift can be improved to a threshold voltage shift of 0V in the complementary semiconductor device of the example. By improving the controllability of the threshold voltage in this way, transistor characteristics, device performance, and degree of integration can be significantly improved.
以上説明した如く、本発明に係る相補型半導体
装置によれば、しきい値電圧の制御性及びトラン
ジスタ特性の向上を図ると共に、ゲート抵抗の低
減を図つて高性能及び高集積度を得ることができ
るものである。
As explained above, according to the complementary semiconductor device according to the present invention, it is possible to improve controllability of threshold voltage and transistor characteristics, reduce gate resistance, and obtain high performance and high degree of integration. It is possible.
第１図は、本発明の一実施例の断面図、第２図
は、従来の相補型半導体装置の断面図である。
２０……半導体基板、、２１……Ｐ−Well領
域、２２……素子分離絶縁膜、２３，２４……ゲ
ート酸化膜、２５，２５ａ，２５ｂ……ゲート電
極、２６……チツ化シリコン膜、２７……高融点
金属膜、３０……相補型半導体装置。
FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional complementary semiconductor device. 20... Semiconductor substrate, 21... P-Well region, 22... Element isolation insulating film, 23, 24... Gate oxide film, 25, 25a, 25b... Gate electrode, 26... Silicon titanide film, 27... High melting point metal film, 30 ... Complementary semiconductor device.
Claims (1)
た反対導電型のウエル領域と、該ウエル領域とこ
れに隣接する前記半導体基板の領域にまたがるよ
うに設けられた素子分離絶縁膜と、前記半導体基
板の主面及び前記ウエル領域の主面を覆うように
形成された絶縁膜と、該絶縁膜及び前記素子分離
絶縁膜を覆うように形成されたゲート電極と、該
ゲート電極上に10〜50Åの範囲内の膜厚で形成さ
れたチツ化シリコン膜と、該チツ化シリコン膜上
に形成された高融点金属膜とを具備することを特
徴とする相補型半導体装置。1. A well region of an opposite conductivity type formed in a predetermined region of a semiconductor substrate of one conductivity type, an element isolation insulating film provided so as to span the well region and an area of the semiconductor substrate adjacent thereto, and the semiconductor substrate. an insulating film formed to cover the main surface of the substrate and the main surface of the well region; a gate electrode formed to cover the insulating film and the element isolation insulating film; 1. A complementary semiconductor device comprising: a silicon nitride film formed with a thickness within the range of 1 and a high melting point metal film formed on the silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60232252A JPS6292360A (en) | 1985-10-17 | 1985-10-17 | Complementary type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60232252A JPS6292360A (en) | 1985-10-17 | 1985-10-17 | Complementary type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6292360A JPS6292360A (en) | 1987-04-27 |
| JPH0346980B2 true JPH0346980B2 (en) | 1991-07-17 |
Family
ID=16936357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60232252A Granted JPS6292360A (en) | 1985-10-17 | 1985-10-17 | Complementary type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6292360A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140009269A (en) * | 2011-01-14 | 2014-01-22 | 도레이 카부시키가이샤 | Molding material, prepreg, fiber-reinforced composite material, fiber-reinforced composite material laminate, and process for production of fiber-reinforced molding base material |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0716455B1 (en) * | 1994-12-09 | 2000-03-01 | AT&T Corp. | Dual gate formation |
| JP3440698B2 (en) * | 1996-06-24 | 2003-08-25 | ソニー株式会社 | Method for manufacturing semiconductor device |
| US5846871A (en) * | 1997-08-26 | 1998-12-08 | Lucent Technologies Inc. | Integrated circuit fabrication |
| EP0936667A1 (en) * | 1998-01-20 | 1999-08-18 | Lucent Technologies Inc. | Lattice matched barrier for dual doped polysilicon gates |
-
1985
- 1985-10-17 JP JP60232252A patent/JPS6292360A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140009269A (en) * | 2011-01-14 | 2014-01-22 | 도레이 카부시키가이샤 | Molding material, prepreg, fiber-reinforced composite material, fiber-reinforced composite material laminate, and process for production of fiber-reinforced molding base material |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6292360A (en) | 1987-04-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |