JPS61274365A - Mos type field effect transistor - Google Patents

Abstract

PURPOSE:To make deterioration caused by hot carriers hard to occur by a method wherein the second gate electrode is provided on a thin-doped drain with a thin insulation film in between or directly and the electrode is connected to a source or the drain or a gate. CONSTITUTION:A gate, a source and a drain of an LDD type MOSFET are covered with a thin SiO2 film 5 and a polycrystalline silicon film 6 is deposited on it. The polycrystalline silicon film 6 is connected to the gate 4 through a contact hole drilled in the insulation film 5. The deterioration of the LDD type MOSFET is caused by the phenomenon that carriers are trapped in the insulation film above the thin-doped drain 31 and the number of carriers in the drain is reduced by the trapped carriers. Therefore, if the second gate 6 is provided on the drain and a suitable potential is applied to it, the penetration of the carriers into the insulation film is suppressed and, even if they penetrate and are trapped, they do not cause the reduction of the number of carriers in the drain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a shallowly doped drain (L1ght17D
The present invention relates to a MOS type field effect transistor having an open drain (abbreviated as LDD).

[Technical background of the invention and its problems]

In the conventional Lm)D type M08FET (field effect transistor), there are insufficient measures against deterioration of the fine LDD type MOSFET due to hot carriers, so miniaturization has been restricted or the power supply voltage has been lowered. LDD
Deterioration of a type MOSFET occurs when carriers are trapped in the insulating film on the shallow (doped) drain, and the carriers reduce the number of carriers in the drain.

However, if the miniaturization is limited, the degree of integration will not increase, the chip area will increase, and the speed will decrease. Furthermore, if the power supply voltage is lowered, the speed will be reduced, and an additional interface circuit with an external circuit will be required.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a MOS type field effect transistor that is less susceptible to deterioration due to hot carriers.

[Summary of the invention]

In order to achieve the above object, the present invention provides a second gate electrode on the shallowly doped drain via a thin insulating film or directly, and connects the electrode to the source, drain or ? -), so as to apply an appropriate potential to the second gate electrode.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. The figure shows the LDD type MOSFET of the same example, in which 1 is a P-type silicon substrate, 2. is a deeply N-type doped drain (or source);2. is a deeply N-doped source (
31 is a shallowly N-doped drain (also +t source), s is a shallowly N-doped source (or drain), 4 is a polycrystalline silicon gate (first gate), 5 is a 5in2 film, and 6 is a second e-) made of polycrystalline silicon.

That is, in the present invention, there is a Teha, I, DD type MOSFET Or
- Thin gate, source and drain (e.g. 5ooX)
810 film 5 and a polycrystalline silicon film 6 thereon by, for example, LPCVD (Lov Pressur@Ch@m1e).
It is deposited by the al vapor deposition method. The polycrystalline silicon film 6 is connected to, for example, a contact hole 4 formed in the insulating film 5, for example.

However, as mentioned above (the deterioration of LDD type MOSFET is
This occurs because carriers are dragged into the insulating film on the lightly doped drain 31, and the carriers reduce the number of carriers in the drain. Therefore, by providing a second gate 6 on this drain and applying an appropriate potential there, injection of carriers into the insulating film is suppressed, and even if carriers are injected and dragged, the number of carriers in the drain decreases. It will not cause 5. this is,
Charges of opposite polarity are induced in the second gate electrode 6, and
This is to cancel out the effect of the charged charges.

〔Effect of the invention〕

As explained above, according to the present invention, an LDD type MOS that causes deterioration due to hot carriers than the conventional one can be used.
A field effect transistor can provide this.

[Brief explanation of drawings]

The figure is a sectional view showing one embodiment of the present invention. 1...P-type silicon substrate, jl,',--...deeply N
Drain or source doped in the mold, 31°! ,
-...a shallowly N-type doped drain or source;
4...Made of polycrystalline silicon. 1st Of-t, 5.
...810□ film, 6... second layer made of polycrystalline silicon
gate of

Claims (5)

[Claims] (1) a MOS type field effect transistor body with a lightly doped drain (so-called LDD), and a first gate provided on the shallowly doped drain of the body apart from a first gate on the channel region of the body; A MOS type field effect transistor characterized by comprising a second gate. (2) The MOS field effect transistor according to claim 1, wherein the second gate is connected to the first gate. (3) The MOS field effect transistor according to claim 1, wherein the second gate is connected to a drain. (4) The MOS field effect transistor according to claim 1, wherein the second gate is connected to a source. (5) The MOS field effect transistor according to claim 1, wherein high resistance polycrystalline silicon is used as the material of the second gate.