JPS60154662A - Mos type semiconductor device - Google Patents
Mos type semiconductor deviceInfo
- Publication number
- JPS60154662A JPS60154662A JP59011366A JP1136684A JPS60154662A JP S60154662 A JPS60154662 A JP S60154662A JP 59011366 A JP59011366 A JP 59011366A JP 1136684 A JP1136684 A JP 1136684A JP S60154662 A JPS60154662 A JP S60154662A
- Authority
- JP
- Japan
- Prior art keywords
- well
- voltage
- transistor
- type
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に、高耐圧のＬＩ ＯＥｌ型ト
ランジスタで構成した０ＭＯ８ＩＣに関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to an 0MO8IC constructed of high-voltage LIOEL type transistors.
従来の高耐圧ＣＭＯ８ＩＣの構造を第１図に示す、説明
の都合上、以下の説明においては、Ｐ型基板を用いたＣ
ＭＯＳについて説明するが、Ｎ型基板を用いたＣＭＯＢ
についても同様である。The structure of a conventional high-voltage CMO8IC is shown in Figure 1.For convenience of explanation, in the following explanation, a CMO8IC using a P-type substrate
I will explain MOS, but CMOB using an N-type substrate
The same applies to
１はＰ型ｓ７基板、２は１内に形成されたＮ型ウェル領
域、３．４は１，２内に形成された、それぞれ、Ｎチャ
ヌル型及びＰチャネル型トランジスタである。５．６は
８ＯＮチヤネル型トランジスタのソース、ドレインとな
るＮ型拡散層、７はゲート電極（例えばポリＳｊ）、８
は高耐圧トランジスタに特有の、低濃度のＮ型層（通常
オフセット層と呼ばれる。以下、Ｎオフセット層と呼ぶ
）である。９ ｔ １（ｌはＰチャネル型トランジスタ
のソース、ドレインとなるＰ型拡散層、１１はゲート電
極、１２は低濃度のＰ型層（以下、Ｐオフセット層と呼
ぶ）である。このように同一基板内にＮチャネルとＰチ
ャネル型の高耐圧トランジスタを集積し、ＣＭＯ１ｌｉ
工Ｃを構成する。1 is a P-type S7 substrate, 2 is an N-type well region formed in 1, and 3.4 is an N-channel type transistor and a P-channel type transistor formed in 1 and 2, respectively. 5.6 is an N-type diffusion layer that becomes the source and drain of the 8ON channel transistor; 7 is a gate electrode (for example, poly Sj); 8
is a low concentration N-type layer (usually called an offset layer, hereinafter referred to as an N-offset layer) which is specific to high voltage transistors. 9 t 1 (l is a P-type diffusion layer that becomes the source and drain of a P-channel transistor, 11 is a gate electrode, and 12 is a low concentration P-type layer (hereinafter referred to as a P-offset layer). In this way, the same By integrating N-channel and P-channel type high voltage transistors in the substrate, CMO1li
Configure engineering C.
従来のこのような構造の高耐圧ＣＭＯ８工Ｃにおいては
、ウェル領域内に形成したトランジスタの耐圧が、基板
内に形成したトランジスタの耐圧よりも低くなり、０Ｍ
Ｏ８ＩＣとしての動作電圧が、ウェル内に形成したトラ
ンジスタの耐圧で、決まってしまうため、動作電圧を大
きくできないという問題点があった。例えば１として４
Ｘ ｌ（１”α−３のＰ基板をつがい、ウェル濃度と
して２×川１６ｃｒｎ−３程度のウェルを形成するとす
ると、６ＯＮ型拡散層と１との耐圧は約５０■（階段接
合、接合の深さ１μｍと仮定）であるのに対し、ｌＯの
Ｐ型拡散層と２との耐圧は約肋ＶとなｊＱｃＭＯ８工Ｃ
としての動作電圧は２０Ｖになってしまう。In the conventional high-voltage CMO8C with such a structure, the breakdown voltage of the transistor formed in the well region is lower than that of the transistor formed in the substrate, and the breakdown voltage of the transistor formed in the well region is lower than that of the transistor formed in the substrate.
Since the operating voltage of the O8 IC is determined by the withstand voltage of the transistor formed in the well, there is a problem that the operating voltage cannot be increased. For example, 1 and 4
Assuming that P substrates of (assuming a depth of 1 μm), whereas the withstand voltage between the P-type diffusion layer of lO and 2 is approximately V.
The operating voltage will be 20V.
本発明はこのような問題点を解決するもので、その目的
とするところは、ウェル内に形成するトランジスタの耐
圧を上げてやり、高耐圧の０ＭＯ８ＩＣを提供すること
にある。The present invention is intended to solve these problems, and its purpose is to increase the breakdown voltage of the transistor formed in the well, thereby providing a high breakdown voltage 0MO8 IC.
本発明の半導体装置は、ウェル内に形成したトランジス
タのドレインとなる拡散層が、濃度の薄い拡散層でおお
われていることを特徴とする。The semiconductor device of the present invention is characterized in that a diffusion layer that serves as a drain of a transistor formed in a well is covered with a lightly doped diffusion layer.
以下、本発明について、実施例に基づき詳細に説明する
。Ｗ、２図に本発明の実施例を示す、）１３が本発明の
主旨により設げた、１０のＰ型拡散層よりも濃度のりす
い、Ｐ型拡散層で、ｌＯを完全におおうように設けられ
て−る。Hereinafter, the present invention will be described in detail based on Examples. Figure 2 shows an embodiment of the present invention. ) 13 is a P-type diffusion layer with a lower concentration than the P-type diffusion layer 10, which was provided according to the spirit of the present invention, and was provided so as to completely cover lO. I'm being beaten.
作用を説明すると、８の基板側に設けられたＮチャネル
トランジスタは従来例と同様である。）２のウェル内に
設けられたＰチャネルトランジスタについては、ｌ（）
のドレインに電圧が印加されると１３の薄−拡散層があ
るためドレイン電界がｌ：３でかんわされ、降伏電圧が
上が９．４のＰチャネルトランジスタの耐圧が上がる。To explain the operation, the N-channel transistor 8 provided on the substrate side is the same as the conventional example. )2, for a P-channel transistor provided in a well of l()
When a voltage is applied to the drain of the transistor, the drain electric field is 1:3 due to the presence of 13 thin diffusion layers, and the withstand voltage of the P-channel transistor whose breakdown voltage is 9.4 is increased.
そのため、Ｎチャネル側とＰチャネル側の耐圧かにぼ同
じとなり、０ＭＯ８ＩＣとしての面］圧も上がシ、動作
電圧も大きくとれる。Therefore, the withstand voltages on the N-channel side and the P-channel side are almost the same, and the surface pressure as an 0MO8 IC is also higher, and the operating voltage can also be increased.
本発明は、ウェル構造をもつＣＭ ＯＥｌＩＣにおいて
、ウェル側に形成したトランジスタのドレインを、うす
い拡散層でおおい、ウェル側のトランジスタの耐圧を上
げることが主旨であるので、ウェルはＰ型ウェルであっ
ても、Ｎ型ウェルであってもよい。The main purpose of the present invention is to cover the drain of a transistor formed on the well side with a thin diffusion layer in a CM OEl IC having a well structure, thereby increasing the withstand voltage of the transistor on the well side. It may also be an N-type well.
また実施例においては、オフセット層を持っている高耐
圧トランジスタについて説明しているがオフセット層が
ない通常のＣＭ （ｌ Ｓ においても本発明が適用で
きることはｂうまでもない。Further, in the embodiments, a high breakdown voltage transistor having an offset layer is described, but it goes without saying that the present invention can also be applied to a normal CM (l S ) having no offset layer.
以上述べたように本発明によれば、ウェル側のトランジ
スタのｍ１＝Ｉ圧が上がり、基板側のトランジスタとウ
ェル側のトランジスタの耐圧がはぼ同じとなり、ＣＭＯ
ＢＩＣとしての動作電圧が上がるという効果を有する。As described above, according to the present invention, the m1=I voltage of the transistor on the well side increases, the breakdown voltages of the transistor on the substrate side and the transistor on the well side become almost the same, and the CMO
This has the effect of increasing the operating voltage as a BIC.
嬉１図は従来の高配圧（、’ＭＯＩＣの断面図。
第２図は本発明の高耐圧ＣＭＯ８工Ｃの実施例の断面図
。
１・・・Ｐ型ｓ７基板
２・・・Ｎ型ウェル領域
８・ＩＩＩＩＮチャネル形トランジスタ４・・・Ｐチャ
ネル形トランジスタ
５．６・・Ｎ型拡散層
７、ｌ］・ φゲート電極
８・・・Ｎオフセット層
９ 、 Ｉ（＋・中Ｐ型拡散層
１２＠−・Ｐオフセット層
Ｉ３・・・低濃度Ｐ型拡散Ｊ藝
以 上
出願人 株式会社＝ｌＶ訪精工舎Figure 1 is a cross-sectional view of a conventional high-voltage MOIC. Figure 2 is a cross-sectional view of an embodiment of the high voltage CMO8 C of the present invention. 1... P-type S7 substrate 2... N-type well Region 8. 12＠-・P offset layer I3...Low concentration P type diffusion
Claims (1)
ェル領域が形成され、該半導体基板と、該ウェル領域に
、それぞれ、いわゆるＭＯ＋３型トランジスタが形成さ
れたいわゆるＣＭＯｆＩ工Ｃにおいて、前記ウェル領域
内に形成されたトランジスタのドレインとなる拡散層が
、該拡散層よ勺も濃度の薄い拡散層でおおわれることを
特徴とするＭＯ８型半導体装置。(1) In a so-called CMOfI technology, a well region of a second conductivity type is formed in a semiconductor substrate of a first conductivity type, and a so-called MO+3 type transistor is formed in the semiconductor substrate and the well region, respectively. . An MO8 type semiconductor device, characterized in that a diffusion layer serving as a drain of a transistor formed in the well region is covered with a diffusion layer having a low concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59011366A JPS60154662A (en) | 1984-01-25 | 1984-01-25 | Mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59011366A JPS60154662A (en) | 1984-01-25 | 1984-01-25 | Mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60154662A true JPS60154662A (en) | 1985-08-14 |
Family
ID=11776021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59011366A Pending JPS60154662A (en) | 1984-01-25 | 1984-01-25 | Mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60154662A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6289352A (en) * | 1985-10-16 | 1987-04-23 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPH01194454A (en) * | 1988-01-29 | 1989-08-04 | Nec Corp | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5815363B2 (en) * | 1979-06-27 | 1983-03-25 | 東洋製罐株式会社 | Manufacturing method for canned food containing liquid nitrogen and nitrogen filling device |
-
1984
- 1984-01-25 JP JP59011366A patent/JPS60154662A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5815363B2 (en) * | 1979-06-27 | 1983-03-25 | 東洋製罐株式会社 | Manufacturing method for canned food containing liquid nitrogen and nitrogen filling device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6289352A (en) * | 1985-10-16 | 1987-04-23 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPH01194454A (en) * | 1988-01-29 | 1989-08-04 | Nec Corp | Semiconductor device |
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