JPH11214525A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mixedly mount a standard (high-speed) MOS transistor and a high breakdown voltage MOS transistor by suppressing the addition of the number of manufacturing processes of a semiconductor device. SOLUTION: In a method for manufacturing a semiconductor device where transistor regions with different breakdown voltages, namely a standard breakdown voltage MOS transistor region A and a high breakdown voltage MOS transistor region B, are mixedly mounted, an oxidation acceleration substance 7 is selectively injected to the high breakdown voltage transistor region B on a well diffusion layer 1 of a semiconductor substrate, gate oxidation is made to the entire surface on the transistor region of the semiconductor substrate, and the gate oxide film of the high breakdown voltage MOS transistor region B is formed thicker than the gate oxide film of the standard breakdown voltage MOS transistor region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device structure of, for example, a MOS transistor or a BiCMOS transistor and a method of manufacturing the same, and forms two or more types of transistor regions having different operating voltages applied to gate electrodes on the same semiconductor substrate. And a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, many semiconductor devices use a plurality of power supplies. For example, a non-volatile memory uses a power supply of about 12 V which is higher at the time of data writing or erasing operation than at the time of normal data reading. For this reason, circuits related to data writing and erasing operations require a high breakdown voltage region that can withstand high voltages. On the other hand, since a voltage of 5 V is used for normal data reading, a circuit related to reading need not be in a high withstand voltage region, but may be in a standard (low) withstand voltage region. By mixing these standard (high-speed) transistor regions and high-withstand-voltage transistor regions on the same semiconductor substrate (same chip), there is an advantage that the degree of freedom in the circuit configuration is increased, and as a result, the degree of integration is improved.
As a result, the chip area is reduced, which leads to cost reduction.

Conventionally, in order to form two or more types of transistor regions having different operating voltages applied to a gate electrode on the same semiconductor substrate, it is necessary to form two gate oxide films optimal for a standard breakdown voltage transistor region and a high breakdown voltage transistor region, respectively. It is formed by a degree of oxidation treatment.

FIGS. 7A to 7C are cross-sectional views showing a manufacturing flow of the conventional semiconductor device. In FIG. 7, 1 is a well diffusion layer of a semiconductor substrate, 2 is a field oxide film for element isolation, A is a standard (high-speed) MOS transistor area,
B is a high voltage MOS transistor region, 6 is a resist film,
8a and b are gate oxide films. The well diffusion layer 1
Is N-type for a P-channel MOS transistor, and N
In the case of a channel MOS transistor, it is a P-type.

Next, a conventional method for manufacturing a semiconductor device will be described. First, as shown in FIG. 7A, a field oxide film 2 for element isolation is formed on a well diffusion layer 1 of a semiconductor substrate, and an oxide film (thermal oxide film) on a transistor active region is removed. A first gate oxide film 8 is formed. In the figure, region A is a region where a standard (high-speed) MOS transistor is to be formed, and region B is a high breakdown voltage MO transistor.
4 shows a region where an S transistor is to be formed.

Next, as shown in FIG.
A resist film 6 is formed on the OS transistor region B, and the gate oxide film 8 on the standard (high-speed) MOS transistor region A is removed using the resist film 6 as a mask.

[0007] Then, as shown in FIG. 7 C, after removing the resist film 6, a second gate oxidation is performed to form a gate oxide film 8 a on the standard (high-speed) MOS transistor region A. At this time, the gate oxide film 8b in the high breakdown voltage MOS transistor region B has a thickness obtained by further increasing the oxide film by the second oxidation of the gate oxide film 8 already formed by the first oxidation.

As described above, in the conventional manufacturing process of a MOS type semiconductor device, a standard (high-speed) MOS transistor region A and a high-breakdown-voltage MOS transistor region B are separately formed by two gate oxidation steps.

[0009]

The conventional method of manufacturing a semiconductor device is configured as described above. Since the gate oxidation step has to be performed twice, not only the number of steps increases but also the second time. Since the thickness of the first gate oxide film formed in the acid cleaning step immediately before the oxidation is reduced, it is difficult to control the thickness of the gate oxide film.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a standard (high-speed) MOS transistor and a high-voltage MOS transistor are mounted on one chip while minimizing the number of process steps. The purpose is to let them.

[0011]

According to the first aspect of the present invention,
In a method of manufacturing a semiconductor device in which two or more transistor regions having different breakdown voltages are mixed, a step of selectively injecting an oxidation promoting substance into a high breakdown transistor region on a semiconductor substrate; Forming a gate oxide film in the high-breakdown-voltage transistor region so as to be thicker than the gate oxide film in the standard-breakdown-voltage transistor region.

According to a second aspect of the present invention, in a method of manufacturing a semiconductor device in which two or more transistor regions having different withstand voltages are mixed, a field oxide film for element isolation on a semiconductor substrate and a gate on a transistor region are provided. An oxide film, a step of forming a gate electrode in a region where a gate electrode is to be formed, a step of implanting low-concentration impurity ions into a transistor region using the gate electrode as a mask, and forming a sidewall film on a side wall of the gate electrode After that, a resist film is formed so as to cover the high breakdown voltage transistor region,
A step of implanting high-concentration impurity ions into the standard-breakdown-voltage transistor region; and a step of implanting high-concentration impurities into at least the source-drain diffusion layer of the high-breakdown-voltage transistor region and forming a wiring layer thereon. Production method.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect, wherein a high-concentration impurity is implanted into the source / drain diffusion layer of the high breakdown voltage transistor region in a self-aligned manner.

According to a fourth aspect of the present invention, in a semiconductor device in which two or more types of transistor regions having different breakdown voltages are mixed, a source / drain diffusion layer of a high breakdown voltage transistor region is a low concentration diffusion layer at a field edge portion. It is characterized by being formed.

According to a fifth aspect of the present invention, in a semiconductor device in which two or more types of transistor regions having different breakdown voltages are mounted, a source / drain diffusion layer of a standard breakdown voltage transistor region is formed of a high-concentration diffusion layer, and a gate electrode is formed. A low-concentration diffusion layer is spread so as to overlap a part of the gate electrode, and the source-drain diffusion layer in the high-breakdown-voltage transistor region is formed of a low-concentration diffusion layer. The low-concentration diffusion layer extends over a part of the gate electrode. It is characterized in that the wiring layer is extended and at least the high-concentration impurity is implanted into the source / drain diffusion layer in the high breakdown voltage transistor region to form a wiring layer thereon.

According to a sixth aspect of the present invention, in the semiconductor device in which two or more transistor regions having different withstand voltages are mounted, the source / drain diffusion layer of the high withstand voltage transistor region is located near the intersection of the gate electrode and the transistor active region. It is not formed.

According to a seventh aspect of the present invention, in a method of manufacturing a semiconductor device in which two or more transistor regions having different withstand voltages are mounted, a field oxide film for element isolation and a gate on the transistor region are provided on the semiconductor substrate. An oxide film, a step of forming a gate electrode in a region where a gate electrode is to be formed, a step of implanting low-concentration impurity ions into a transistor region using the gate electrode as a mask, and forming a sidewall film on a side wall of the gate electrode Thereafter, a step of forming a resist film so as to cover the field edge portion of the high breakdown voltage transistor region and implanting high concentration impurity ions is included.

In a semiconductor device in which two or more transistor regions having different withstand voltages are mounted, the source / drain diffusion layer of the standard withstand voltage transistor region is formed of a high-concentration diffusion layer, and the gate electrode The low-concentration diffusion layer is spread so as to partially overlap the high-voltage transistor region, and the high-concentration diffusion layer is mainly formed in the source-drain diffusion layer of the high-breakdown-voltage transistor region, and the low-concentration diffusion layer is formed at the field edge portion. And extends over a part of the gate electrode.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 (a)-
(C) and FIGS. 2A and 2B are cross-sectional views showing a manufacturing flow of the semiconductor device according to the first embodiment of the present invention.

In the figure, 1 is a well diffusion layer of a semiconductor substrate, 2 is a field oxide film for element isolation, 3 is a thermal oxide film, A is a standard (high-speed) MOS transistor region, B is a high voltage MOS transistor region, 6 Is a resist film, 7 is oxygen (O) or fluorine (F ⁺ ) ions, 8a and b are gate oxide films, 9 and 10 are polysilicon films and silicide films for gate electrodes, and 11 is a source / drain diffusion layer. The source / drain diffusion layer 11 is a P-channel MOS
The transistor is N-type, and the N-channel MOS transistor is P-type.

Next, the process flow of the first embodiment will be described. First, as shown in FIG. 1A, a field oxide film 2 for element isolation is formed on a well diffusion layer 1 on a semiconductor substrate. The thermal oxide film 3 exists on the active region of the MOS transistor. In the drawing, the region A is a region where a standard (high-speed) MOS transistor is to be formed, and the region B is a region where a high breakdown voltage MOS transistor is to be formed. The area is shown.

Next, as shown in FIG.
A resist film 6 is formed on the S transistor region A, and oxygen (O) or fluorine (F ⁺ ) ions 7 are implanted into the active region of the high breakdown voltage MOS transistor region B using the resist film 6 as a mask.

Then, as shown in FIG. 1C, after removing the resist film 6, the oxide film 3 on the transistor active region is removed.

Next, when gate oxidation (thermal oxidation) is performed, gate oxide films 8a and 8b are formed as shown in FIG. At this time, the film thickness h2 of the gate oxide film 8b in the high breakdown voltage MOS transistor region B into which the oxygen (O) or fluorine (F ⁺ ) ions 7 are implanted is the same as the film thickness of the gate oxide film 8a in the standard (high-speed) MOS transistor region A. It is formed thicker than the thickness h1, and the breakdown voltage of the MOS transistor region B can be increased. This utilizes the effect of accelerated oxidation by oxygen (O) or fluorine (F ⁺ ) ions 7. In addition,
The thickness h2 of the gate oxide film 8b can be optimally controlled by the amount of oxygen (O) or fluorine (F ⁺ ) ions 7 to be implanted.

Finally, as shown in FIG. 2B, a polysilicon film 9 serving as a gate electrode and a silicide 10 are formed on the gate oxide films 8a and 8b, and then the gate oxide film 8 is formed.
a, b, the polysilicon film 9 and the silicide 10 are selectively removed, and an impurity having a conductivity opposite to that of the well diffusion layer 1 is diffused into the well diffusion layer 1 so as to be formed in the A region and the B region, respectively. A source / drain diffusion layer 11 is formed.

As described above, according to the first embodiment, an oxidation promoting substance such as oxygen (O) or fluorine (F ⁺ ) ion is implanted into the high breakdown voltage MOS transistor region, and the amount of the implanted oxidation promoting substance is varied. By controlling the oxidation rate at the time of gate oxidation to increase, a thick gate oxide film is simultaneously formed on the high voltage MOS transistor region and a thinner gate oxide film is formed on the standard MOS transistor region. That is, the standard transistor region and the high-withstand-voltage transistor region can be mixedly mounted on one semiconductor substrate (one chip), and can be formed by one-time gate oxidation as a process step. There is an effect that need not be performed twice.

Embodiment 2 FIG. 3 (a) to 3 (c) and FIG. 4 (a) are cross-sectional views showing a manufacturing flow of the semiconductor device according to the second embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a well diffusion layer of a semiconductor substrate. On this well diffusion layer 1, a field oxide film 2 for element isolation and MOS transistor regions (standard and high breakdown voltage MOS transistor regions A and B) are provided. A gate oxide film 8a is formed thereon. The polysilicon film 9 for the gate electrode and the silicide film 1 are formed on the gate oxide film 8a.
0 is formed. 12 is LDD (Lightly doped drai
n) low-concentration impurity ions implanted to form a low-concentration diffusion layer; 13 denotes LDD (Lightly doped drain)
, A high concentration impurity ion implanted to form a high concentration diffusion layer, 14 a side wall oxide film formed on the side wall of the gate electrode, 15a a low concentration source / drain diffusion layer, 15b a high concentration source / drain Diffusion layer, 16 is S
High concentration impurity ions for AC (Self Aligned Contact), 17 is an interlayer insulating film, 18 is silicide, 19 is aluminum wiring, and 23 is a contact opening.

Next, a process flow of the semiconductor device of the second embodiment will be described. First, as shown in FIG. 3A, a field oxide film 2 for element isolation is formed on a well diffusion layer 1 of a semiconductor substrate, and is formed on a standard (high-speed) MOS transistor region A and a high breakdown voltage MOS transistor region B. A gate oxide film 8a is formed. Then, after a polysilicon film 9 and a silicide film 10 for a gate electrode are formed in a region where a gate electrode is to be formed, an LDD (Lightly doped drai) is formed in the transistor region using the gate electrode as a mask.
In order to form the low concentration diffusion layer of n), low concentration impurity ions 12 are implanted.

Next, as shown in FIG. 3B, after forming sidewall films 14 on both side walls of the gate electrode, a resist film 6 is formed so as to cover at least the high breakdown voltage MOS transistor region B. Using the resist film 6 as a mask, only on the standard (high-speed) MOS transistor region A,
In order to form a high concentration diffusion layer of LDD (Lightly doped drain), high concentration impurity ions 13 are implanted.

Next, as shown in FIG. 3C, after an interlayer insulating film 17 is formed on the semiconductor substrate, the interlayer insulating film 17 and the gate oxide film 8a in the region where the wiring is to be formed are selectively etched. The contact opening 23 is formed. At this time, the position of the contact opening 23 should not overlap at least the field edge of the source / drain diffusion layer of the transistor. Thereafter, the SAC (Self-Self) is formed on each transistor region through the contact opening 23.
A high concentration impurity ion 50 for Aligned Contact (self-aligned connection) is implanted to reduce the contact resistance with the source / drain diffusion layers.

Thereafter, as shown in FIG. 4A, silicide 18 for wiring and aluminum wiring 19 are formed in the contact opening 23.

As described above, according to the second embodiment, the source / drain diffusion layer in the high breakdown voltage MOS transistor region B becomes the low concentration diffusion layer 15a at the field edge. With this structure, the breakdown voltage between the source / drain diffusion layer and the well is improved, so that the breakdown voltage of the MOS transistor can be increased.

Embodiment 3 FIG. 5A is a plan view showing a semiconductor device according to a third embodiment of the present invention, and FIG.
FIG. 6 is a side sectional view showing the semiconductor device of FIG.

In the figure, 1 is a well diffusion layer on a semiconductor substrate, 2 is a field oxide film for element isolation, A is a standard (high-speed) MOS transistor region, B is a high voltage MOS transistor region, 8a is a gate oxide film, 9 and 10 are a polysilicon film and a silicide film for a gate electrode, 14 is a sidewall oxide film, 15a is a low concentration source / drain diffusion layer, 15b is a high concentration source / drain diffusion layer, 20
Is a transistor active region, 21 is a gate electrode, and 22 is a resist film for forming a source / drain.

Next, a process flow of the semiconductor device of the third embodiment will be described. First, a field oxide film 2 for element isolation is formed on a well diffusion layer 1 of a semiconductor substrate, and a gate oxide film 8a is formed on a standard (high-speed) MOS transistor region A and a high breakdown voltage MOS transistor region B. Then, after forming the polysilicon film 9 and the silicide film 10 for the gate electrode, the transistor region is LDD (Lightly doped dr.) Using the gate electrode as a mask.
In order to form the low concentration source / drain diffusion layer 15a of (ain), low concentration impurity ions are implanted. At this time,
In the high breakdown voltage MOS transistor region B, a resist film 22 is formed near the intersection of the edge of the transistor active region 20 and the gate electrode.
Is used as a mask to implant the low concentration impurity ions.

Next, after a sidewall film 14 is formed on both side walls of the gate electrode, an LDD (Lightly doped drai
In order to form the high concentration diffusion layer of n), high concentration impurity ions are implanted. At this time, in the high-breakdown-voltage MOS transistor region B, the resist film 22 is formed near the intersection of the edge of the transistor active region 20 and the gate electrode.
Is formed, and the high concentration impurity ions are implanted using the resist film 22 as a mask.

FIG. 5B is a sectional view taken along the line CC of FIG. 5A. In the high breakdown voltage MOS transistor region B, the edge of the transistor active region 20 and the gate electrode 21 (polysilicon film) 9 and the silicide film 10), the source / drain diffusion layers 15a and 15a
Since 5b does not exist, a high breakdown voltage can be achieved. Because
This is because the electric field tends to concentrate at the intersection of the edge of the transistor active region and the gate electrode, which causes the breakdown voltage to decrease.

Embodiment 4 6 (a) to 6 (c) are cross-sectional views showing a flow of manufacturing a semiconductor device according to Embodiment 4 of the present invention.

In the figure, 1 is a well diffusion layer of a semiconductor substrate, 2 is a field oxide film, A is a standard (high-speed) MOS transistor region, B is a high voltage MOS transistor region,
6 is a resist film, 8a is a gate oxide film, 9 and 10 are polysilicon films and silicide films for gate electrodes, 12 is low concentration impurity ions, 13 is high concentration impurity ions,
4 is a side wall oxide film, 15a is a low concentration source / drain diffusion layer, and 15b is a high concentration source / drain diffusion layer.

Next, a process flow of the semiconductor device of the fourth embodiment will be described. First, as shown in FIG. 6A, a field oxide film 2 for element isolation is formed on a well diffusion layer 1 on a semiconductor substrate, and a gate oxide film 8a, a polysilicon film 9 for a gate electrode, and a silicide film are formed. After the formation of LDD 10, LDD (Light
Low concentration impurity ions 12 are implanted to form a low concentration diffusion layer of y doped drain).

Next, as shown in FIG. 6B, a sidewall film 14 is formed on the side wall of the gate electrode, and a photoresist film 6 is formed on the edge of the active region of the high breakdown voltage MOS transistor region B. . Then, using the sidewall film 14 and the resist film 6 as a mask, the LDD (Li
In order to form a high concentration diffusion layer (ghtly doped drain), high concentration impurity ions 13 are implanted.

After that, as shown in FIG. 6C, when the resist film 6 is removed, the source / drain diffusion layer in the standard breakdown voltage transistor region A is formed by the high concentration diffusion layer 15b, and the gate electrodes 9 and 10 are formed. The low-concentration diffusion layer 15a is spread so as to partially overlap, and the high-concentration diffusion layer 15b is mainly formed in the source / drain diffusion layer of the high-breakdown-voltage transistor region B. And spread over a part of the gate electrodes 9 and 10.

As described above, according to the fourth embodiment, the source / drain diffusion layer of the high breakdown voltage MOS transistor region B becomes the low concentration diffusion layer 15a at the field edge. With this structure, the breakdown voltage between the source / drain diffusion layer and the well is improved, so that the breakdown voltage of the MOS transistor can be increased.

Although the above embodiment has been described with reference to a MOS device, the present invention can be applied to not only a MOS device but also a BiCMOS device.

[0046]

As described above, according to the first aspect of the present invention, an oxidation accelerating substance is implanted into the high breakdown voltage transistor region, and the oxidation rate at the time of gate oxidation is controlled by increasing the amount of the injected oxidation accelerating substance. As a result, a thick gate oxide film is simultaneously formed on the high breakdown voltage transistor region and a thin gate oxide film is formed on the standard transistor region. As a result, the standard transistor region and the high breakdown voltage transistor region can be mixedly mounted on one semiconductor substrate (one chip), and can be formed by a single gate oxidation as a process step. There is an effect that it is not necessary to perform the operation twice.

According to the present invention, the source / drain diffusion layer in the high-breakdown-voltage MOS transistor region becomes a low-concentration diffusion layer at the field edge, so that the source / drain diffusion layer is The breakdown voltage between wells is improved, and the breakdown voltage of the transistor can be increased.

According to the sixth aspect of the present invention, a high breakdown voltage MO
In the S transistor region, since the source / drain diffusion layer does not exist near the intersection of the edge of the transistor active region and the gate electrode, concentration of the electric field at that portion can be prevented, and there is an effect that the breakdown voltage can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing flow of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view illustrating a manufacturing flow of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating a manufacturing flow of the semiconductor device according to Embodiment 2 of the present invention;

FIG. 4 is a sectional view illustrating a manufacturing flow of the semiconductor device according to the second embodiment of the present invention;

FIG. 5 is a plan view and a side sectional view showing a semiconductor device according to a third embodiment of the present invention;

FIG. 6 is a sectional view illustrating a manufacturing flow of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a manufacturing flow of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 well diffusion layer, 2 field oxide film, 6 resist film, 7 oxidation promoting material, 8a, b gate oxide film, 9
Polysilicon film, 10 silicide film, 11 source / drain diffusion layer, 12 low concentration impurity ion, 13 high concentration impurity ion, 14 sidewall oxide film, 1
5a low concentration source / drain diffusion layer, 15b high concentration source / drain diffusion layer, 16 SAC (Self Aligned)
High concentration impurity ions for contact, 17 interlayer insulating film, 18 silicide, 19 aluminum wiring, 20 transistor active region, 21 gate electrode, 22 source
Resist film for drain formation, 23 contact opening, A standard MOS transistor area, B high breakdown voltage MO
S transistor region.

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor device in which two or more transistor regions having different withstand voltages are mixed, a step of selectively injecting an oxidation promoting substance into a high withstand voltage transistor region on a semiconductor substrate; Forming a gate oxide film on a transistor region having a high withstand voltage, and forming a gate oxide film in a high withstand voltage transistor region thicker than a gate oxide film in a standard withstand voltage transistor region. 2. A method of manufacturing a semiconductor device in which two or more transistor regions having different withstand voltages are mixed, a field oxide film for element isolation on a semiconductor substrate, a gate oxide film on a transistor region, and a gate electrode. Forming a gate electrode in a region to be formed; implanting low-concentration impurity ions into the transistor region using the gate electrode as a mask; forming a sidewall film on a side wall of the gate electrode; Forming a resist film so as to cover the substrate, implanting high-concentration impurity ions into the standard-breakdown-voltage transistor region, implanting high-concentration impurities into at least the source-drain diffusion layer of the high-breakdown-voltage transistor region, and forming a wiring thereon Forming a layer. 3. The method according to claim 2, wherein a high-concentration impurity is implanted into the source / drain diffusion layer of the high breakdown voltage transistor region in a self-aligned manner. 4. A semiconductor device in which two or more transistor regions having different breakdown voltages are mounted, wherein a source / drain diffusion layer of a high breakdown voltage transistor region is formed of a low concentration diffusion layer at a field edge portion. Characteristic semiconductor device. 5. A semiconductor device in which two or more transistor regions having different breakdown voltages are mounted, wherein the source / drain diffusion layer of the standard breakdown voltage transistor region is
The low-concentration diffusion layer is formed of a high-concentration diffusion layer, and extends over a part of the gate electrode. The source-drain diffusion layer in the high-breakdown-voltage transistor region is formed of a low-concentration diffusion layer. The high concentration diffusion layer extends over a part of the gate electrode, and at least the high concentration impurity is implanted into at least the source / drain diffusion layer of the high breakdown voltage transistor region to form a wiring layer thereon. Semiconductor device. 6. A semiconductor device in which two or more transistor regions having different breakdown voltages are mounted, wherein a source / drain diffusion layer of a high breakdown voltage transistor region is not formed in the vicinity of the intersection of a gate electrode and a transistor active region. Characteristic semiconductor device. 7. A method for manufacturing a semiconductor device in which two or more transistor regions having different withstand voltages are mixed, a field oxide film for element isolation on a semiconductor substrate, a gate oxide film on a transistor region, and a gate electrode. Forming a gate electrode in a region to be formed; implanting low-concentration impurity ions into the transistor region using the gate electrode as a mask; forming a sidewall film on a side wall of the gate electrode; Forming a resist film so as to cover the field edge portion, and implanting high-concentration impurity ions. 8. A semiconductor device in which two or more types of transistor regions having different withstand voltages are mixed, wherein the source / drain diffusion layer of the standard withstand voltage transistor region includes:
The high-concentration diffusion layer is formed of a high-concentration diffusion layer, and the low-concentration diffusion layer is extended so as to overlap a part of the gate electrode. A semiconductor device, wherein a diffusion layer having a concentration is formed at a field edge portion and extends over a part of a gate electrode.