JP2001185724A - Method of manufacturing dmos transistor - Google Patents

Method of manufacturing dmos transistor

Info

Publication number
JP2001185724A
JP2001185724A JP36701499A JP36701499A JP2001185724A JP 2001185724 A JP2001185724 A JP 2001185724A JP 36701499 A JP36701499 A JP 36701499A JP 36701499 A JP36701499 A JP 36701499A JP 2001185724 A JP2001185724 A JP 2001185724A
Authority
JP
Japan
Prior art keywords
layer
mask
mask layer
manufacturing
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP36701499A
Other languages
Japanese (ja)
Inventor
Akira Sato
彰 佐藤
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, セイコーエプソン株式会社 filed Critical Seiko Epson Corp
Priority to JP36701499A priority Critical patent/JP2001185724A/en
Publication of JP2001185724A publication Critical patent/JP2001185724A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856Source regions
    • H01L29/086Impurity concentration or distribution
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

[PROBLEMS] To provide a method of manufacturing a DMOS transistor which reduces manufacturing costs while maintaining reliability while reducing man-hours. A silicon substrate forms an N -type drift region. On this substrate 11, a mask layer 1 for selective oxidation is formed.
The second pattern is formed and selectively oxidized to form the element isolation insulating film 13. Thereafter, a lithography step is added to the mask layer 12 again, and the mask layer 12 is etched according to the pattern of the resist 14. This etched mask layer is a P + type body diffusion layer,
It is used as an ion implantation mask for an N type source offset layer. Thereby, the subsequent gate formation process
This is achieved by the same process as the process of forming the MOS transistors other than the DMOS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a monolithic IC.
DMOS (Double diffused Metal Oxide Semiconducducer) which requires high breakdown voltage and low on-resistance
tor) type transistors.

[0002]

2. Description of the Related Art LSI chips are diversified, and high integration, miniaturization, and low power consumption are required. For example, a drive circuit or the like at the output stage of a liquid crystal driver IC is required to have a high withstand voltage and a low on-resistance, and a DMOS (Double diffused MOS) transistor is configured.

FIG. 9 is a sectional view showing a main part of a conventional method for manufacturing a DMOS transistor. For example, after an element isolation insulating film 22 is formed on a silicon substrate 21 having an N type drift region, a gate oxide film 23 is formed and the gate electrode 24 is patterned. Thereafter, a resist 26 for forming the P + type body diffusion layer 25 is formed. This P + type body diffusion layer 25 is
Is achieved by ion implantation (dotted line) using silicon as a mask and annealing diffusion.

Thereafter, the resist 26 is removed, and ion implantation for forming source / drain regions is performed using the gate electrode 24 as a mask (not shown). After forming the DMOS type transistor in this way, other MOS transistors other than the DMOS are used.
Enters the type transistor forming process.

[0005]

The formation of a DMOS transistor involves ion implantation and high-temperature diffusion of a self-aligned body portion using a gate electrode as a mask.
Therefore, generally, before forming another MOS transistor such as a logic portion, the threshold of which is controlled by channel doping, the DM transistor is formed.
It is necessary to form an OS transistor. Therefore, it is necessary to provide a lithography process dedicated to each of the DMOS type and the MOS type rather than the gate forming process.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a DMOS transistor which can reduce man-hours while maintaining reliability while reducing manufacturing costs. .

[0007]

A method of manufacturing a DMOS transistor according to the present invention includes a lithography step of selectively etching a mask layer on an element region when a semiconductor substrate of a first conductivity type is selectively oxidized. Forming a second conductive type body diffusion layer on the element region using the mask layer as an ion implantation mask; and forming a first conductive layer on the surface of the body diffusion layer using the mask layer as an ion implantation mask. Forming a mold offset layer, removing the mask layer and forming a gate electrode partially overlapping on the body diffusion layer and the offset layer via a gate oxide film, and using the gate electrode as a mask. Forming source and drain regions on the element region.

According to the method for manufacturing a DMOS transistor of the present invention, the mask layer covering the element region when the semiconductor substrate is selectively oxidized is selectively etched again to form a mask for the body diffusion layer. Form a layer. This mask layer is used to form an offset layer in a self-aligned manner.
Subsequent gate electrode formation can be performed in common with other transistors. Since the offset layer is also formed before the formation of the gate electrode, the diffusion profile of the offset layer and the body diffusion layer does not change even if the gate electrode is formed with some deviation.

[0009]

1 to 8 show a DMOS (Double diffused Metal Oxide) according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a main part of a method for manufacturing a semiconductor (transistor) type transistor in the order of steps.

First, as shown in FIG.
1 forms an N type drift region. A pattern of a mask layer 12 (Si 3 N 4 film) for selective oxidation is formed on the substrate 11, and the exposed portion of the pattern is selectively oxidized. Thus, an element isolation insulating film 13 (SiO 2 film) is formed. Thereafter, a resist 14 is selectively formed on the mask layer 12 in order to add a lithography step again.

Next, as shown in FIG.
2 is selectively etched according to the pattern of the resist 14 to form a mask layer 12A. This mask layer 1
Using 2A as an ion implantation mask, P + -type impurity ions are implanted into the element region. This allows
A P + type body part (15) is formed. After that,
As shown in FIG. 3, a P + -type body diffusion layer 15 in which a partial region enters below the mask layer 12A is formed by an appropriate annealing process.

Next, as shown in FIG. 4, using the mask layer 12A as an ion implantation mask, N-type impurity ions are implanted into the surface of the P + -type body diffusion layer 15 on the element region. Thus, an N type source offset layer 16 is formed. After that, as shown in FIG.
The mask layer 12A is removed.

Next, as shown in FIG.
7 is formed. Thereafter, CVD is performed on the gate oxide film 17.
Polysilicon is deposited by a (Chemical Vapor Deposition) method or the like. Then, as shown in FIG. 7, the polysilicon is selectively etched and removed through a lithography process to form a gate electrode 18.

The gate electrode 18 is provided so as to partially overlap the P + type body diffusion layer 15 and the source offset layer 16. That is, the gate electrode 18
Are formed on the element region so as to overlap from the edge of the P + type body diffusion layer 15 to the vicinity of the edge of the source offset layer 16. More specifically, the gate electrode 18 has a pattern corresponding to the pattern of the mask layer 12A.
It is formed to overlap the source offset layer 16 side by 0.3 μm or more.

Next, as shown in FIG.
Are used as masks to form source and drain regions on the element region.
The + type diffusion layer 19 is formed. The formation of the gate electrode 18 and the N + type diffusion layer 19 serving as the source and drain regions.
Is formed at the same time as the transistor forming process other than the DMOS.

According to the method of the above-described embodiment, the mask in which the mask layer for forming the element isolation insulating film 13 is selectively etched again is used for the ion implantation and the high-temperature diffusion processing of the body part peculiar to the DMOS transistor. You. That is, the mask layer 12A for the P + type body diffusion layer 15
Then, it is used as a mask layer 12A for forming the source offset layer 16 in a self-aligned manner.

If the above-described manufacturing process is adopted, another M such as a logic portion, whose threshold is controlled by channel doping, may be used.
At the same time as the formation of the OS transistor, the remaining steps of forming the DMOS transistor are included. This eliminates the need to separate the DMOS type and the MOS type in the gate forming step, and the gate forming step can be performed twice to once. As a result, a lithography step, a cleaning step, and the like can be reduced, and a significant reduction in manufacturing cost can be expected. Since the formation after the gate is performed simultaneously, the adverse effect of the other transistors on the DMOS is naturally eliminated.

Before the formation of the gate electrode 18, the mask layer 1 is formed.
Since the P + -type body diffusion layer 15 and the source offset layer 16 are formed using 2A, the diffusion profile of the source offset layer and the P + -type body diffusion layer does not change even if the gate electrode 18 is formed with some deviation. Absent. As a result, the number of steps can be reduced, and high reliability of manufacturing can be maintained.

When the gate electrode 18 is patterned, by positively overlapping it with the source offset layer 16 side, for example, a double diffusion structure can be formed only on the source side, and the punch-through breakdown voltage can be improved. In this manufacturing method, a lightly doped region (source offset layer 16) is formed without forming a so-called side wall (spacer).
There is an advantage that can be provided. From this point of view, a highly reliable DMOS transistor can be incorporated in a monolithic IC at low cost while reducing man-hours.

[0020]

As described above, according to the method of the present invention, the mask layer covering the element region when the semiconductor substrate is selectively oxidized is selectively etched again to form a body diffusion layer. Is formed. This mask layer is used to form an offset layer in a self-aligned manner. Thus, subsequent gate electrode formation can be performed in common with other transistors. Since the offset layer is also formed before the gate electrode is formed, there is no change in the diffusion profiles of the offset layer and the body diffusion layer. As a result, it is possible to provide a method for manufacturing a DMOS transistor that reduces manufacturing costs while maintaining high reliability while reducing man-hours in LSI manufacturing.

[Brief description of the drawings]

FIG. 1 shows a DMOS (Double dif) according to an embodiment of the present invention.
FIG. 4 is a first cross-sectional view showing a main part of a method of manufacturing a fused MOS) transistor in the order of steps.

FIG. 2 is a second cross-sectional view following FIG. 1 showing a main portion of a method of manufacturing the DMOS transistor according to the embodiment of the present invention in the order of steps.

FIG. 3 is a third cross-sectional view following FIG. 2 showing a main portion of the method for manufacturing the DMOS transistor according to the embodiment of the present invention in the order of steps.

FIG. 4 is a fourth cross-sectional view following FIG. 3 showing a main portion of the method for manufacturing the DMOS transistor according to the embodiment of the present invention in the order of steps.

FIG. 5 is a fifth sectional view following FIG. 4 and showing the main parts of the method for manufacturing the DMOS transistor according to the embodiment of the present invention in the order of steps;

FIG. 6 is a sixth sectional view following FIG. 5 and showing the main parts of the method for manufacturing the DMOS transistor according to the embodiment of the present invention in the order of steps.

FIG. 7 is a seventh cross-sectional view following FIG. 6 showing the main part of the method for manufacturing the DMOS transistor according to the embodiment of the present invention in the order of steps.

FIG. 8 is an eighth cross-sectional view following FIG. 7 showing the main part of the method for manufacturing the DMOS transistor according to the embodiment of the present invention in the order of steps.

FIG. 9 is a cross-sectional view showing a main part in a conventional method for manufacturing a DMOS transistor.

[Explanation of symbols]

11, 21 ... silicon substrate 12, 12A ... mask layer 13, 22 ... element isolation insulating film 14, 26 ... resist 15, 25 ... P + type body diffusion layer 16 ... source offset layer 17, 23 ... gate oxide film 18, 24 ... Gate electrode 19 ... N + type diffusion layer

Claims (2)

[Claims]
1. A lithography step of selectively etching a mask layer on an element region when a semiconductor substrate of a first conductivity type is selectively oxidized, and the element region using the mask layer as an ion implantation mask. Forming a second conductivity type body diffusion layer thereon; using the mask layer as an ion implantation mask to form a first conductivity type offset layer on the surface of the body diffusion layer; removing the mask layer Forming a gate electrode partially overlapping on the body diffusion layer and the offset layer via a gate oxide film; and forming source and drain regions on the element region using the gate electrode as a mask. A method for manufacturing a DMOS transistor, comprising:
2. The method of manufacturing a DMOS transistor according to claim 1, wherein the gate electrode is formed so as to overlap the pattern of the mask layer by 0.3 μm or more toward the offset layer.
JP36701499A 1999-12-24 1999-12-24 Method of manufacturing dmos transistor Withdrawn JP2001185724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36701499A JP2001185724A (en) 1999-12-24 1999-12-24 Method of manufacturing dmos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36701499A JP2001185724A (en) 1999-12-24 1999-12-24 Method of manufacturing dmos transistor

Publications (1)

Publication Number Publication Date
JP2001185724A true JP2001185724A (en) 2001-07-06

Family

ID=18488256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP36701499A Withdrawn JP2001185724A (en) 1999-12-24 1999-12-24 Method of manufacturing dmos transistor

Country Status (1)

Country Link
JP (1) JP2001185724A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906820B2 (en) 2007-11-13 2011-03-15 Ricoh Company, Ltd. Source offset MOSFET optimized for current voltage characteristic invariance with respect to changing temperatures
CN102543738A (en) * 2010-12-20 2012-07-04 上海华虹Nec电子有限公司 High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same
CN102810514A (en) * 2011-06-01 2012-12-05 北大方正集团有限公司 Method and system for manufacturing complementary metal oxide semiconductors of high-voltage metal gates
US20130017675A1 (en) * 2011-07-14 2013-01-17 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor device
CN105990139A (en) * 2015-01-30 2016-10-05 无锡华润上华半导体有限公司 Method of manufacturing lateral diffusion metal oxide semiconductor field effect transistor
WO2017175544A1 (en) * 2016-04-06 2017-10-12 株式会社デンソー Semiconductor device and method for manufacturing same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906820B2 (en) 2007-11-13 2011-03-15 Ricoh Company, Ltd. Source offset MOSFET optimized for current voltage characteristic invariance with respect to changing temperatures
CN102543738A (en) * 2010-12-20 2012-07-04 上海华虹Nec电子有限公司 High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same
CN102810514A (en) * 2011-06-01 2012-12-05 北大方正集团有限公司 Method and system for manufacturing complementary metal oxide semiconductors of high-voltage metal gates
US20130017675A1 (en) * 2011-07-14 2013-01-17 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor device
JP2013021242A (en) * 2011-07-14 2013-01-31 Sumitomo Electric Ind Ltd Semiconductor device manufacturing method
US8748276B2 (en) * 2011-07-14 2014-06-10 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor device
CN105990139A (en) * 2015-01-30 2016-10-05 无锡华润上华半导体有限公司 Method of manufacturing lateral diffusion metal oxide semiconductor field effect transistor
WO2017175544A1 (en) * 2016-04-06 2017-10-12 株式会社デンソー Semiconductor device and method for manufacturing same
JP2017188585A (en) * 2016-04-06 2017-10-12 株式会社デンソー Semiconductor device and manufacturing method of the same

Similar Documents

Publication Publication Date Title
US6518623B1 (en) Semiconductor device having a buried-channel MOS structure
USH986H (en) Field effect-transistor with asymmetrical structure
DE4212829C2 (en) Process for the production of metal oxide semiconductor field effect transistors
EP0749165B1 (en) Thin film transistor in insulated semiconductor substrate and manufacturing method thereof
US7144780B2 (en) Semiconductor device and its manufacturing method
KR100584711B1 (en) Semiconductor device, method for manufacturing the semiconductor device
US7071529B2 (en) Semiconductor device having a Damascene gate or a replacing gate
US6277675B1 (en) Method of fabricating high voltage MOS device
JP3946545B2 (en) Method for manufacturing CMOS thin film transistor
US5302845A (en) Transistor with an offset gate structure
US6010929A (en) Method for forming high voltage and low voltage transistors on the same substrate
US5465005A (en) Polysilicon resistor structure including polysilicon contacts
US6855581B2 (en) Method for fabricating a high-voltage high-power integrated circuit device
JP4851080B2 (en) LDMOS transistor device, integrated circuit and manufacturing method thereof
US4885617A (en) Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit
JP2004241755A (en) Semiconductor device
US6787849B2 (en) Semiconductor devices and methods of manufacturing the same
US20030127702A1 (en) Termination structure for a semiconductor device
JP3532188B1 (en) Semiconductor device and manufacturing method thereof
US7256092B2 (en) Method for fabricating integrated circuits having both high voltage and low voltage devices
KR20020072494A (en) Field effect transistor and semiconductor device manufaturing method
US6815284B2 (en) Manufacturing method of semiconductor device
EP0918353A1 (en) A method of manufacturing a recessed insulated gate field-effect semiconductor device
US6190981B1 (en) Method for fabricating metal oxide semiconductor
US5397715A (en) MOS transistor having increased gate-drain capacitance

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20070306