JP2007335784A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of making compatible improvement in the NBTI service life of a pMOS transistor and improvement in the performance of an nMOS transistor. <P>SOLUTION: A high-speed operating circuit formed in the semiconductor device comprises: an nMOS transistor including, as a component, an SiON gate insulating film (first gate insulating film) 13 in which fluorine is not introduced, and a pMOS transistor including, as a component, the SiON gate insulating film (second gate insulating film) 14 which is thicker than the SiON gate insulating film 13, and in which fluorine is introduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and can be applied to, for example, a semiconductor device using a leading-edge CMOS having a 65 nm node or later and a manufacturing method of the semiconductor device.

  In recent CMOS devices, a plurality of pMOS transistors and nMOS transistors are formed in one semiconductor device. More specifically, an input / output circuit portion and a high-speed operation circuit portion to which a voltage lower than that of the input / output circuit portion is applied are formed in one semiconductor device. A plurality of nMOS transistors are formed.

  Note that Patent Documents 1 and 2 and Non-Patent Document 1 exist as prior arts related to the present invention.

JP 2001-237324 A Japanese Patent Laid-Open No. 10-64898 T. T. et al. Aoyama, “Effect of fluorine on boron diffusion in thin silicon dioxides and oxynitride”, Journal of applied physics vol. 77 (1), 1995, pp417

  However, one of the most important problems that control the reliability of advanced CMOS devices in recent years is a life when a negative gate bias is applied to a pMOS transistor, that is, a so-called NBTI (Negative Bias Temperature Instability) life. As the technology generation advances, it is becoming increasingly difficult to ensure the NBTI life.

  By the way, a MOS transistor of a high-speed operation circuit is required to have a high on-current in order to realize a high-frequency operation. In the SRAM (Static Random Access Memory), the demand is particularly strong in an nMOS transistor.

  Therefore, an object of the present invention is to provide a semiconductor device that can achieve both improvement in the NBTI life of a pMOS transistor and improvement in performance of an nMOS transistor. It is another object of the present invention to provide a semiconductor device manufacturing method that can manufacture the semiconductor device by a simpler method without affecting the performance of the semiconductor device.

  In order to achieve the above object, a semiconductor device according to claim 1 according to the present invention is applied with an input / output circuit section and a voltage lower than that of the input / output circuit section, and the film is thinner than the input / output circuit section A high-speed operation circuit unit having a thin gate insulating film, wherein the high-speed operation circuit unit is formed in a first region on the surface of the semiconductor substrate and is not introduced with fluorine. A gate insulating film, a first gate electrode formed on the surface of the first gate insulating film, and the semiconductor substrate facing the first gate electrode. An nMOS transistor having a pair of n-type impurity diffusion regions and a second region on the surface of the semiconductor substrate, which is thicker than the first gate insulating film, and the fluorine is contained in the film. The second gate where was introduced An edge film, a second gate electrode formed on the surface of the second gate insulating film, containing impurities and containing at least silicon as a constituent element, and the semiconductor substrate facing the second gate electrode interposed therebetween And a pMOS transistor having a pair of p-type impurity diffusion regions formed in the surface of the semiconductor substrate.

  According to a seventh aspect of the present invention, there is provided a semiconductor device manufacturing method comprising a pMOS transistor and an nMOS transistor, wherein the first gate insulating film is provided on the surface of the semiconductor substrate. Forming a gate electrode material, forming a mask covering the surface of the nMOS transistor formation region and opening at least a part of the surface of the pMOS transistor formation region, and after forming the mask, the semiconductor substrate Injecting fluorine into the upper surface, introducing the fluorine into at least a part of the gate electrode material of the pMOS transistor formation region, performing a heat treatment after the fluorine introduction, and performing the heat treatment, And introducing an impurity into the gate electrode material in the pMOS transistor formation region.

  A method for manufacturing a semiconductor device according to claim 11 of the present invention is a method for manufacturing a semiconductor device having a pMOS transistor and an nMOS transistor, and the first gate insulating film is interposed on the surface of the semiconductor substrate. Forming a gate electrode material; forming a mask covering the surface of the nMOS transistor formation region and opening at least a part of the surface of the pMOS transistor formation region; and after forming the mask, Injecting oxygen into the pMOS transistor formation region, introducing the oxygen into at least a part of the gate electrode material, performing a heat treatment after the oxygen introduction, and after performing the heat treatment, and a step of introducing an impurity into the gate electrode material in the pMOS transistor formation region.

  The semiconductor device according to claim 1 of the present invention has a high-speed operation including an input / output circuit portion and a gate insulating film to which a voltage lower than that of the input / output circuit portion is applied and which is thinner than the input / output circuit portion. The high-speed operation circuit unit is formed in a first region on the surface of the semiconductor substrate, the first gate insulating film into which fluorine is not introduced, and the first device A first gate electrode formed on the surface of the gate insulating film and a pair of n-type impurity diffusion regions formed in the surface of the semiconductor substrate across the semiconductor substrate facing the first gate electrode. An nMOS transistor, and a second gate insulating film formed in a second region on the surface of the semiconductor substrate, having a thickness greater than that of the first gate insulating film, wherein the fluorine is introduced into the film And the second gate insulating film A pair formed on the surface of the semiconductor substrate with a second gate electrode formed on the surface, containing impurities and containing at least silicon as a constituent element, and the semiconductor substrate facing the second gate electrode. A pMOS transistor having a p-type impurity diffusion region.

  Therefore, it is possible to provide a semiconductor device that can simultaneously improve the NBTI lifetime of the pMOS transistor and improve the performance of the nMOS transistor.

  According to a seventh aspect of the present invention, there is provided a semiconductor device manufacturing method comprising a pMOS transistor and an nMOS transistor, wherein the gate is formed on the surface of the semiconductor substrate via the first gate insulating film. Forming an electrode material; forming a mask covering the surface of the nMOS transistor formation region and opening at least a part of the surface of the pMOS transistor formation region; and after forming the mask, Injecting fluorine into the gate electrode material in at least a part of the pMOS transistor formation region, performing a heat treatment after the fluorine introduction, and after performing the heat treatment, the pMOS transistor And a step of introducing impurities into the gate electrode material in the formation region.

  Therefore, the semiconductor device according to claim 1 can be manufactured by a simpler method without affecting the performance of the semiconductor device. Further, by adopting this method, it is possible to suppress the diffusion of impurities contained in the gate electrode constituting the pMOS transistor into the semiconductor substrate.

  A method for manufacturing a semiconductor device according to an eleventh aspect of the present invention is a method for manufacturing a semiconductor device including a pMOS transistor and an nMOS transistor, wherein the gate electrode is formed on the surface of the semiconductor substrate via the first gate insulating film. Forming a material; forming a mask covering the surface of the nMOS transistor formation region and opening at least a part of the surface of the pMOS transistor formation region; and after forming the mask, Injecting oxygen to introduce oxygen into at least a part of the gate electrode material of the pMOS transistor formation region, performing a heat treatment after the oxygen introduction, and forming the pMOS transistor after the heat treatment step And a step of introducing impurities into the gate electrode material in the region.

  Therefore, the semiconductor device according to claim 1 can be manufactured by a simpler method without affecting the performance of the semiconductor device. Further, by adopting this method, it is possible to suppress the diffusion of impurities contained in the gate electrode constituting the pMOS transistor into the semiconductor substrate.

  As a means for extending the NBTI lifetime of the pMOS transistor, the present invention employs a thick gate insulating film of the pMOS transistor. However, when the gate insulating film of the nMOS transistor is made thick as described above, the performance of the nMOS transistor is degraded (that is, the on-current is decreased). Therefore, focusing on the gate insulating film of the transistor, it can be said that there is a trade-off relationship between the NBTI lifetime and the transistor performance.

  By the way, the demand for transistor performance (improvement of on-current) in a CMOS device is often particularly severe in an nMOS transistor (hereinafter, a pMOS transistor is simply referred to as a pMOS and an nMOS transistor is simply referred to as an nMOS). ).

  For example, in the case of a so-called six-transistor type SRAM (Static Random Access Memory) circuit in which a memory cell is composed of four nMOS and two pMOS, a high on-current is required for the nMOS for high-frequency operation, while the pMOS is turned on. The demand for current is not as high as nMOS.

  Therefore, the semiconductor device according to the present invention adopts a configuration in which the gate insulating film of the pMOS is made thicker than that of the nMOS in the portion where the MOS transistor having an extremely thin gate insulating film such as a high-speed logic circuit such as an SRAM circuit is used. To do. As a result, a high-performance nMOS exhibiting a high on-current and a pMOS having high NBTI reliability can be realized at the same time.

  Hereinafter, a method for manufacturing a semiconductor device having the above-described configuration will be specifically described with reference to the drawings.

<Embodiment 1>
A method for manufacturing a semiconductor device according to the first embodiment will be described with reference to process cross-sectional views in part of the description. In the present embodiment, a method for manufacturing a semiconductor device in the case where an nMOS and a pMOS are simultaneously manufactured on the same silicon substrate and each has a single type of gate insulating film will be described. The semiconductor device manufacturing method according to the embodiment and the semiconductor device manufactured by the manufacturing method are the core of the present invention, and are intended for the formation of a high-speed element portion of a CMOS integrated circuit.

  Referring to FIG. 1, a p-type substrate is used as a silicon substrate (which can be grasped as a semiconductor substrate) 101, and an element isolation groove 102 is formed on the surface thereof using a well-known shallow groove element isolation method. Subsequently, boron (B) ions are implanted in a state where a desired region is covered with a resist by using photolithography, and a p-well (not shown) is formed in a region for forming an nMOS (which can be grasped as a first region). To do. Further, phosphorus (P) ions are implanted into a desired region other than the p well to form an n well (not shown) in a region where the pMOS is formed (which can be grasped as a second region).

  Further, in order to adjust the threshold voltage of the transistor, B ions are applied to a region for forming an nMOS (hereinafter simply referred to as an nMOS formation region), and a region for forming a pMOS (hereinafter simply referred to as a pMOS formation region). Implants a desired amount of arsenic (As) ions and activates these impurities by performing a heat treatment at about 850 ° C. for about 10 seconds in a nitrogen atmosphere.

  Thereafter, a silicon oxide film having a desired film thickness is formed by heat treatment in an oxygen-containing atmosphere, and then a well-known plasma nitriding process is performed to form a SiON gate insulating film (in the nMOS formation region on the silicon substrate 101). 103 (which can be grasped as a first gate insulating film) is formed, and a SiON gate insulating film (second gate insulating film) 104 is formed in the pMOS formation region on the silicon substrate 101. Then, a polycrystalline silicon film 120 having a thickness of 120 nm is deposited on the gate insulating films 103 and 104 by a known chemical vapor deposition method using monosilane as a source gas (that is, a gate is formed on the silicon substrate 101). The gate electrode material 120 is formed through the insulating films 103 and 104).

  Through the above steps, the semiconductor device in the middle of manufacture shown in FIG. 2 is formed.

  At this stage, processing that is the essence of the present invention is performed. First, a method using fluorine ion implantation will be described.

  As shown in FIG. 3, a mask 125 that covers the nMOS formation region with the resist 125 (that is, covers the surface of the nMOS formation region and opens at least a part of the surface of the pMOS formation region is formed using photolithography. In this state, fluorine ions are ion-implanted at an acceleration voltage of 10 kV (that is, after the mask 125 is formed, fluorine ions are implanted into the upper surface of the silicon substrate 101 to form at least a part of the gate electrode material in the pMOS formation region. (Fluorine ions are introduced into (polycrystalline silicon film) 120). Thereafter, after removing the resist 125, heat treatment is performed in a nitrogen atmosphere. The purpose of this heat treatment is to increase the thickness of the SiON gate insulating film 104 by causing the implanted fluorine ions to reach the SiON gate insulating film 104 in the pMOS formation region, and the excess fluorine remaining in the polycrystalline silicon film 120. It is to reduce ions as much as possible.

  Next, the case of using oxygen ion implantation which is another method of the present invention (that is, a method different from fluorine ion implantation) will be described.

  As shown in FIG. 4, after depositing a 40 nm silicon oxide film 130 on a polycrystalline silicon film 120 by chemical vapor deposition using tetraethoxysilane (Si (OC2H5) 4), an nMOS is formed using photolithography. With the region covered with the resist 125 (that is, with the mask 125 covering the surface of the nMOS formation region and opening at least a part of the surface of the pMOS formation region), oxygen ions are ionized at an acceleration voltage of 70 kV. Implantation (that is, after the mask 125 is formed, oxygen ions are implanted into the upper surface of the silicon substrate 101 to introduce oxygen ions into at least a part of the gate electrode material (polycrystalline silicon film) 120 in the pMOS formation region. ). Thereafter (that is, after introduction of oxygen ions), after removing the resist 125 and the silicon oxide film 130, heat treatment is performed in a nitrogen atmosphere. The purpose of this heat treatment is to increase the film thickness of the SiON gate insulating film 104 by causing the implanted oxygen ions to reach the SiON gate insulating film 104 in the pMOS formation region. Note that the reason why the silicon oxide film 130 is formed is that a device capable of implanting oxygen ions shallowly is not currently available, so that the implantation distance of oxygen ions implanted at high speed in the silicon oxide film 130 is adjusted. .

  In addition, by introducing a heat treatment after introducing the fluorine ions and oxygen ions, the thickness of the SiON gate insulating film 104 formed in the pMOS formation region is increased as shown in FIG.

Thereafter (that is, after heat treatment after introduction of fluorine ions or oxygen ions), 5 × 10 ¹⁵ / cm ² of P ions are implanted into the nMOS formation region in the polycrystalline silicon film 120 at an acceleration voltage of 15 kV. On the other hand, 2 × 10 ¹⁵ / cm ² of B ions are implanted into the pMOS formation region at an acceleration voltage of ² kV. Thereafter, the polycrystalline silicon film 120 and the respective SiON gate insulating films 103 and 104 are processed into desired dimensions using photolithography and dry etching. Thus, an n + gate electrode (can be grasped as the first gate electrode) 105 is formed in the nMOS formation region, and a p + gate electrode (can be grasped as the second gate electrode) 106 is formed in the pMOS formation region (FIG. 6). reference).

Here, 3 × 10 ¹⁴ / cm ² As is ion-implanted into the nMOS formation region with an acceleration voltage of 5 kV, and 3 × 10 ¹⁴ / cm ² B is ion-implanted into the pMOS formation region with an acceleration voltage of 1 kV. . As a result, low concentration regions of the n-type diffusion layer 107 and the p-type diffusion layer 108 are formed at predetermined locations in the surface of the silicon substrate 101 (see FIG. 6).

  Next, a silicon oxide film 100 nm is formed using tetraethoxysilane (Si (OC 2 H 5) 4) by chemical vapor deposition, followed by anisotropic dry etching to form a sidewall 109 made of silicon oxide. (See FIG. 6).

Thereafter, 5 × 10 ¹⁵ / cm ² As ions are implanted into the nMOS formation region with an acceleration voltage of 10 kV, and 5 × 10 ¹⁵ / cm ² B ions are implanted into the pMOS formation region with an acceleration voltage of 3 kV. . As a result, high concentration regions of the n-type diffusion layer 107 and the p-type diffusion layer 108 are formed at predetermined locations within the surface of the silicon substrate 101 (that is, having a two-level (high concentration / low concentration) concentration distribution). N-type diffusion layer 107 and p-type diffusion layer 108 are formed) (see FIG. 6).

  Next, heat treatment is performed at 1025 ° C. for 10 seconds to electrically activate the impurities implanted into the n-type diffusion layer 107 and the p-type diffusion layer 108. After performing the above heat treatment, a silicon oxide film is deposited with a thickness of 600 nm using tetraethoxysilane (Si (OC2H5) 4) by plasma enhanced chemical vapor deposition, and this is planarized by chemical mechanical polishing, An interlayer insulating film 110 is formed. Contact holes are formed in the interlayer insulating film 110 using photolithography and dry etching. Further, tungsten is deposited into the contact hole by chemical vapor deposition and sputtering, and this is processed by photolithography and dry etching to form the wiring 111 (see FIG. 6).

  Through the above steps, the nMOS and pMOS having the structure shown in FIG. 6 are completed. The actual formation of the advanced CMOS integrated circuit requires steps such as formation of sidewalls having a more complicated structure, self-aligned silicidation, and multilayer copper wiring, but they are omitted here.

  In the configuration of FIG. 6, when attention is paid to the SiON gate insulating film 103 formed in the nMOS formation region, fluorine (or oxygen) is not introduced into the SiON gate insulating film 103 as is apparent from the above process. . Further, the thickness of the SiON gate insulating film 104 is larger than the thickness of the SiON gate insulating film 103, as will be described later with reference to the drawings. , Fluorine (or oxygen) is introduced.

  A gate electrode 105 is formed on the surface of the SiON gate insulating film 103, and a gate electrode 106 is formed on the surface of the SiON gate insulating film 104. Here, as can be seen from the above configuration and process, the gate electrodes 105 and 106 contain at least silicon as a component. The gate electrode 105 includes at least P (phosphorus) as an impurity, and the gate electrode 106 includes at least B (boron (boron)) as an impurity.

  A pair of n-type impurity diffusion layers (diffusion regions) 107 are formed in the surface of the silicon substrate 101 with the silicon substrate 101 facing the gate electrode 105 interposed therebetween. On the other hand, a pair of p-type impurity diffusion layers (regions) 108 are formed in the surface of the silicon substrate 101 with the silicon substrate 101 facing the gate electrode 106 interposed therebetween.

  As is apparent from the above, the SiON gate insulating film 103, the gate electrode 105, and the impurity diffusion layer 107 constitute an nMOS. On the other hand, the SiON gate insulating film 104, the gate electrode 106, and the impurity diffusion layer 108 constitute a pMOS.

  Next, the characteristics of the pMOS fabricated by the technique using fluorine implantation will be described using experimental data.

  FIG. 7 shows the experimental results showing the relationship between the oxide film capacity equivalent film thickness (EOT, Equivalent Oxide Thickness) of the SiON gate insulating film 104 in the pMOS formation region and the fluorine implantation amount. The experimental results shown in FIG. 7 relate to a sample manufactured by performing a heat treatment at 850 ° C. for 10 minutes after fluorine implantation, and uses four types of SiON gate insulating films 104 as a base. Moreover, EOT is an electrical film thickness obtained from electrical capacitance measurement, and electrical capacitance measurement was performed using pMOS. The derivation of the EOT is based on S.E. Saito et al., IEEE Electron Device Letters Vol. 23 (2002) pp348 was adopted.

  As shown in FIG. 7, the SiON gate insulating film 104 in the pMOS formation region increases in proportion to the amount of fluorine implanted. The amount of film increase does not greatly depend on the thickness of the base SiON gate insulating film (film thickness before film increase). In addition, it was found that when a larger amount of fluorine than the data points shown in FIG. 7 is implanted, the interface state density increases abruptly as the electrical capacitance measurement becomes difficult. It is considered that the rapid increase in the interface state density determines the upper limit of the amount of film increase.

  The upper limit of the amount of film increase is 0.16 nm when the EOT of the base (before film increase) SiON gate insulating film 104 is 1.24 nm. When the EOT of the base SiON gate insulating film 104 is 1.54 nm, it is 0.20 nm. When the EOT of the base SiON gate insulating film 104 is 3.1 nm, it is 0.48 nm. When the EOT of the base SiON gate insulating film 104 is 7.0 nm, it is 0.92 nm.

  From these results, it can be concluded that the upper limit is less than 16% with respect to the EOT of the base (before film increase) SiON gate insulating film 104.

  There are two possible mechanisms for the increase in EOT due to the introduction of fluorine: a decrease in dielectric constant due to the introduction of fluorine into the SiON gate insulating film 104 and an increase in physical film thickness. However, P.I. J. et al. Wright et al., IEEE Transactions on Electron Devices Vol. 36 (1989), pp879, Mitani et al., IEEE Transactions on Electron Devices Vol. 50 (2003), pp 2221, it is considered that the mechanism of film increase is an increase in physical film thickness.

  That is, the fluorine implanted into the polycrystalline silicon film (gate electrode material) 120 reaches the SiON gate insulating film 104 by the subsequent heat treatment and substitutes for oxygen in the SiON, so that the remaining oxygen oxidizes the substrate interface. It is an understanding to increase the film.

Even in the inventors' investigation, as a result of measuring the change in the physical film thickness of the SiON gate insulating film 104 by observing with a transmission electron microscope, an increase in the physical film thickness due to the introduction of fluorine has been confirmed, which is the cause of the increase in EOT. Believes that the increase in physical film thickness is the main. However, K.K. Awazu et al., Journal of applied physics vol. 69 (8), 1991, pp 4183, the addition of fluorine to SiO ₂ is known to change its basic structure, and there are other effects than fluorine simply replacing oxygen. It is guessed. The addition of a certain amount of fluorine adversely affects the electrical characteristics (interface state density) because of this structural change. For this reason, the upper limit of the amount of film increase is less than 16% of the base SiON gate insulating film 104. I think that.

  Here, as can be seen from the above manufacturing process, the thickness of the base SiON gate insulating film is equal to the thickness of the SiON gate insulating film 103. Therefore, from the viewpoint of lowering the electrical characteristics (interface state density), the film thickness of the SiON gate insulating film 104 is less than 16% after the film increase (that is, the finished product) than the film thickness of the SiON gate insulating film 103. It is thick.

  Next, the influence of the heat treatment after fluorine implantation on the electrical characteristics of the SiON gate insulating film 104 will be described.

Here, the fluorine implantation conditions are an acceleration voltage of 10 kV and a dose of 1.5 × 10 ¹⁵ / cm ² . FIG. 8 shows the results of examining the amount of increase in EOT and the amount of B leakage with respect to various heat treatment conditions.

  In order to electrically activate the impurities ion-implanted into the n-type diffusion layer 107 and the p-type diffusion layer 108, the activation annealing treatment at 1025 ° C. for 10 seconds is followed by 10 ° C. at 1050 ° C. for acceleration of B leakage. Second annealing treatment was added. In the experimental result of FIG. 8, the B leakage amount is obtained by measuring the change in the flat band voltage Vfb due to the additional annealing treatment.

  In the lower diagram of FIG. 8, the increase in EOT is maximized under the heat treatment conditions at 850 ° C. for 10 minutes, and an effective film increase is realized. Further, as shown in the upper diagram of FIG. 8, by increasing the temperature of the heat treatment from 850 ° C., the amount of increase in EOT is reduced, but B leakage tends to be suppressed. This is because fluorine injected into the polycrystalline silicon film (gate electrode material) is reduced by outward diffusion, and the acceleration of B diffusion due to the coexistence of fluorine and B in the polycrystalline silicon is suppressed. It is considered to be a body. However, even when the heat treatment is performed at 1000 ° C. for 10 minutes, B leakage is about 2.3 times that of the case where fluorine implantation is not performed.

  From this, it is estimated that even if the excess fluorine in the polycrystalline silicon film is completely expelled, the B leakage may be slightly accelerated by the structural change of fluorine on the SiON gate insulating film 104.

In the case where no heat treatment is performed, B leakage has occurred so much that it does not operate as a pMOS. Therefore, when a large amount of fluorine is implanted so as to increase the film thickness, the heat treatment after the fluorine implantation is essential. That is, for example, T.W. Aoyama et al., Journal of applied physics vol. 77 (1), 1995, pp417, or T.W. As described by Sasaki et al. In Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, pp66 of 2003, a fluorine treatment is performed (ie, a boron heat treatment step). In the method of implanting in the form of BF ₂ ions, it is impossible to achieve both the suppression of B leakage and the increase in the thickness of the SiON gate insulating film 104.

  As shown in FIG. 8, the increase in EOT and the acceleration of B leakage according to the technique of the present invention are generally in a trade-off relationship. However, according to detailed investigations by the inventors, after heat treatment at 1050 ° C. for 10 seconds, 900 ° C. It is known that an EOT film increase and B leakage can be effectively suppressed by applying a heat treatment for 10 minutes, that is, a two-step heat treatment.

  Also, how much B leakage can actually be used is determined by variations in the threshold voltage Vt of the pMOS. That is, B leakage in a range where the variation of the threshold voltage Vt does not increase is allowed. As a result of examining the heat treatment conditions shown in FIG. 8 from this viewpoint, it was found that conditions of 850 ° C. or higher are acceptable. However, allowable heat treatment conditions depend on the plasma nitridation conditions of the SiON gate insulating film and the thermal history of the process flow.

  Next, the influence of the increase in the SiON gate insulating film 104 formed in the pMOS formation region by fluorine implantation on the pMOS performance and the NBTI reliability will be described.

  Here, as heat treatment conditions, 900 ° C. for 10 minutes is used. When the fluorine implantation is not performed, the EOT of the SiON gate insulating film is 1.30 nm, which corresponds to the prior art.

When the fluorine implantation dose is 1 × 10 ¹⁵ / cm ² , the EOT of the SiON gate insulating film 104 increases to 1.35 nm, the on-state current of the pMOS is about 97.5% of the conventional technology, and the pMOS The NBTI lifetime was about 2.2 times that of the prior art. When the fluorine implantation dose is 2 × 10 ¹⁵ / cm ² , the EOT of the SiON gate insulating film 104 is increased to 1.44 nm, the on-current of the pMOS is about 94% of the conventional technology, and the NBTI of the pMOS is increased. The service life is about 7 times that of the conventional technology.

  That is, the technology of the present invention that can extend the NBTI life to 7 times at the expense of only about 6% of the on-current is a great advantage when the performance requirement of the pMOS such as the SRAM circuit in the high-speed operation circuit unit is not high. (In other words, according to the present invention, when only the pMOS SiON gate insulating film 104 constituting the SRAM circuit is increased, the effect of the present invention is further increased). Further, since fluorine is not implanted into the nMOS formation region, it is natural that there is no adverse effect on the nMOS characteristics.

  Here, the SIMS analysis result immediately after fluorine ion implantation and the SIMS analysis result after heat treatment after fluorine ion implantation are shown in FIG. FIG. 10 shows the result of SIMS analysis of the fluorine distribution in the vicinity of the SiON film in a state where heat treatment is performed after fluorine ion implantation. In order to make the distribution in the film thickness direction easy to understand, the distribution is made using a SiON film of about 20 nm thicker than the actual SiON film. In order to show the position of the SiON film, FIG. 10 also shows the oxygen concentration distribution.

  As can be seen from FIGS. 9 and 10, a large amount of fluorine ions are distributed in the gate electrode 106 immediately after fluorine ion implantation (before heat treatment). However, by performing heat treatment after fluorine ion implantation, fluorine ions are redistributed so as to have a distribution peak in the SiON gate insulating film 104.

  Next, the characteristics of a pMOS fabricated by a technique using oxygen ion implantation, which is another technique other than fluorine implantation among the techniques of the present invention, will be described.

When the oxygen ion implantation dose was 2.5 × 10 ¹⁵ / cm ² and the heat treatment after oxygen ion implantation was 1050 ° C. for 30 seconds, the EOT of the SiON gate insulating film 104 increased by 0.08 nm. It is considered that oxygen ions implanted into the polycrystalline silicon film 120 reached the SiON gate insulating film 104 in the pMOS formation region and contributed to the film increase. Also, unlike the case of fluorine ion implantation, B leakage was not accelerated in the case of oxygen ion implantation.

  From the following viewpoint, it is considered that fluorine ion implantation is more practical than oxygen ion implantation.

  That is, in the case of oxygen ion implantation, the sheet resistance of the p + gate electrode 106 in the completed state increased by about 1.7 times. This is presumed to be because some of the implanted oxygen ions remain in the polycrystalline silicon 120 and possibly become fine precipitates of silicon oxide. It is known that high-temperature heat treatment at 1200 ° C. or higher is necessary to completely discharge such silicon oxide precipitates. However, such high temperature heat treatment cannot be applied in the actual CMOS device fabrication flow. Therefore, the pMOS must be used in the form of oxygen precipitates in the polycrystalline silicon film 120, and there remains anxiety for use in a large-scale integrated circuit.

  In addition, oxygen ion implantation is mainly used by manufacturers that manufacture SOI (Silicon on Insulator) wafers called SIMOX (Separation by Implanted Oxygen) wafers, but is rarely used by device manufacturers. Therefore, the technique using oxygen ion implantation among the techniques of the present invention is expected to require a new investment for device manufacturers in many cases, and the technique using fluorine ion implantation is easier to implement. it is conceivable that.

  As described above, in the semiconductor device according to the present embodiment, the SiON gate insulating film 104 constituting the pMOS contains fluorine, and due to the fluorine, the SiON gate insulating film 103 constituting the nMOS is used. Further, the SiON gate insulating film 104 is increased. Therefore, as described above, the NBTI lifetime of the pMOS can be improved.

  On the other hand, the SiON gate insulating film 103 does not contain fluorine, so that no film is increased, and there is no adverse effect on the nMOS characteristics. Therefore, high performance of the nMOS transistor can be maintained regardless of the increase of the SiON gate insulating film 104.

  That is, it is possible to provide a semiconductor device that can achieve both improvement in the NBTI lifetime of the pMOS and high performance of the nMOS.

  From the viewpoint of electrical characteristics (interface state density), the thickness of the SiON gate insulating film 104 is less than 16% thicker than the thickness of the SiON gate insulating film 103 after the film is increased (that is, the finished product). It is desirable that

  It can be said that the technique according to the present embodiment brings a great advantage when the performance requirement of the pMOS such as the SRAM circuit is not high in the high-speed operation circuit unit. In other words, according to the present invention, when only the pMOS SiON gate insulating film 104 constituting the SRAM circuit is increased, the effect of the present invention is further enhanced.

  By the way, as a method of forming the gate insulating films 103 and 104 having different thicknesses on the same semiconductor substrate, a method of combining photolithography and wet etching can be considered. However, this method is not suitable for creating a fine region of the order of 100 nm such as an nMOS or pMOS in an SRAM memory cell or an nMOS or pMOS in a high-speed logic circuit. This is because the resist material used for microfabrication lithography has insufficient wet etching resistance.

  As another method for forming the gate insulating films 103 and 104 having different film thicknesses on the same semiconductor substrate, for example, there is a technique disclosed in Patent Document 1. In the technique related to Patent Document 1, gate insulating films having different thicknesses are formed by implanting ions such as fluorine into a semiconductor substrate before a gate oxidation step and using an improvement in oxidation rate due to ion implantation damage. is doing. However, as a result of investigations by the inventors, it has been found that a gate insulating film formed by using this method has many interface states and is extremely inferior in terms of electrical characteristics and cannot be put into practical use.

As yet another method for forming gate insulating films 103 and 104 having different thicknesses on the same semiconductor substrate, a polycrystalline silicon film is deposited on the gate oxide film, and then fluorine is ion-implanted into the polycrystalline silicon film. Also, a method of performing heat treatment after introducing impurity ions such as B into the gate electrode (polycrystalline silicon film) continuously or after implanting boron and fluorine simultaneously in the form of BF ₂ ions is also considered. It is done.

  However, when the sequence of fluorine ion introduction, introduction of other impurity ions, and heat treatment is performed, the diffusion of B or the like from the gate electrode to the silicon substrate is dramatically accelerated by the introduction of fluorine ions.

  Therefore, as described above, in the method of manufacturing a semiconductor device according to this embodiment, after introducing fluorine ions or oxygen ions, heat treatment is performed, and after the heat treatment, predetermined impurity ions and the like are implanted.

  Therefore, in this method, the SiON gate insulating film 104 is increased without performing the wet etching process and without changing the film thickness of the SiON gate insulating film 103. That is, in the method of the present invention, the gate insulating film 103 that does not increase the thickness constituting the nMOS and the gate insulating film 104 that increases the thickness that constitutes the pMOS are separately formed by fluorine ion implantation using the resist 125 as a mask or Oxygen ion implantation is used.

  Therefore, the method according to the present invention can be applied to a fine region of 100 nm order such as an nMOS in a SRAM memory cell and a pMOS with an increased gate insulating film, or an nMOS in a high-speed logic circuit and a pMOS with an increased gate insulating film. Suitable for making properly.

  Further, since the SiON gate insulating film 104 can be increased without damaging the SiON gate insulating film 104, it is possible to prevent the electrical characteristics of the pMOS from being significantly deteriorated.

  Further, in the method according to the present invention, as described above, the procedures of fluorine ion implantation or oxygen ion, heat treatment, and other impurity ions are performed. Therefore, as shown in the experimental result (FIG. 8), diffusion of impurities implanted into the gate electrode 106 into the silicon substrate 101 can be suppressed while improving the NBTI characteristics of the pMOS.

  Note that when B is introduced as impurity ions into the gate electrode 106, diffusion into the silicon substrate 101 becomes more problematic. In the present invention, as shown in FIG. 8, the diffusion of B is also dramatically suppressed. (Therefore, more B remains in the gate electrode 106 of the finished pMOS).

  As described above, the semiconductor device manufacturing method according to the present invention is a semiconductor device in which only the SiON gate insulating film 104 constituting the pMOS is increased by a simpler method without significantly adversely affecting the performance of the semiconductor device. Can be manufactured. As described above, the non-increased gate insulating film 103 constituting the nMOS and the increased gate insulating film 104 constituting the pMOS can be separately formed in the fine region, and the gate electrode 106 has an impurity as an impurity. Since the diffusion of introduced B or the like into the silicon substrate 101 can be further suppressed, the method according to the present invention is more effective.

  Further, in the method of manufacturing a semiconductor device according to this embodiment, the fluorine ions and the like reach the SiON gate insulating film 104 by a heat treatment performed after the implantation process of fluorine ions and the like. Therefore, it is possible to more effectively increase the thickness of the SiON gate insulating film 104 due to the arrival of the fluorine ions or the like.

<Embodiment 2>
In the first embodiment, an nMOS and a pMOS are simultaneously formed on the same silicon substrate 101, and each forms a single type of gate insulating film (however, the thickness of the gate insulating film 104 constituting the pMOS and the nMOS are formed. The thickness of the gate insulating film 103 is different from that of the gate insulating film 103, and the element formation of the high-speed operation circuit portion of the CMOS integrated circuit is described in mind.

  The description of the first embodiment is for the purpose of improving the outlook, and is not realistic in view of manufacturing an actual advanced CMOS integrated circuit. Actually, it is necessary to form an nMOS and a pMOS having a thickness larger than that of the high-speed operation circuit portion on the same semiconductor substrate, and combine them to constitute an integrated circuit.

  For example, when a high-speed operation circuit element is operated at an input / output voltage of 1V, an element operating at 2.5V is used for the input / output circuit, or for two types of input / output circuits of 3.3V and 1.8V. An element may be prepared. That is, apart from the high-speed operation circuit element portion, nMOS and pMOS having a thick gate insulating film of one or more levels are required. That is, the high-speed operation circuit portion has a gate insulating film to which a voltage lower than that of the input / output circuit portion is applied and is thinner than the input / output circuit portion.

  In addition to digital circuits such as a high-speed operation circuit section and an input / output circuit section, there is an increasing number of cases in which an analog circuit is required to be formed on the same semiconductor substrate. A thick gate insulating film is also generally used.

  In view of the above, an embodiment in which an element having a gate insulating film thicker than a gate insulating film formed in a high-speed operation circuit portion is formed over the same semiconductor substrate will be described in this embodiment. Although the case where one kind of thicker gate insulating film formed in the input / output circuit portion is prepared will be described, two or more kinds of film thicknesses can be prepared, and the basic method is already known.

  Note that, as the gate insulating film formed in the high-speed operation circuit, at least the gate insulating film 103 which does not increase the film constituting the nMOS and the gate insulating film which increases the film constituting the pMOS described in the first embodiment. 104.

  In FIG. 11, on the silicon substrate (semiconductor substrate) 41, the nMOS formation region (hereinafter referred to as a core nMOS formation region) and the pMOS formation region (hereinafter referred to as a core operation region) of the high-speed operation circuit which are separated from each other by the element isolation trench 42. The core pMOS forming region), the nMOS forming region of the input / output circuit (hereinafter referred to as I / OnMOS forming region), and the pMOS forming region of the input / output circuit (hereinafter referred to as I / OpMOS forming region) The surface of the silicon substrate 41 is exposed by the cleaning process and the dissolution process using dilute hydrofluoric acid. Then, a silicon oxide film 43 of, eg, a 7.5 nm-thickness is formed on the surface of the silicon substrate 41 by heat treatment in an atmosphere containing oxygen (FIG. 11).

  A resist 44 is applied over the entire surface of the silicon substrate 41 on which the silicon oxide film 43 is formed, and the resist 44 in the core nMOS formation region and the core pMOS formation region is selectively removed by ordinary photolithography (FIG. 12). .

  Thereafter, the silicon oxide film 43 on the core nMOS formation region and the core pMOS formation region is removed by dissolution treatment in diluted hydrofluoric acid, and the surface of the silicon substrate 41 is exposed from the removed region. Subsequently, the resist 44 is completely removed by a dissolution process using an aqueous solution of sulfuric acid and hydrogen peroxide solution (FIG. 13), and an aqueous solution of ammonia and hydrogen peroxide solution is applied to the silicon substrate 41 shown in FIG. The cleaning process is continued using an aqueous solution of hydrochloric acid and hydrogen peroxide.

Through the series of cleaning processes so far, the film thickness of the silicon oxide film 43 on the I / OnMOS formation region and the I / OpMOS formation region is reduced from 7.5 nm to 7.2 nm. Then, a silicon oxide film having a thickness of 1.4 nm, for example, is formed in the core nMOS formation region and the core pMOS formation region by heat treatment in an atmosphere containing oxygen. Thereafter, by introducing nitrogen by plasma nitriding, a SiON gate insulating film 45 is formed in the core nMOS forming region and the core pMOS forming region, and a SiON gate insulating film 46 is formed in the I / OnMOS forming region and the I / OpMOS forming region. Is formed (FIG. 14).

  The respective equivalent oxide film thicknesses are 1.24 nm for the SiON gate insulating film 45 in the core nMOS formation region and the core pMOS formation region, and 7 for the SiON gate insulating film 46 in the I / OnMOS formation region and the I / OpMOS formation region. It became 3 nm.

  By combining the above gate insulating film formation procedure and the method of manufacturing the semiconductor device described in the first embodiment for the core nMOS formation region and the core pMOS formation region, the nMOS, pMOS, and input / output forming the high-speed operation circuit portion An nMOS and a pMOS that form a circuit can be formed on the same silicon substrate 41.

  Here, as described above, the thickness of the gate insulating film 46 formed in the I / O formation region is generally larger than the thickness of the gate insulating film 45 formed in the core formation region. Further, since the method described in the first embodiment is applied to the core formation region (high-speed operation circuit portion), a gate insulating film (which can be grasped as the first region) formed in the core nMOS formation region ( The thickness of the gate insulating film 45 (which can be grasped as the second gate insulating film) 45B formed in the core pMOS formation region (which can be grasped as the second region) is larger than the film thickness of 45a which can be grasped as the first gate insulating film). The film thickness is thicker (the film thickness difference is not clearly shown in FIG. 14).

  It is obvious that the pMOS (core pMOS) of the high-speed operation circuit section formed by the above procedure has the effects described in the first embodiment.

  In the method of manufacturing the semiconductor device according to the present embodiment (a semiconductor device including an input / output circuit section having a MOS transistor and a high-speed operation circuit section having a pMOS and an nMOS), the SiON gate insulating film 45 (SiON gate insulating film) is used. Before the step of forming the first gate insulating film in relation to the film 46, the SiON gate insulating film 46 (on the surface of the silicon substrate 41 in the I / O forming region (MOS transistor forming region)) A step of forming a second gate insulating film in relation to the SiON gate insulating film 45).

  Then, a register is formed so as to cover the I / O formation region in addition to the core nMOS formation region, and a fluorine ion or oxygen ion implantation process is performed using the resist as a mask.

  Thereby, by adopting the method according to the present embodiment, a high-speed operation circuit and an input / output circuit having a gate insulating film thicker than the gate insulating film formed in the high-speed operation circuit, In a high-speed operation circuit, a more practical semiconductor device having an nMOS having a gate insulating film that has not been increased and a pMOS having a gate insulating film that has been increased can be manufactured.

  Since fluorine ion implantation or oxygen ion implantation for increasing the thickness of the SiON gate insulating film 45a is performed by a combination of photolithography and ion implantation, it is not limited to the example described in the first embodiment and is introduced in a desired range. be able to. For example, not only the SiON gate insulating film 45a constituting the core pMOS but also the SiON gate insulating film 46 constituting the I / OpMOS can be subjected to the film increasing process. As described, the on-current of the pMOS is slightly reduced, but the NBTI lifetime can be dramatically improved.

  The high-speed operation circuit portion is formed in a predetermined region (which can be grasped as a third region) on the surface of the silicon substrate (semiconductor substrate) 41, fluorine is not introduced, and the SiON gate insulating film 45a (first region) Another gate insulating film (which can be grasped as a third gate insulating film) having a film thickness equivalent to that of the other gate insulating film, and a gate electrode (third electrode) formed on the surface of the other gate insulating film And a pair of p-type impurity diffusion regions formed in the surface of the silicon substrate with the silicon substrate facing the other gate electrode interposed therebetween may be provided.

  In other words, among the multi-core pMOSs formed on the silicon substrate 41, only the pMOS constituting the SRAM is subjected to the film increasing process, and the SiON gate insulating film of the pMOS in the high-speed logic circuit portion having a high on-current requirement value is increased. There is also an option of not letting it go. Thereby, a more practical semiconductor device can be provided.

  In addition, one large-scale integrated circuit has a transistor to which a voltage is applied in various patterns during operation, and is used so that a state in which a negative voltage is applied to the gate electrode lasts for a long time. PMOS) can be subjected to the film-increasing treatment (described in the first embodiment) of the present invention. Note that the pMOS transistor in the 6-transistor type SRAM may be used for a long time in a state where a negative voltage is applied to the gate voltage, and from the viewpoint of the NBTI life, the above-described film increasing process is more necessary.

<Embodiment 3>
In the present embodiment, the case where the formation of the SiON gate insulating films 103 and 104 is performed by another method will be described based on the example described in the first embodiment.

  Specifically, contrary to the general method of forming a silicon oxide film and then converting it to a SiON film by plasma nitriding treatment, the silicon nitride film is formed and then oxidized to give SiON This is a method of converting into a film. The SiON gate insulating film produced as the latter method is, for example, S.I. As disclosed in Tsukikawa et al. In Symposium on VLSI Technology Digest of Technical Papers 2002, pp202, it has a high nitrogen concentration and leaks into the substrate of B, which is included as an impurity in the gate leakage current characteristics and gate electrode. It is known to be excellent in resistance. Hereinafter, a method for forming a SiON gate insulating film according to the present embodiment will be briefly described.

  In the nMOS and pMOS formation method described in the first embodiment, the SiON gate insulating film 103 in the nMOS formation region and the SiON gate insulating film 104 in the pMOS formation region are formed as follows.

  A silicon nitride film with a thickness of about 0.8 nm is formed by plasma nitriding, and this is heat-treated at 1000 ° C. in an atmosphere containing oxygen. Even when this method is used, the SiON gate insulating film 104 in the pMOS formation region can be selectively increased by the method using fluorine implantation in the technique of the present invention.

  The relationship between the equivalent oxide thickness (EOT) of the SiON gate insulating film 104 in the pMOS formation region and the amount of implanted fluorine is shown in FIG. The data shown in FIG. 15 relates to a sample using 850 ° C. for 10 minutes as a heat treatment condition after fluorine implantation.

  Although the amount of film increase is smaller than the result in the case of the first embodiment (result shown in FIG. 7), fluorine implantation is performed on the SiON gate insulating film produced by the method according to the present embodiment. It can be seen that the EOT of the SiON gate insulating film is increased by performing.

The EOT of the SiON gate insulating film (base SiON film shown in FIG. 15) without fluorine implantation is 1.11 nm, which corresponds to the prior art. When the fluorine implantation dose is 1 × 10 ¹⁵ / cm ² , the EOT of the SiON gate insulating film increases to 1.15 nm, the on-current is about 98.5% of the conventional technology, and the NBTI life is about three times as long. became. When the fluorine implantation dose is 2 × 10 ¹⁵ / cm ² , the EOT of the SiON gate insulating film increases to 1.21 nm, the on-current is about 97.5% of the conventional technology, and the NBTI life is about 10%. Doubled. As can be seen from the experimental results, the NBTI lifetime can be extended by a factor of 10 at the expense of only 2.5% on-current.

<Embodiment 4>
In this embodiment, the case where the entire region of the gate electrodes 105 and 106 in a completed state is made of nickel silicide instead of polycrystalline silicon is described based on the example described in Embodiment 1. Here, nickel silicide is used as an example of a metal silicide used as a gate electrode material, but silicides such as cobalt and titanium can also be used, and multi-component materials such as adding cobalt to nickel silicide are also considered. (That is, mention is made of the case where the gate electrode is a full silicide film).

  Since the process up to selectively increasing the thickness of the SiON gate insulating film 104 in the pMOS formation region using the implantation of fluorine or the like into the polycrystalline silicon film and the subsequent heat treatment is the same as that in the first embodiment, This will be described with reference to process cross-sectional views.

  Referring to FIG. 16, by the method described in the first embodiment, element isolation trench 102, SiON gate insulating film 103 in the nMOS forming region, SiON gate insulating film 104 in the pMOS forming region, A polycrystalline silicon film 605 is formed. Here, the polycrystalline silicon film 605 is not patterned into a gate electrode structure as shown in FIG. 16 at this stage.

After the formation of the polycrystalline silicon film 605, the SiON gate insulating film 104 in the pMOS formation region is selectively increased by fluorine ion implantation using the technique of the present invention (that is, the technique described in the first embodiment). (See FIG. 16). Further, an ion implantation process is performed on the polycrystalline silicon film 605 in the nMOS formation region under the conditions of a P ion concentration of 8 × 10 ¹⁵ / cm ² and an acceleration voltage of 15 kV. Further, an ion implantation process is performed on the polycrystalline silicon film 605 in the pMOS formation region under the conditions of a B ion concentration of 5 × 10 ¹⁵ / cm ² and an acceleration voltage of ² kV.

  Next, a silicon nitride film 606 having a thickness of 60 nm is deposited using dichlorosilane and ammonia gas by a known chemical vapor deposition method. Thereafter, the silicon nitride film 606 and the polycrystalline silicon film 605 are patterned into desired dimensions (shapes) using photolithography and dry etching (see FIG. 16).

Next, the nMOS forming area, the As ion concentration 3 × 10 ¹⁴ / cm ^2, the ion implanted at an acceleration voltage of 5 kV, with respect to the pMOS forming region, B ions concentration 3 × 10 ¹⁴ / cm ^2. Ion implantation is performed under the condition of an acceleration voltage of 1 kV. Low concentration regions of the n-type diffusion layer 107 and the p-type diffusion layer 108 are formed by the respective ion implantation processes (see FIG. 16).

  Next, a 100 nm-thickness silicon oxide film is formed using tetraethoxysilane (Si (OC2H5) 4) by chemical vapor deposition, and then the silicon oxide film is anisotropically dry etched. Sidewalls 109 made of silicon oxide are formed (see FIG. 16).

Thereafter, As ions are implanted into the nMOS formation region at a concentration of 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 10 kV, and B ions are implanted into the pMOS formation region at a concentration of 5 × 10 ¹⁵ / cm ^2. Then, ions are implanted under the condition of an acceleration voltage of 3 kV. By the respective ion implantation processes, high concentration regions of the n-type diffusion layer 107 and the p-type diffusion layer 108 are formed. That is, as shown in FIG. 16, the n-type diffusion layer 107 and the p-type diffusion layer 108 have a two-stage configuration of a low concentration region and a high concentration region. Next, heat treatment is performed at 1025 ° C. for 10 seconds to electrically activate impurities implanted into the n-type diffusion layer 107 and the p-type diffusion layer 608.

  After performing the above heat treatment, a silicon oxide film having a thickness of 300 nm is deposited by plasma chemical vapor deposition using tetraethoxysilane (Si (OC2H5) 4), and this is planarized by chemical mechanical polishing for interlayer insulation. A film 110 is formed (see FIG. 16). In the chemical mechanical polishing process, a silicon nitride film 606 is used as a stopper for stopping polishing.

  Next, the silicon nitride film 606 is selectively removed using a phosphoric acid (H 3 PO 4) aqueous solution, and the polycrystalline silicon film 605 is partially removed by dry etching and dissolution treatment using an aqueous solution of ammonia and hydrogen peroxide. And the thickness of the polycrystalline silicon film 605 is reduced to 75 nm (see FIG. 17).

  Subsequently, a nickel film 611 is deposited by sputtering (see FIG. 17), and heat treatment is performed in a nitrogen atmosphere at 350 ° C. to cause the nickel film 611 to react with the polycrystalline silicon film 605. After removing unnecessary nickel film 611 by dissolution treatment with an aqueous solution in which phosphoric acid, nitric acid (HN3), acetic acid (CH3COOH), and hydrogen peroxide water are mixed, heat treatment is performed in a nitrogen atmosphere at 550 ° C. The entire region of the silicon film 605 is converted to nickel silicide (full silicidation).

  Thus, as shown in FIG. 18, a nickel silicide gate electrode 612 containing phosphorus is formed in the nMOS formation region, and a nickel silicide gate electrode 613 containing boron is formed in the pMOS formation region. Here, as described above, each of the gate electrodes 612 and 613 is called full silicide because the entire region is substantially composed of nickel silicide.

  Thereafter, a silicon oxide film is deposited by plasma chemical vapor deposition and chemical mechanical polishing is performed to increase the thickness of the interlayer insulating film 110 to 600 nm. Thereafter, a contact hole is opened in the interlayer insulating film 110 using photolithography and dry etching. Thereafter, tungsten is deposited into the contact hole by chemical vapor deposition and sputtering, and this is processed by photolithography and dry etching to form the wiring 111 (see FIG. 18).

  Through the above steps, an nMOS and a pMOS using nickel silicide as a gate electrode are completed on the same substrate. By the technique of the present invention, the SiON gate insulating film 104 in the pMOS forming region is replaced by the SiON gate insulating film 103 in the nMOS forming region. The finish is also thick. The actual formation of advanced CMOS integrated circuits requires steps such as formation of sidewalls with a more complicated structure, formation of metal silicide on the surface of the diffusion layer, and formation of multilayer copper wiring, but are omitted here. .

  When a SiON film is used as a gate insulating film and nickel silicide is used as a gate electrode, it is known that boron (B) addition is effective as a means for bringing the work function of the gate electrode of the pMOS close to a desired value. Therefore, as in the case of using the polycrystalline silicon gate electrode, the high temperature heat treatment is performed in a state where boron (B) is added to the polycrystalline silicon film 605, and then converted into nickel silicide. Even when a full silicide gate electrode made of is used, suppression of B leakage to the silicon substrate 101 in an intermediate process is equally important as when a polycrystalline silicon gate electrode is used.

  Therefore, when a full silicide film is used as a gate electrode and fluorine implantation is used in a predetermined region, it is not realistic to perform boron (B) implantation or BF2 ion implantation following fluorine implantation. . As in the technique of the present invention (that is, as described in the embodiment), it is possible to suppress the B leakage by removing the excess boron (B) by performing heat treatment after the fluorine implantation and before introducing boron (B). Essential on. Furthermore, since the electric field is directly applied in the case where the full silicide film is used as the gate electrode than in the case where the polysilicon film is used as the gate electrode, there is a greater concern about NBTI reliability. . Therefore, the necessity for the effect described in the first embodiment is increased.

  Further, in this embodiment, the SiON gate insulating film 104 in the pMOS formation region is increased by using fluorine implantation into the polycrystalline silicon film 605. Therefore, the effect resulting from the film increase described in the first embodiment is maintained. Since the effect of increasing the gate insulating film is not affected by whether or not the polycrystalline silicon film 605 is converted to nickel silicide in the process after the film increase, it can be said that it is a natural result.

FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. 4 is a cross-sectional view showing a configuration of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to Embodiment 1. FIG. It is a figure which shows the experimental data which investigated the relationship between the amount of fluorine injection | pouring and the increase amount of an oxide film equivalent film thickness at the time of performing the method of Embodiment 1. It is a figure which shows the experimental data which investigated the effect by the heat processing after fluorine injection | pouring. It is a figure which shows the experimental data which investigated the density | concentration distribution of the fluorine in a gate electrode, a gate insulating film, etc. It is a figure which shows the experimental data which investigated the density | concentration distribution of the fluorine in a gate electrode, a gate insulating film, etc. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. It is a figure which shows the experimental data which investigated the relationship between the fluorine implantation amount at the time of performing the method of Embodiment 3, and the increase amount of an oxide film equivalent film thickness. FIG. 10 is a process cross-sectional view for explaining the method of manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a process cross-sectional view for explaining the method of manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a process cross-sectional view for explaining the method of manufacturing the semiconductor device according to the fourth embodiment.

Explanation of symbols

101, 41 silicon substrate, 102, 42 element isolation trench, 103, 104, 45, 46 SiON gate insulating film, 105, 106 gate electrode, 107 n-type diffusion layer, 108 p-type diffusion layer, 109 sidewall, 110 interlayer insulation Film, 111 wiring, 43 silicon oxide film, 605 polycrystalline silicon film, 606 silicon nitride film, 611 nickel film, 612 nickel silicide gate electrode (containing phosphorus), 613 nickel silicide gate electrode (containing boron)

Claims (14)

A semiconductor device comprising: an input / output circuit unit; and a high-speed operation circuit unit having a gate insulating film that is applied with a lower voltage than the input / output circuit unit and is thinner than the input / output circuit unit
The high-speed operation circuit unit includes:
A first gate insulating film formed in a first region on the surface of the semiconductor substrate and into which fluorine is not introduced;
A first gate electrode formed on the surface of the first gate insulating film;
An nMOS transistor having a pair of n-type impurity diffusion regions formed in the semiconductor substrate surface across the semiconductor substrate facing the first gate electrode;
A second gate insulating film formed in a second region on the surface of the semiconductor substrate, having a thickness greater than that of the first gate insulating film, wherein the fluorine is introduced into the film;
A second gate electrode formed on the surface of the second gate insulating film, containing an impurity and containing at least silicon as a component;
A pMOS transistor having a pair of p-type impurity diffusion regions formed in the surface of the semiconductor substrate across the semiconductor substrate facing the second gate electrode.
Semiconductor device. The second gate insulating film is a SiON film;
The film thickness of the second gate insulating film is less than 16% thicker than the film thickness of the first gate insulating film.
The semiconductor device according to claim 1. As the impurity contained in the second gate electrode, at least boron is contained,
The semiconductor device according to claim 1. The high-speed operation circuit unit includes:
A third gate insulating film formed in a third region on the surface of the semiconductor substrate and having a thickness equivalent to that of the first gate insulating film without introduction of fluorine; and the third gate insulating film A pMOS transistor having a third gate electrode formed on the surface and a pair of p-type impurity diffusion regions formed in the surface of the semiconductor substrate across the semiconductor substrate facing the third gate electrode Further equipped with
The semiconductor device according to claim 1. The high-speed operation circuit unit includes an SRAM circuit unit,
The pMOS transistor formed in the second region is used only for the SRAM circuit portion.
The semiconductor device according to claim 4. The second gate electrode is
In the completed state, the entire area is metal silicide,
6. The semiconductor device according to any one of claims 1 to 5, wherein: In a method for manufacturing a semiconductor device including a pMOS transistor and an nMOS transistor,
Forming a gate electrode material on the semiconductor substrate surface via a first gate insulating film;
Forming a mask covering the surface of the nMOS transistor formation region and opening at least a part of the surface of the pMOS transistor formation region;
After the mask formation, implanting fluorine into the upper surface of the semiconductor substrate, introducing the fluorine into at least a part of the gate electrode material in the pMOS transistor formation region, and performing a heat treatment after the fluorine introduction;
A step of introducing impurities into the gate electrode material in the pMOS transistor formation region after the heat treatment step;
A method for manufacturing a semiconductor device. The impurity introduced into the second gate electrode contains at least boron.
8. A method of manufacturing a semiconductor device according to claim 7, wherein: Causing the fluorine to reach the first gate insulating film by the heat treatment;
9. The method of manufacturing a semiconductor device according to claim 7, wherein the method is a semiconductor device manufacturing method. The semiconductor device includes:
An input / output circuit having a MOS transistor;
A voltage lower than that of the input / output circuit unit is applied, and a high-speed operation circuit unit including the pMOS transistor and the nMOS transistor is provided.
Before the step of forming the first gate insulating film, comprising the step of forming the second gate insulating film on the surface of the semiconductor substrate in the MOS transistor formation region,
The mask is formed so as to cover the surface of the MOS transistor.
The method for manufacturing a semiconductor device according to claim 7, wherein the method is a semiconductor device manufacturing method. In a method for manufacturing a semiconductor device including a pMOS transistor and an nMOS transistor,
Forming a gate electrode material on the semiconductor substrate surface via a first gate insulating film;
Forming a mask covering the surface of the nMOS transistor formation region and opening at least a part of the surface of the pMOS transistor formation region;
After the mask is formed, oxygen is implanted into the upper surface of the semiconductor substrate, the oxygen is introduced into at least a part of the gate electrode material in the pMOS transistor formation region, and a heat treatment is performed after the oxygen introduction;
A step of introducing impurities into the gate electrode material in the pMOS transistor formation region after the heat treatment step;
A method for manufacturing a semiconductor device. The impurity introduced into the second gate electrode contains at least boron.
The method of manufacturing a semiconductor device according to claim 11, wherein: Causing the oxygen to reach the first gate insulating film by the heat treatment;
13. The method for manufacturing a semiconductor device according to claim 11, wherein the semiconductor device is manufactured. The semiconductor device includes:
An input / output circuit having a MOS transistor;
A voltage lower than that of the input / output circuit unit is applied, and a high-speed operation circuit unit including the pMOS transistor and the nMOS transistor is provided.
Before the step of forming the first gate insulating film, comprising the step of forming the second gate insulating film on the surface of the semiconductor substrate in the MOS transistor formation region,
The mask is formed so as to cover the surface of the MOS transistor.
The method for manufacturing a semiconductor device according to claim 11, wherein the method is a semiconductor device manufacturing method.

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