JP2009272368A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control the effective work function of an MIS transistor comprising a metal gate electrode using a TaC<SB>x</SB>film on an Hf-O-based insulating film. <P>SOLUTION: A gate insulating film 2 is formed from a silicon layer 1c side of an SOI substrate 1. Then, TaC<SB>x</SB>film is deposited by a room temperature sputtering method on the gate insulating film 2. A metal gate electrode 3 constituted by forming the TaC<SB>x</SB>film thereon. Then, a silicon film in an amorphous state is formed on the metal gate electrode 3, and then the metal gate electrode 3 is subjected to heat treatment. Then, the silicon film is removed, and then oxygen is added to the metal gate electrode 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and in particular, a semiconductor device in which a CMIS (Complementary MIS) element is configured by an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a p-channel MISFET using metal as a gate electrode material. It is related to technology effective when applied to.

  In the CMIS element, in order to realize a low threshold voltage in both an n-channel MISFET (hereinafter referred to as an n-type MIS transistor) and a p-channel MISFET (hereinafter referred to as a p-type MIS transistor), different work functions are used. So-called dual gate formation is performed in which a gate electrode is formed using a material having (Fermi level in the case of polysilicon). For example, by introducing an n-type impurity and a p-type impurity into a polysilicon film forming the gate electrodes of an n-type MIS transistor and a p-type MIS transistor, respectively, the work of the gate electrode material of the n-type MIS transistor is achieved. The threshold voltage is lowered by setting the function (Fermi level) near the silicon conductor and the work function (Fermi level) of the gate electrode material of the p-type MIS transistor near the valence band of silicon. ing.

  In recent years, with the miniaturization of MIS transistors constituting a semiconductor integrated circuit, the gate oxide film has been rapidly thinned. For this reason, when a voltage is applied to the polysilicon gate electrode in order to turn on the MIS transistor, the influence of depletion occurring in the gate electrode near the gate oxide film interface becomes more prominent. As a result of the apparent increase in thickness, it has become difficult to ensure on-current, and the operating speed of the MIS transistor has been significantly reduced.

  Further, when the thickness of the gate oxide film is reduced, electrons are allowed to pass through the gate oxide film due to a quantum effect called direct tunneling, so that a leakage current increases. Further, in the p-type MIS transistor, boron in the gate electrode (polycrystalline silicon film) diffuses into the semiconductor substrate through the gate oxide film, and the threshold voltage fluctuates in order to increase the impurity concentration in the channel region.

  Therefore, studies are being made to replace the gate insulating film material from silicon oxide with an insulating film having a higher dielectric constant (high dielectric film, high-k film) and the gate electrode material from polysilicon to metal or metal silicide. ing.

  This is because, when the gate insulating film is composed of a high dielectric film, the actual physical film thickness (dielectric constant of the high dielectric film / dielectric constant of the silicon oxide film) is obtained even if the silicon oxide film thickness conversion capacity is the same. This is because the leakage current can be reduced as a result. As high dielectric film materials, various metal oxides such as Hf (hafnium) insulating films and Zr (zirconium) insulating films have been studied. In addition, by forming the gate electrode with a material that does not contain polysilicon, problems such as the reduction of on-current due to the influence of depletion and the leakage of boron from the gate electrode to the substrate can be avoided.

  In R. Mitsuhashi et al., ISAGST, 2007 (Non-patent Document 1), the nitrogen concentration of the metal gate electrode on HfSiO (N) is 15 at. It is described that an FET having an effective work function of about 4.7 eV is realized by using% TaCN.

Further, VSChang et al., IEDM, 2007, p.535. (Non-patent Document 2) discloses that the nitrogen concentration of the metal gate electrode on HfO ₂ is 8 at. It is described that an FET having an effective work function of about 4.8 eV is realized by using% TaCN.
R. Mitsuhashi et al., ISAGST, 2007 VSChang et al., IEDM, 2007, p.535.

The effective work function of a MIS transistor in which a TaC _x gate electrode is provided on an Hf—O-based insulating film composed of Hf—O such as HfSiO (N) and HfO ₂ is obtained by adding N (nitrogen). The function can be changed. However, when forming the TaCN gate electrode with the addition of N to the TaC _x, N is diffused from TaCN to Hf-O-based insulating film by high-temperature heat treatment activation annealing, Hf-N with respect to Hf-O bond The bond has conductivity or becomes a defect, and there is a concern that reliability as a gate insulating film is lowered.

An object of the present invention is to provide a technique capable of controlling the effective work function of a MIS transistor having a metal gate electrode using a TaC _x film on a Hf—O-based insulating film.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

In one embodiment of the present invention, a metal gate electrode is formed by adding oxygen to TaC _x by heat treatment at a temperature lower than the temperature for activation.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

According to this embodiment, the effective work function of the MIS transistor can be controlled by changing the oxygen concentration in TaC _x .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof may be omitted.

(Embodiment 1)
A method for manufacturing a semiconductor device having a MIS transistor provided with a TaC _x electrode, which is a metal carbide having conductivity, as a metal gate electrode on the Hf—O-based insulating film in the present embodiment will be described with reference to the drawings. First, as shown in FIG. 1, for example, an FD (Full Depletion) -SOI (Silicon On Insulator) substrate (hereinafter referred to as an SOI substrate) 1 which is a semiconductor substrate is prepared. The SOI substrate 1 includes a silicon layer (also referred to as an SOI layer) 1c on a silicon oxide layer 1b provided on a support substrate 1a. Note that a single crystal silicon substrate or the like may be used as the semiconductor substrate.

In this embodiment mode, FD-SOI is used as the semiconductor substrate. The FD-SOI can partition the region depleted, so it is possible to easily control the threshold voltage, controlling the effective work function of the MIS transistor having a metal gate electrode using TaC _x Suitable for

Subsequently, as shown in FIG. 2, a gate insulating film 2 is formed from the silicon layer 1 c side of the SOI substrate 1. Specifically, a silicon oxide film 2a having a thickness of about 2 to 10 nm is deposited on the silicon layer 1c by, for example, a CVD (Chemical Vapor Deposition) method, and, for example, H ₂ O gas and Hf source of TDMAH are deposited on the silicon oxide film 2a. After depositing a hafnium oxide film 2b having a thickness of about 1 to 8 nm by an ALD (Atomic Layer Deposition) method using AA, an annealing process is performed to form the gate insulating film 2. This annealing treatment is performed, for example, at 800 ° C. for 1 second in an N ₂ atmosphere of 100 Pa.

  In the present embodiment, hafnium oxide is used as the high dielectric film (high-k film) constituting the gate insulating film 2. This hafnium oxide has a higher dielectric constant than silicon oxide film and silicon oxynitride film, so the physical film thickness can be increased by (dielectric constant of hafnium oxide film / dielectric constant of silicon oxide film) times, resulting in leakage current. Can be reduced. For this reason, in order to reduce the leakage current, the hafnium oxide film 2b may be formed on the silicon layer 1c. In this embodiment, hafnium oxide is used as the high dielectric film, but high dielectric films such as hafnium nitride silicate, Hf—Si—O, Hf—Al—O, and Hf—Al—O—N are also used. be able to.

  In the present embodiment, the gate insulating film 2 includes a silicon oxide film 2a provided between the SOI substrate 1 and the hafnium oxide film 2b. Since the effective work function of the MIS transistor increases as the hafnium oxide film 2b provided thereon becomes thinner, the silicon oxide film 2a particularly serves as an offset of the effective work function of the p-type MIS transistor. It is considered a thing.

Subsequently, as shown in FIG. 3, a metal gate electrode 3 is formed on the gate insulating film 2. Specifically, a metal gate electrode 3 is formed by depositing a tantalum carbide (TaC _x ) film of about 5.1 to 18.4 nm by room temperature sputtering. As will be described later, the oxygen concentration in the film changes depending on the thickness of the TaC _x film, and the effective work function of the MIS transistor also changes. For this reason, a TaC _x film having a film thickness that provides a desired effective work function is deposited.

Subsequently, as shown in FIG. 4, after depositing an amorphous silicon film on the metal gate electrode 3, the amorphous silicon film is polycrystallized by annealing to form a silicon film 4. Specifically, first, an amorphous silicon film having a thickness of about 21 nm is deposited by a room temperature sputtering method, and annealed to be polycrystallized to form a silicon film 4. This annealing process is performed, for example, at 600 ° C. for 5 minutes in an N ₂ atmosphere of 100 atm. Thereafter, in order to remove the oxide on the surface of the silicon film 4 formed by the annealing treatment, the silicon film 4 is removed by a developer after performing 1% hydrofluoric acid treatment.

Since the TaC _x film as deposited by the room temperature sputtering method in the previous step is not structurally stable, it is necessary to stabilize the structure and recover damage during film formation. Therefore, in the present embodiment, heat treatment is performed to stabilize the structure of the TaC _x film. Specifically, on TaC _x film, to prevent damage due to heat, after depositing a silicon film in an amorphous state as a protective film for preventing the oxidation of TaC _x film is annealed. If a polycrystalline silicon film is deposited on the TaC _x film instead of an amorphous silicon film, it is considered that the TaC _x film becomes an oxide film due to heat during the deposition and does not have conductivity.

  Subsequently, as shown in FIG. 5, the metal gate electrode 3 is processed. Specifically, gate processing is performed by dry etching the metal gate electrode 3 and the gate insulating film 2 therebelow using a resist film (not shown) formed by photolithography as a mask. Thereafter, the resist film is removed by ashing.

Subsequently, an annealing process is performed to recover defects at the interface between the silicon layer 1c and the silicon oxide film 2a. This annealing treatment is performed, for example, at 400 ° C. for 30 minutes in a 3% H ₂ atmosphere.

Subsequently, oxygen is added to the metal gate electrode 3. In the present embodiment, oxygen is added to the TaC _x film constituting the metal gate electrode 3 by low-temperature oxidation at 400 ° C. in a 20% O ₂ atmosphere.

According to the study of the present inventors, the oxygen concentration in the TaC _x film, as shown in FIG. 6, varies depending on the film thickness, in accordance with TaC _x film thickness decreases, increasing the oxygen concentration in the TaC _x film I understand that In addition, as shown in FIG. 7, it can be seen that the effective work function increases as the oxygen concentration in the TaC _x film increases. This is thought to be due to the fact that Ta in the film is oxidized and the electronegativity is lowered and the effective work function is increased. In the present embodiment, the case where TaC _x is used as the metal carbide having conductivity is described, but Ti, Zr, Hf, V, Nb, Mo, and W having the same electronegativity as Ta are carbonized. Even if any one of TiC _x , ZrC _x , HfC _x , VC _x , NbC _x , MoC _x , and WC _x is used, the same effect is considered to be obtained.

As shown in FIG. 7, the oxygen concentration in the TaC _x film is 0 to 23 at. As the ratio increases to%, the effective work function of the metal gate electrode may also change from 4.4 to 5.2 eV.

Therefore, in the present embodiment, when forming an n-type MIS transistor, the oxygen concentration in the TaC _x film is set to 0 at. % Greater than 5%. % Or less. That is, when forming an n-type MIS transistor, the film thickness of the TaC _x film formed by the low-temperature sputtering method is set to 7 nm to so that the effective work function of the gate electrode material of the n-type MIS transistor is close to the conduction band of silicon. What is necessary is just to be about 18.4 nm. When it is thicker than 18.4 nm, as shown in FIG. 6, it is considered that the TaC _x film on the hafnium oxide film 2b side does not contain oxygen sufficiently. Therefore, the effective work function can be controlled by providing a TaC _x film having a desired oxygen concentration at the interface with the hafnium oxide film 2b (Hf—O-based insulating film).

When forming a p-type MIS transistor, the oxygen concentration in the TaC _x film is set to 9 at. % Or more and 23 at. % Or less. That is, when forming a p-type MIS transistor, the thickness of the TaC _x film formed by low-temperature sputtering is set to 1 to 1 so that the work function of the gate electrode material of the p-type MIS transistor is close to the valence band of silicon. What is necessary is just to be about 5.5 nm.

In this manner, the effective work function of the MIS transistor including the metal gate electrode 3 using the TaC _x film on the hafnium oxide film 2b (Hf—O-based insulating film) can be controlled. When a metal gate electrode is formed by adding nitrogen (N) to TaC _x in order to control the effective work function, N diffuses from TaCN into the Hf-O insulating film by high-temperature heat treatment of activation annealing, It can be considered that the reliability of the gate insulating film is lowered. Therefore, in this embodiment, oxygen is added to the Hf—O-based insulating film constituting the gate insulating film 2 to prevent the reliability of the gate insulating film 2 from being lowered. This is a state in which oxygen is deficient in the formed Hf—O-based insulating film, and oxygen diffused by the addition of oxygen to the metal gate electrode 3 supplies oxygen to the Hf—O-based insulating film, thereby repairing it. It is thought to do. This will be described with reference to FIG.

FIG. 8 is an explanatory diagram showing the relationship _between the flat band voltage V _FB and the silicon oxide equivalent film thickness EOT HfO ₂ in the TaC _x electrode / HfO ₂ / SiO ₂ structure with oxygen added. In FIG. 8, the thickness of SiO ₂ is constant (4 nm), and the thickness of HfO ₂ is a parameter (1 to 8 nm). Also, the flat band voltage capacitance (C) of the MIS capacitor - was calculated from the gate voltage _{(V G)} characteristics. In the capacitance C- gate voltage V _G characteristics, regardless of the oxygen concentration in the TaC _x film, measurements were reproduced by the ideal curve.

As shown in FIG. 8, it can be seen that the flat band voltage V _FB shifts in the positive direction as the oxygen concentration in the TaC _x film increases. This is where the HfO ₂ oxygen is excessive to positive charge deficiency, because positive charge is supplied oxygen from TaC _x film is decreased, because the negative voltage applied to the gate voltage V _G becomes a low voltage It is thought that.

Subsequently, as shown in FIG. 9, after an impurity is implanted into the silicon layer 1 c of the SOI substrate 1, the impurity is diffused by activation annealing (heat treatment) to form a diffusion layer 5 on both sides of the metal gate electrode 3. To do. In this way, a MIS transistor having a metal gate electrode using TaC _x on the Hf—O-based insulating film can be formed. The characteristics of the MIS transistor in this embodiment will be described below with reference to the drawings.

FIG. 10 is an explanatory diagram of a TaC _x / HfO ₂ structure based on an X-ray diffraction pattern using oxygen added to the TaC _x film as a parameter. FIG. 10 shows that the oxygen concentration in the TaC _x film is _{0 to} 12 at. Since no difference is seen in the structure regardless of%, TaC _x to which oxygen is added can be used as the metal gate electrode.

FIG. 11 is an explanatory diagram showing the relationship between the oxygen concentration in the TaC _x film and the film thickness. As can be seen from Figure 11, with an increase of the oxygen concentration in the TaC _x film, it is possible to reduce the resistivity of the TaC _x film.

FIG. 12 is an explanatory diagram of the reliability of an oxygen-added TaC _x electrode by NBTI (Negative Bias Temperature Instability). Here, using the SiO ₂ of 2 nm _HfO 2/2 nm thick thickness as the gate insulating film. FIG. 12 shows that the oxygen concentration in the TaC _x film is 0 at. %, 12 at. % NBTI shows almost no difference, indicating that the oxygen added to the TaC _x electrode does not affect the reliability. That is, the TaC _x film added with oxygen can ensure reliability as a metal gate electrode.

FIG. 13 is an explanatory diagram showing the relationship between the capacitance (C) and the gate voltage (V _G ) of an oxygen-added TaC _x electrode n-type MIS transistor and p-type MIS transistor. Here, using the SiO ₂ of 2 nm _HfO 2/2 nm thick thickness as the gate insulating film. FIG. 13 shows that the oxygen concentration in the TaC _x film is 12 at. %, The capacitances of the storage region and the inversion region are almost the same regardless of the n-type MIS transistor and the p-type MIS transistor, and the gate electrode is not depleted. Thus, an on-current can be secured and the operation speed of the MIS transistor can be maintained.

FIG. 14 is an explanatory diagram showing the relationship between the threshold voltage (V _th ) of the oxygen-added TaC _x electrode n-type MIS transistor and p-type MIS transistor and the oxygen concentration in the TaC _x film. Here, using the SiO ₂ of 2 nm _HfO 2/2 nm thick thickness as the gate insulating film. The threshold voltage _{(V th)} is the drain current _{(I D)} when the drain voltage is 0.1 V - was calculated from the gate voltage _{(V G)} characteristics. FIG. 14 shows that the threshold voltage (V _th ) shifts in the positive direction as the oxygen concentration in the TaC _x film increases regardless of the n-type MIS transistor and the p-type MIS transistor. That is, in the MIS transistor on the HfO ₂ film, the oxygen concentration in the TaC _x film is set to 0 to 12 at. By changing it to%, the threshold voltage (V _th ) can be changed by 0.5 to 0.6 V.

FIG. 15 is an explanatory diagram showing electron mobility and hole mobility with the oxygen concentration in the TaC _x film as a parameter in a MIS transistor using an oxygen-added TaC _x electrode. Here, using the SiO ₂ of 2 nm _HfO 2/2 nm thick thickness as the gate insulating film. FIG. 15 shows that the electron mobility and the hole mobility do not depend on the oxygen concentration in the TaC _x film. For this reason as well, as described with reference to FIG. 13, the on-current can be secured and the operation speed of the MIS transistor can be maintained.

  Thus, according to the semiconductor device of the present embodiment, it is possible to manufacture a semiconductor device including a MIS transistor having excellent transistor characteristics after 32 nm technology.

(Embodiment 2)
In the present embodiment, a semiconductor device having a CMIS element including a TaC _x electrode (metal gate electrode) on an Hf—O-based insulating film will be described with reference to the drawings. FIG. 16 is a cross-sectional view schematically showing a main part of a semiconductor device in which the n-type MIS transistor Qn and the p-type MIS transistor Qp in this embodiment form a CMIS element.

  For example, a p-type well 13 and an n-type well 14 whose periphery is defined by an element isolation region 12 are formed on the main surface of a semiconductor substrate composed of a p-type single crystal silicon substrate 11. An n-type MIS transistor Qn is formed on the p-type well 13, and a p-type MIS transistor Qp is formed on the n-type well 14. In this embodiment, the silicon substrate 11 is used as the semiconductor substrate, but an SOI substrate may be used.

  The n-type MIS transistor Qn includes a gate insulating film 15 formed on the surface of the p-type well 13, an n-type gate electrode 16 formed on the gate insulating film 15, and an n-type formed on the p-type well 13. A diffusion layer (source / drain) 17 is provided. The p-type MIS transistor Qp is formed in the gate insulating film 15 formed on the surface of the n-type well 14, the p-type gate electrode 18 formed on the gate insulating film 15, and the n-type well 14. A p-type diffusion layer (source / drain) 19 is provided.

  A metal wiring 22 is connected to the n-type diffusion layer (source / drain) 17 of the n-type MIS transistor Qn via a plug 21 in a contact hole 20 formed in an interlayer insulating film 23 made of, for example, silicon oxide. ing. Similarly, a metal wiring 22 is connected to the p-type diffusion layer (source / drain) 19 of the p-type MIS transistor Qp through a plug 21 in a contact hole 20 formed in the interlayer insulating film 23.

  The gate insulating film 15 of each of the n-type MIS transistor Qn and the p-type MIS transistor Qp includes a silicon oxide film 15a on the main surface of the silicon substrate 11 and an oxide that is an Hf-O-based insulating film on the silicon oxide film 15a. A hafnium film 15b.

  The n-type gate electrode 16 of the n-type MIS transistor Qn includes a tantalum carbide film 16a (first metal film) doped with oxygen on the hafnium oxide film 15b and conductive polysilicon on the tantalum carbide film 16a. And the film 16b. The p-type gate electrode 18 of the p-type MIS transistor Qp includes a tantalum carbide film 18a (second metal film) doped with oxygen on the hafnium oxide film 15b and conductive polysilicon on the tantalum carbide film 18a. And a film 18b.

In the present embodiment, the oxygen concentration in the tantalum carbide film 16a (first metal film) is lower than the oxygen concentration in the tantalum carbide film 18a (second metal film). Since the effective work function increases as the oxygen concentration in the tantalum carbide (TaC _x ) film increases from FIG. 7 shown in the first embodiment, the oxygen concentration in the tantalum carbide film 16a (first metal film). The n-type gate electrode 16 and the p-type gate electrode 18 are configured so that the oxygen concentration is lower than the oxygen concentration in the tantalum carbide film 18a (second metal film). Thus, by adjusting the oxygen concentration in the tantalum carbide film, the n-type gate electrode 16 and the p-type gate electrode 18 can be formed, and the n-type MIS transistor Qn using a single metal gate electrode material and A CMIS element can be constituted by the p-type MIS transistor Qp.

  Further, in the n-type gate electrode 16, the oxygen concentration in the tantalum carbide film 16a is set to 0 at. % Greater than 5%. %, And in the p-type gate electrode 18, the oxygen concentration in the tantalum carbide film 18a is 9 at. % Or more and 23 at. % Or less is preferable. As a result, the effective work function of the n-type gate electrode 16 of the n-type MIS transistor Qn becomes close to the conduction band of silicon, while the effective work function of the p-type gate electrode 18 of the p-type MIS transistor Qp is changed to the silicon load. It can be made near the electronic band. Thereby, the threshold value of the CMIS element can be reduced, and a CMIS element having a high on-current and low power consumption can be realized.

In the present embodiment, the tantalum carbide film 16a (first metal film) is thicker than the tantalum carbide film 18a (second metal film). As shown in the first embodiment, the oxygen concentration in the tantalum carbide film increases as the film thickness of tantalum carbide (TaC _x ) decreases from FIGS. 6 and 7, and the effective work function increases accordingly. Thus, the n-type gate electrode 16 and the p-type gate electrode 18 are configured such that the film thickness of the tantalum carbide film 16a (first metal film) is larger than the film thickness of the tantalum carbide film 18a (second metal film). is doing. Thus, by adjusting the film thickness of tantalum carbide, the n-type gate electrode 16 and the p-type gate electrode 18 can be configured, and the n-type MIS transistor Qn and the p-type using a single metal gate electrode material. A CMIS element can be formed by the MIS transistor Qp.

  Further, in order to make the effective work function of the n-type gate electrode 16 in the vicinity of the conduction band of silicon, the film thickness of the tantalum carbide film 16a to which oxygen is added is set to 7 nm to 18.4 nm. In order to make the work function near the valence band of silicon, the film thickness of the tantalum carbide film 18a to which oxygen is added is preferably set to 1 to 5.5 nm. Thereby, the threshold value of the CMIS element can be reduced, and a CMIS element having a high on-current and low power consumption can be realized.

Note that the manufacturing method of the semiconductor device in this embodiment mode can employ the same steps as the manufacturing method of the semiconductor device shown in Embodiment Mode 1. The difference is that the tantalum carbide film 16a of the n-type MIS transistor Qn has a predetermined film thickness (7 nm to 18 nm) when the metal gate electrode 3 is formed with reference to FIG. 3 shown in the first embodiment. 4 nm), and the tantalum carbide film 18a of the p-type MIS transistor Qp is deposited with a predetermined film thickness (1 to 5.5 nm). Thereafter, as described with reference to FIG. 5, oxygen may be added to the tantalum carbide film 16a and the tantalum carbide film 18a by low-temperature oxidation at 400 ° C. in a 20% O ₂ atmosphere.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the case where the TaC _x film is deposited by the room-temperature sputtering method has been described. However, the TaC _x film may be deposited by the CVD method, and thereafter, the TaC _x film is configured by adding oxygen. A metal gate electrode to be formed is formed. In the CVD method, since the TaC _x film is deposited at a high temperature, the number of steps for performing heat treatment using the amorphous silicon film as a protective film can be reduced.

In the above embodiment, TaC _x with oxygen added is used as the metal gate electrode. However, any one of TiC _x , ZrC _x , HfC _x , VC _x , NbC _x , MoC _x , and WC _x with oxygen added is used. It may be a metal film. In this case, the CMIS element can be configured by making the oxygen concentration in the metal film constituting the n-type gate electrode lower than the oxygen concentration in the metal film constituting the p-type gate electrode.

  The present invention is widely used in the manufacturing industry of semiconductor devices, in particular, semiconductor devices in which a CMIS element is composed of an n-type MISFET and a p-type MISFET using metal as a gate electrode material.

It is sectional drawing which shows typically the principal part of the semiconductor device in the manufacturing process in one embodiment of this invention. FIG. 2 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 1. FIG. 3 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 2. FIG. 4 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 3. FIG. 5 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 4. It is an explanatory view showing a relationship between oxygen concentration and the film thickness in the TaC _x film. It is an explanatory view showing a relationship between oxygen concentration and the effective work function in the TaC _x film. It is an explanatory view showing a relationship between the flat band voltage _{V FB} and the equivalent oxide thickness _{EOT HfO2} in oxygenated TaC _x electrode _/ HfO _{2 /} SiO 2 structure. FIG. 6 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 5. It is an illustration of _TaC x / HfO ₂ structure by X-ray diffraction pattern of oxygen added as a parameter in the TaC _x film. It is an explanatory view showing a relationship between oxygen concentration and the film thickness in the TaC _x film. It is an explanatory view of reliability due to NBTI of oxygenated TaC _x electrode. It is an explanatory view showing the relationship between the capacitance and the gate voltage of the n-type MIS transistor and the p-type MIS transistor of oxygenated TaC _x electrode. It is an explanatory view showing a relationship between oxygen concentration in the threshold voltage and TaC _x film of n-type MIS transistor and the p-type MIS transistor of TaC _x electrodes oxygenated. In MIS transistor using an oxygen TaC _x electrode by adding an explanatory view showing an electron mobility and hole mobility which is a parameter of oxygen concentration in the TaC _x film. It is sectional drawing which shows typically the principal part of the semiconductor device in other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 SOI substrate 1a Support substrate 1b Silicon oxide layer 1c Silicon layer 2 Gate insulating film 2a Silicon oxide film 2b Hafnium oxide film 3 Metal gate electrode 4 Silicon film 5 Diffusion layer 11 Silicon substrate 12 Element isolation region 13 P type well 14 N type well 15 Gate insulating film 15a Silicon oxide film 15b Hafnium oxide film 16 n-type gate electrode 16a Tantalum carbide film (first metal film)
16b Polysilicon film 17 n-type diffusion layer (source / drain)
18 p-type gate electrode 18a Tantalum carbide film (second metal film)
18b Polysilicon film 19 p-type diffusion layer (source / drain)
20 Contact hole 21 Plug 22 Metal wiring 23 Interlayer insulating film Qn n-type MIS transistor Qp p-type MIS transistor

Claims (10)

A method for manufacturing a semiconductor device comprising an n-channel MIS transistor and a p-channel MIS transistor on a main surface of a semiconductor substrate,
(A) forming a gate insulating film from the silicon side of the semiconductor substrate;
(B) forming a metal gate electrode on the gate insulating film;
(C) forming an amorphous silicon film on the metal gate electrode;
(D) after the step (c), heat-treating the metal gate electrode;
(E) after the step (d), removing the silicon film;
(F) After the step (e), adding oxygen to the metal gate electrode;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), the metal gate electrode formed of a metal carbide having conductivity is formed. In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), the metal gate electrode made of tantalum carbide is formed. In the manufacturing method of the semiconductor device according to claim 3,
In the step (f), the oxygen concentration in the tantalum carbide is set to 0 at. % Greater than 5%. % Or less, a method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 3,
In the step (f), the oxygen concentration in the tantalum carbide is set to 9 at. % Or more and 23 at. % Or less, a method for manufacturing a semiconductor device. A CMIS element composed of an n-channel MIS transistor and a p-channel MIS transistor is provided on the main surface of the semiconductor substrate,
Each of the gate insulating films of the n-channel MIS transistor and the p-channel MIS transistor includes an Hf—O-based insulating film made of Hf—O.
The n-type gate electrode of the n-channel MIS transistor includes a first metal film made of tantalum carbide to which oxygen is added on the Hf-O-based insulating film,
The p-type gate electrode of the p-channel MIS transistor includes a second metal film made of tantalum carbide to which oxygen is added on the Hf-O insulating film,
A semiconductor device, wherein an oxygen concentration in the first metal film is lower than an oxygen concentration in the second metal film. The semiconductor device according to claim 6.
The oxygen concentration in the first metal film is 0 at. % Greater than 5%. % Or less,
The oxygen concentration in the second metal film is 9 at. % Or more and 23 at. % Or less of a semiconductor device. The semiconductor device according to claim 6.
A semiconductor device, wherein the thickness of the first metal film is larger than the thickness of the second metal film. The semiconductor device according to claim 6.
The semiconductor device, wherein the gate insulating film includes a silicon oxide film provided between the semiconductor substrate and the Hf-O-based insulating film. The semiconductor device according to claim 6.
The semiconductor device, wherein the semiconductor substrate is an SOI substrate.