JP2008243994A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amorphous semiconductor device in which an La-Hf-O film eliminating a low dielectric layer in an interface with a semiconductor region is used as a gate insulating film, and to provide a manufacturing method thereof. <P>SOLUTION: In the semiconductor device, an La-Hf-O film added with Si in an amorphous state is used as a gate insulating film. The manufacturing method thereof is also provided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an amorphous insulating film gate containing silicon and a method for manufacturing the same.

Silicon super-integrated circuits mounted on electronic devices are one of the fundamental technologies that will support the advanced information society in the future. In order to increase the functionality of integrated circuits, it is essential to improve the performance of semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and CMOSFETs (Complementary MOSFETs). Up to now, the performance of devices has basically been performed in accordance with the proportional reduction rule. However, it has been recognized that the performance enhancement by further miniaturization in recent years is difficult to realize due to various physical limitations. ing. For example, it is considered that the conventional gate insulating film SiON cannot meet the demand for high performance by miniaturization. Therefore, introduction of a so-called High-k gate insulating film having a relative dielectric constant higher than that of SiON has been studied. As the high-k gate insulating film, materials such as HfO ₂ and HfSiON are practically used. However, these Hf-based materials inevitably form a structural transition layer at the interface with the silicon substrate.

  Since this structural transition layer has a lower relative dielectric constant than the high-k gate insulating film (hereinafter referred to as a low dielectric constant layer), it reduces the effective capacity of the gate insulating film, and improves the transistor performance. It becomes a cause to inhibit.

  As a method for reducing the interface low dielectric constant layer, a gate insulating film technique made of a La—Al—O film has been proposed (see Non-Patent Document 1). With this La—Al—O film, since a low dielectric constant layer does not appear at the interface with the Si substrate, it is considered that the gate insulating film capacity can be remarkably increased, and the transistor performance can be continuously improved.

  On the other hand, there is a gate insulating film technology made of La—Hf—O (see Non-Patent Documents 2, 3, and 4). In Non-Patent Document 2, as in Non-Patent Document 1, a structure without a low dielectric constant layer at the interface with the silicon substrate can be realized. However, this La—Hf—O film is crystalline. A crystalline gate insulating film is said to be difficult to ensure the operational instability and long-term reliability of a transistor due to generation of an electrically active trap caused by a grain boundary included in the crystalline gate insulating film. In addition, it is said that variations in transistor characteristics and the like due to fluctuations in crystal orientation become apparent. In Non-Patent Document 3, amorphous La-Hf-O is realized. This seemed to solve the crystalline problem, but on the other hand, a low dielectric constant layer was formed at the interface with the silicon substrate (Non-patent Document 4).

Since the La-Hf-O film system uses Hf as compared with the La-Al-O film, the technology of the high-k gate insulating film that has been developed so far (film formation, etching processing, etc.) Is a material system that can be diverted more easily. Therefore, it is desirable to realize an amorphous gate insulating film without a low dielectric constant layer in this material system. However, it is presumed that there was no technique for forming an amorphous La—Hf—O gate insulating film on a silicon substrate without a low dielectric constant layer.
M. Suzuki et al., "Ultra-thin (EOT = 3Å) and low leakage dielectrics of La-aluminate directly on Si substrate fabricated by high temperature deposition", 2004 IEDM, pp445-448 A.Dimoulas et al., "La2Hf2O7 High-k gate dielectric grown directly on Si (001) by molecular-beam epitaxy", Appl. Phys. Lett. 85, pp3205-3207 Yamamoto et al., "Increasing crystallization temperature and improving MOS characteristics in ternary oxides with high dielectric constant (Hf-La-O)," Proceedings of the 53rd Joint Conference on Applied Physics (Spring 2006), 25a-V-8, p853 Y. Yamamoto et al., "Vfb Modification by Thin La2O3 Insertion into HfO2 / SiO2 Interface", 2006 Int'l Workshop on Dielectric Thin Films for Future ULSI Devices, pp65-66

As described above, it is desirable to realize an amorphous gate insulating film without a low dielectric constant layer by using this La-Hf-O film.
However, a technique for realizing a structure which is a gate insulating film using a La—Hf—O film and is amorphous and does not have a low dielectric constant layer has not been proposed so far.
Therefore, the present invention provides a semiconductor device using a La—Hf—O film which is amorphous and has a low dielectric constant layer excluded from an interface with a semiconductor region as a gate insulating film, and a method for manufacturing the same. Objective.

  An embodiment according to the present invention is formed on and in contact with a semiconductor substrate, a source region and a drain region formed apart from the semiconductor substrate, and the semiconductor substrate between the source region and the drain region, La, An insulating film containing Hf, Si, and O and is amorphous, and a gate electrode formed on the insulating film.

  Furthermore, the present embodiment is formed on a semiconductor substrate having an n-type element formation region and a p-type element formation region that are electrically separated by an element isolation layer, and is formed apart from the p-type element formation region. formed on and in contact with the p-type element formation region between the n-type source region and the n-type drain region and the n-type source region and the n-type drain region, and includes La, Hf, Si, and O, and An n-type semiconductor element composed of an amorphous first insulating film and a first gate electrode formed on the first insulating film is separated from the n-type element formation region. A p-type source region and a p-type drain region that are formed, and an n-type element formation region between the p-type source region and the p-type drain region, and includes La, Hf, Si, and O. A second insulating film that is amorphous and the second insulating film To provide a semiconductor device including a p-type semiconductor element composed of a second gate electrode formed on the upper.

  In addition, the present embodiment includes a step of forming an insulating film that is in contact with a semiconductor substrate and includes La, Hf, Si, and O and is amorphous; a step of heat-treating the insulating film; and And a step of forming a gate electrode. A method for manufacturing a semiconductor device is provided.

  Further, in the present embodiment, a process of forming an insulating film that is in contact with a semiconductor substrate from which Si is exposed, contains La, Hf, and O, and is amorphous, and supplies Si to the insulating film by heat treatment. There is provided a method for manufacturing a semiconductor device, comprising: a step of forming a gate electrode on the insulating film.

  According to the present invention, a semiconductor device using a La—Hf—O film that is amorphous and has a low dielectric constant layer excluded from the interface with a semiconductor region as a gate insulating film, and a method for manufacturing the same are provided. Can do.

Embodiments according to the present invention will be described in detail with reference to the drawings.
The drawings used for the description of the following embodiments are schematic diagrams, and shapes, dimensions, ratios, and the like may differ from actual devices. However, these may be appropriately changed in consideration of the following description and known techniques. Is something that can be done.

First, an outline of the present embodiment will be described.
This embodiment employs a La-Hf-O-based gate insulating film (hereinafter referred to as a La-Hf-O film) to form an amorphous form, and to form a low dielectric constant layer at the interface with the semiconductor. This is a technology for realizing a semiconductor device having an excluded structure.

  First, it has been found that the amorphous structure of the insulating film is maintained by adding an appropriate amount of Si to the La—Hf—O film. A normal La—Hf—O film has a property of crystallizing at 750 ° C. However, the La—Hf—O film to which Si is added can maintain an amorphous state even at a high temperature of about 800 ° C. This is considered to be a result of the Si element in the added film inhibiting the nucleation / growth of the La—Hf—O crystal.

Fig. 1 shows the results of XRD (X-ray diffractometry) verification, in which crystals contained in a La-Hf-O film (thickness 4-5 nm thin film) containing about 2 atomic percent of Si are physically evaluated. is there. As shown in FIG. 1, when the heat treatment temperatures after deposition were 400 ° C. and 800 ° C., no diffraction peaks other than the Si substrate were observed. However, at 1000 ° C., a diffraction peak believed to be derived from La ₂ Hf ₂ O ₇ crystals was observed. From this, it can be seen that the La—Hf—O thin film originally crystallized at about 750 ° C. maintained an amorphous state even after annealing at 800 ° C. This seems to be an effect of Si contained in the film.

  In the above verification, a heat treatment was performed after depositing a La—Hf—O film on a Si substrate by a laser ablation method using a deposition target made of La, Hf, and O. It is presumed that Si in La—Hf—O is supplied from the Si substrate during this process. However, the effect of maintaining the La—Hf—O film in the present embodiment in an amorphous state is considered to be due to a mechanism in which the Si element inhibits nucleation / growth of the La—Hf—O crystal. Therefore, it can also be obtained by intentionally adding Si at the time of forming the La—Hf—O film.

If the amount of Si in the La—Hf—O film is 1% or more, the effect of suppressing crystallization as shown in FIG. 1 is exhibited. Even if the addition amount is large, the effect of suppressing crystallization can be maintained. However, if too much Si is added, the low relative dielectric constant of SiO ₂ with respect to the high relative dielectric constant (ε to 25) of the La—Hf—O film. The effect of the rate (ε˜4) begins to work. That is, the greater the amount of Si added, the lower the average relative dielectric constant of the film, thereby lowering the gate insulating film capacitance and hindering the increase in the operation speed of the transistor. When the Si addition amount is 10%, the average relative dielectric constant is about 23, and the reduction rate can be suppressed to about 10%. By suppressing the addition amount of Si to 10% or less, the gate insulating film capacity does not significantly decrease and does not hinder the transistor operation speed.

  Second, the appearance of the interface low dielectric constant layer can be completely eliminated by selecting the process conditions. The key process conditions are (1) the substrate temperature during the deposition of the La—Hf—O film, the oxygen partial pressure in the film forming apparatus, and (2) the heat treatment applied to the La—Hf—O film after deposition. Atmosphere and processing temperature.

The substrate temperature during deposition needs to be maintained at 800 ° C. or higher. If the film is formed at a high temperature of 800 ° C. or higher, the network structure of the film is highly complete, and diffusion of oxygen in the film and oxygen outside the film is difficult to occur. Accordingly, it is difficult to form an interface low dielectric constant layer in the heat treatment performed after deposition. In addition, when the oxygen partial pressure is high in the deposition chamber atmosphere during deposition, the surface of the semiconductor substrate is oxidized, so the oxygen partial pressure must be suppressed to 1 × 10 ⁻⁶ Pa or less.

  On the other hand, if the substrate temperature is lower than 800 ° C. during deposition, an incomplete portion remains in the atomic bond network structure in the film. As a result, in the post-deposition heat treatment described later, oxygen diffuses in or out of the film, the surface of the semiconductor substrate, for example, the silicon substrate is oxidized, and an interface low dielectric constant layer appears.

Another important process in eliminating the interfacial low-k layer is to heat-treat after La—Hf—O deposition. As described above, when the La—Hf—O film is deposited, the oxygen partial pressure is lowered so that the semiconductor surface is not easily oxidized. Therefore, the La—Hf—O film has a portion where oxygen is slightly deficient. In order to compensate for this, heat treatment is performed in an oxygen atmosphere after deposition.
The treatment temperature is desirably 200 ° C. or higher and 950 ° C. or lower. More preferably, it is performed within a range of 200 ° C. or more and 400 ° C. or less. If the treatment temperature is less than 200 ° C., the effect of supplementing oxygen that is slightly insufficient cannot be obtained, and if the treatment temperature is higher than 950 ° C., crystallization of the film occurs.

  Further, in the heat treatment step after the deposition, the semiconductor surface may be oxidized simultaneously with the supply of oxygen to the La—Hf—O film, and an interface low dielectric constant layer may be formed. Although deposition of a La—Hf—O film at a high temperature as in this embodiment makes it relatively difficult for oxygen movement in the film to occur, a finite amount of oxygen can reach the substrate under certain conditions. is there. In order to avoid this, the heat treatment after deposition should be performed at a low temperature. For example, when the temperature is 400 ° C. or lower, there is almost no possibility of formation of an interface low dielectric constant layer, and a high insulating film capacity can be maintained. Note that the heat treatment atmosphere of the heat treatment after deposition is required to contain at least oxygen. For example, an inert gas may be contained as a carrier gas.

FIG. 2 is a view showing a laminated structure of a La—Hf—O film formed in the range of process conditions defined in this embodiment and a Si substrate.
As the specified process conditions described in the present embodiment, for example, at a substrate temperature of 800 ° C. during deposition and a heat treatment temperature of 400 ° C. after deposition, a La—Hf—O film serving as a gate insulating film has a thickness L [4. 4 nm] is formed. FIG. 2 shows an observation result of the laminated structure of the La—Hf—O film and the Si substrate, which is observed at the atomic scale resolution by a cross-sectional TEM (Transmission electron microscopy) method. Incidentally, according to this film formation, approximately 2 atomic% of Si is present inside La—Hf—O.

  A normal low dielectric constant layer is observed as a white contrast layer in TEM observation. In TEM observation, more significant electron scattering occurs due to heavy atoms in the sample, and the electron beam incident on the position does not contribute to imaging, resulting in a black contrast. Here, since the normal low dielectric constant layer is mainly composed of Si, the electron beam is less likely to be scattered and the contrast becomes white as compared with the presence of heavy elements such as La and Hf. In the stacked structure shown in FIG. 2 according to the present embodiment, no white contrast layer can be found at the interface between the La—Hf—O film and the Si substrate. That is, it can be confirmed that if the La—Hf—O film is formed under the film forming conditions according to the present embodiment, the interface low dielectric constant layer does not appear. Further, from FIG. 2, it is confirmed that the La—Hf—O film according to the present embodiment is amorphous even after the above process.

In order to more strictly confirm the estimation based on the TEM experiment result that there is no low dielectric constant layer at the interface, a MOS capacitor was created by changing the physical film thickness of the La-Hf-O film, and its electrical FIG. 3 shows the relationship between the physical film thickness and EOT, which is obtained by measuring the capacitance value to obtain the SiO ₂ equivalent film thickness EOT (Equivalent oxide thickness). If this plot is extrapolated to zero physical film thickness, if an EOT offset is observed, it means that a finite amount of an interface low dielectric constant layer is formed. With this method, it is possible to confirm the existence of a low dielectric constant layer that is too thin to be observed with TEM. Extrapolating the experimental plot revealed that the line passed through the origin. This means that there is no structural transition layer at the interface between the La—Hf—O film and the Si substrate in this experiment.

  It has been found that maintaining the substrate temperature during deposition at 800 ° C. or higher has the effect of improving the interface characteristics between the La—Hf—O film and the semiconductor. FIG. 4a is a capacitance-voltage characteristic of the MOS capacitor of the La—Hf—O film formed with the deposition temperature set to 500 ° C. or 800 ° C. in FIG. 4b. For the MOS capacitor, an n-type silicon substrate and a molybdenum gate electrode were used. In this experiment, the heat treatment after the deposition of the La—Hf—O film is not performed. In the case of the MOS capacitor formed at 500 ° C., the capacitance showed an abnormal behavior with respect to the change of the gate voltage. This was caused by trapping of the injected charge from the molybdenum or Si substrate into the La-Hf-O film by trapping or by trapping the interface between the La-Hf-O film and the Si substrate and wrapping. It can be regarded as a result. On the other hand, under the 800 ° C. film forming conditions of this embodiment, a very simple capacitance-voltage characteristic was obtained, which suggests that the Si surface changes with depletion and accumulation according to the gate voltage. This suggests that the La-Hf-O film midway wrap and interface trap in the case of film formation at 500 ° C. are remarkably reduced.

Third, setting the La / Hf ratio is important. It was found that good properties as shown in FIGS. 1 to 4a and 4b can be obtained when the La / Hf ratio is near 1. This seems to be due to the fact that La ₂ Hf ₂ O ₇ in the La—Hf—O material system has a very stable composition ratio. That is, since it is close to the composition that exists stably as a compound, the traps in the film and the interface traps hardly occur, and it is presumed that the properties are extremely excellent even in an amorphous state. From this viewpoint, La / Hf = 1 is most desirable. The range of La / Hf ratio is preferably 0.9 to 1.1.

  In this embodiment, a La—Hf—O film containing a slight amount of Si is directly bonded to a semiconductor, for example, Si. In such a structure, the microscopic atomic structure of the insulating film / Si interface is directly reflected in the electrical characteristics. Specifically, when the La / Hf ratio is significantly deviated from 1, the defect density at the interface increases. In general, when the Al-based composition increases, defects having negative charges increase at the interface, and when the La-based composition increases, defects having positive charges increase at the interface. When these surplus charges are formed, the flat band voltage Vfb of the MOS structure greatly deviates from its ideal position, and it becomes difficult to set the threshold voltage Vth of the transistor to an appropriate value. In addition, surplus charge at the interface becomes a Coulomb scatterer, reducing the current amount of the transistor and lowering the switching speed. In order to avoid such a problem, it is necessary to keep the La / Hf ratio in the range of 0.9 to 1.1 and the surplus charges at the interface within the proper range.

Here, it is mentioned that the conventional manufacturing method cannot obtain the structure and effects according to the present embodiment.
First, when La—Hf—O is formed by the method of Non-Patent Document 2, the presence of silicon is not mentioned in the film, and a crystal of La ₂ Hf ₂ O ₇ is formed after deposition. The process of Non-Patent Document 2 has a film deposition temperature of 750 to 770 ° C., and this is presumed to contribute to the difference from the present embodiment. In Non-Patent Document 2, formation of a low dielectric constant layer is not recognized at the interface with the silicon substrate. However, the post-deposition heat treatment process for improving electrical characteristics, which is indispensable in this embodiment, is not implemented in Non-Patent Document 2.

  On the other hand, in Non-Patent Documents 3 and 4, the film formation temperature was room temperature. Strictly, Non-Patent Document 3 does not disclose the substrate temperature at the time of film formation, but Non-Patent Document 4 discloses more detailed conditions than the same research group. It is estimated that Based on our experimental results, when a La-Hf-O film is deposited at room temperature, oxygen diffuses in the film during the heat treatment after deposition due to imperfection of the network structure of the film. It is estimated that the surface of Si is reoxidized and a low dielectric constant layer is formed. In fact, in Non-Patent Document 4, an interface low dielectric constant layer having a thickness of 1 nm is formed.

Next, a CMOSFET will be described as an example of the semiconductor device according to the first embodiment. FIG. 5 shows a cross-sectional configuration of the CMOSFET in the gate length direction.
This CMOSFET is formed on the main surface side of a silicon substrate 1 by electrically separating a p-type well region 2 and an n-type well region 3 by an element isolation layer 4. The element isolation layer 4 is formed of, for example, SiO ₂ . An n-channel (hereinafter referred to as n-ch) MIS transistor is formed in the p-type well region 2, and a p-channel (hereinafter referred to as p-ch) MIS transistor is formed in the n-type well region 3. .

  As a configuration of the n-ch MIS transistor, an n-type extension layer 9 is formed on both sides of the p-type well region 2 at a distance to be a current path (channel region), and an n-type diffusion layer 10 is formed below them. Is done. Both ends of the n-type extension layer 9 are applied to form a gate insulating film 5 on the current path. A gate electrode 6 is stacked on the gate insulating film 5, and gate sidewalls 8 are formed on both sides of the gate insulating film 5 and the gate electrode 6, respectively.

  These n-type diffusion layers 10 are configured so that the junction depth with the p-type well region 2 is deeper than that of the n-type extension layer 9, and the n-type diffusion layer 10 and the n-type extension layer 9 are n-ch MIS transistors. Source / drain regions. Here, the source / drain region may be a region where a semiconductor is doped at a high concentration, or may be a metal silicide.

  Similarly, in the p-ch MIS transistor, a p-type extension layer 19 is formed on both sides of the n-type well region 3 at a distance to be a current path (channel region), and a p-type diffusion layer 20 is formed below them. Is done. Both ends of the p-type extension layer 19 are engaged, and the gate insulating film 15 is formed on the current path. A gate electrode 16 is stacked on the gate insulating film 15, and gate sidewalls 18 are formed on both sides of the gate insulating film 15 and the gate electrode 16, respectively.

  These p-type diffusion layers 20 are configured such that the junction depth with the n-type well region 3 is deeper than that of the p-type extension layer 19, and the p-type diffusion layer 20 and the p-type extension layer 19 are p-type MIS transistors. Source / drain regions. The n-channel MIS transistor and the p-ch MIS transistor are covered with an interlayer insulating film 24.

  In the first embodiment, the gate insulating films 5 and 15 are the La—Hf—O films to which Si is added, and are in an amorphous state. The gate insulating film 5 and the p-type well region 2 and the gate insulating film 15 and the n-type well region 3 are in direct contact.

Next, a method for manufacturing the semiconductor device CMOSFET in the first embodiment will be described with reference to FIGS.
As shown in FIG. 6, the element isolation layer 4 is formed on the silicon substrate 1. The element isolation layer 4 may use a local oxidation method, an STI (Shallow Trench Isolation) method, or a mesa type. After the element isolation layer 4 is formed, the p-type well region 2 and the n-type well region 3 are respectively formed by normal ion implantation.

Next, La—Hf—O with Si added as a gate insulating film is formed on the surface of the silicon substrate 1. Here, as an example, the laser ablation method described above was used. First, the natural oxide film on the surface of the silicon substrate including the element isolation layer 4 and the well regions 2 and 3 was removed by normal wet etching, and then immediately loaded into the film forming apparatus. In this example, the composition ratio is adjusted to La ₂ Hf ₂ O ₇ and a very small amount of Si is used.

This target was irradiated with a KrF excimer laser (λ = 248 nm) to form a laser ablation film on the silicon substrate 1. The substrate temperature during the film formation was maintained at 800 ° C., and the oxygen partial pressure in the process gas atmosphere was maintained at 1 × 10 ⁻⁶ Pa or less. The formation of the gate insulating film is not limited to laser ablation, and other methods such as molecular beam epitaxy and sputtering may be used. However, since the laser ablation method has a characteristic that the composition of the target becomes as close as possible to the composition of the deposited thin film, it is preferable as the manufacturing method of the present embodiment where composition control is the key.

Next, heat treatment for the purpose of improving the quality of the deposited gate insulating film 5 (15) is performed. As an example, heat treatment was performed, for example, at 400 ° C. for 30 minutes in a nitrogen atmosphere to which oxygen was slightly added. It is essential that the atmosphere contains oxygen. The oxygen may be molecular oxygen, atomic oxygen, excited state oxygen, N ₂ O, NO, ozone, or the like, and is not particularly limited. The temperature is preferably 200 ° C. or more and 950 ° C. or less, more preferably 400 ° C. or less.

  This is because, as shown in FIG. 7, when the temperature is from 0 ° C. to 400 ° C., the insulation film capacity is not significantly reduced by the heat treatment after deposition. The decrease in the insulating film capacitance is a cause of reducing the current amount of the transistor and causing a reduction in switching speed.

  Here, Si in the La—Hf—O film may have a profile, and the concentration is preferably higher on the gate electrode side than the central region. By increasing the Si concentration, the reactivity of the interface between the insulating film and the gate electrode is lowered, and stable characteristics can be expected even after a high temperature process. This is an effect obtained by mixing Si having relatively low reactivity with La, Hf, etc. having high chemical reactivity.

  Further, it is desirable that the Si concentration of the La—Hf—O film is higher on the side of the bonding surface with the silicon substrate 1 than in the central region. The bond between La, Hf and oxygen is a highly ionic bond, and itself has a polarization, so that it becomes a source for scattering electrons, holes, etc. that move through the channel of the transistor. As a result, the driving current of the transistor is lowered, and the switching speed may be lowered. This is because an increase in Si concentration on the Si substrate side is expected to reduce the number of scatterers due to La and Hf ion polarization and improve the transistor speed. However, if Si exceeding 10% is added, the relative dielectric constant is remarkably reduced, and the merit of thinning scaling for direct bonding as shown in FIG. 3 is lost.

  FIG. 8 is an element profile analysis result by Rutherford backscattering of a La—Hf—O (Si addition) / Si laminated structure, in which the concentration increases on the Si substrate side and the gate electrode side of the La—Hf—O film. It shows that the Si profile can actually be created. This profile can be realized by simultaneously depositing, for example, a La—Hf—O target and a Si target in a so-called multi-target type film forming apparatus. The power applied to each target is adjusted, and in the initial stage of film formation, the power of the Si target is increased so as to add a larger amount of Si, and a La—Hf—O film containing a relatively large amount of Si is formed. The Si concentration on the Si substrate side and the gate electrode side can be set high by setting the power of the target weak and lowering the Si concentration in the film, and then increasing the power of the Si target again to form the film.

  From the profile shown in FIG. 8, it can also be seen that the ratio of La to Hf is approximately 1: 1 in most regions of the La—Hf—O film. This is a feature of the laser ablation method in which the composition of the target itself is easily reflected in the composition of the deposited film, and also shows that the addition of Si hardly affects the La / Hf ratio of the La—Hf—O film. ing.

  Thereafter, a single-layer or multilayer conductive film to be a gate electrode is formed over the La—Hf—O film by using an existing film formation technique. Here, as an example, a tantalum carbide film for an n-channel MIS transistor and a tungsten film for a p-ch MIS transistor are formed to a thickness of 10 nm by CVD, and a titanium nitride film is formed to a thickness of 10 nm by CVD. A silicon layer was deposited to 50 nm by low pressure CVD.

  For the n-channel MIS transistor, tantalum silicide, tantalum nitride silicide, titanium nitride silicide, tungsten silicide, tungsten nitride silicide, or the like can be used. For p-ch MIS transistors, ruthenium, titanium nitride, titanium aluminum nitride, platinum, platinum iridium, or the like can be used. In addition, the high Si concentration of the La—Hf—O film in the vicinity of the gate electrode interface leads to suppression of the interface reaction with these gate electrodes.

  Subsequently, patterning is performed by photolithography, unnecessary films are removed by anisotropic etching, and gate electrodes 6 and 16 are formed, respectively. Further, shallow extension layers 9 and 19 of high impurity concentration of n-type and p-type MIS transistors are formed by ion implantation of phosphorus and boron in a self-aligning manner using the gate electrode. The extension layers 9 and 19 may be formed using an elevated source / drain structure that can suppress the short channel effect as a device characteristic by using a selective epitaxial growth method. Further, impurities may be introduced simultaneously with the formation of the elevated source / drain structure.

  Next, sidewalls 8 and 18 for insulating the gate electrode and the source / drain regions are formed. The deep diffusion layers 10 and 20 are formed by ion implantation of phosphorus and boron with a larger acceleration voltage than before. In the steps so far, the activation process temperature of the source / drain is a temperature at which the gate insulating films 5 and 15 are not crystallized, for example, 900 ° C.

  As the activation process conditions for the source / drain, flash lamp annealing, laser annealing, or the like can be used. According to these, since the activation of impurities in the semiconductor can be realized in a shorter time, it becomes easy to maintain the heat resistance of the gate electrode / insulating film / semiconductor structure.

Thereafter, a silicon oxide film to be the interlayer insulating film 7 is deposited by low pressure CVD, the upper end of the gate electrode is exposed by CMP (chemical mechanical planarization), and then a nickel layer is formed to a thickness of 50 nm by sputtering or the like. Thereafter, by performing a low-temperature heat treatment at 500 ° C., silicide is formed from the interface region between nickel and polycrystalline Si to form Ni ₂ Si. Here, in this embodiment, all the polycrystalline Si is converted into silicide. Of course, a part of the polycrystalline Si may be silicidized by making the Ni film thinner. Thereafter, unreacted Ni is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution.

  Through the manufacturing process described above, the CMOSFET semiconductor device having the structure shown in FIG. 5 is produced. In the structure of the semiconductor device of this embodiment, the gate insulating film 5 and the p-type well region 2 and the gate insulating film 15 and the n-type well region 3 are in direct contact without interposing a low interface dielectric layer. For this reason, it is possible to set the insulating film capacitance to an extremely high value, and the current driving capability of the transistor is increased. Further, since the gate insulating films 5 and 15 are amorphous, there are few electrically active defects in the film, and the operation of the transistor is stabilized and the reliability is increased. In addition, since it is amorphous, fluctuations in characteristics such as variations in threshold voltage between transistor elements are small.

Next, a modification of the first embodiment will be described.
In the first embodiment described above, the source / drain regions are formed by introducing impurities after the gate insulating film and the gate electrode are processed. Even if a different manufacturing process (manufacturing method) is employed, the semiconductor device having the structure shown in FIG. 5 can be produced.

  This is a method of creating a transistor by a so-called replacement gate. Source / drain regions are formed in a self-aligned manner using a dummy gate made of polycrystalline silicon or the like. At this time, the source / drain regions are formed at a high temperature of 1000 ° C. or higher. Thereafter, the dummy gate is removed by an existing manufacturing method such as wet etching or dry etching to produce a structure as shown in FIG.

  Here, a gate insulating film and a gate electrode are formed again inside the trench 21 as in the first embodiment. For example, a film of La—Hf—O with a slight addition of Si is formed by a method with good step coverage such as a chemical vapor deposition method or an atomic layer deposition method. Of course, the above-described method such as laser ablation may be used. Furthermore, the structure shown in FIG. 10 is obtained by performing post-deposition heat treatment similar to that of the first embodiment described above.

  Subsequently, as shown in FIG. 11, an n-ch MIS transistor gate electrode 6a, for example, hafnium silicide to which nitrogen is added is formed in the n-ch MIS transistor. In addition, a p-ch MIS transistor gate electrode 16a, for example, nickel-rich nickel silicide is formed as a gate electrode in the p-ch MIS transistor.

  In addition, the gate electrode of the n-ch MIS transistor has a rare earth metal silicide (hafnium silicide, erbium, yttrium, etc.), a metal silicide (titanium silicide, zirconium, tantalum, etc.), and a nitridation obtained by adding nitrogen to the metal silicide. Metal silicide, tantalum carbide / tantalum nitride, and alloys obtained by adding a rare earth metal such as erbium to these can be used.

  The gate electrode of the p-ch MIS transistor has platinum group elements (platinum, iridium, ruthenium, palladium, osmium, etc.), alloys or silicides of platinum group elements, oxides of ruthenium and iridium, SrRuO, gold and silver. Aluminum aluminum nitride, tungsten and nitride thereof, molybdenum and nitride or oxide thereof can be used.

  Furthermore, a metal thin film such as tungsten is deposited on the entire surface of the structure shown in FIG. Thereafter, device planarization is performed by CMP or the like, whereby the semiconductor device having the structure shown in FIG. 5 can be obtained.

In this modification, there is no high-temperature process for forming a transistor that reaches 1000 ° C. after deposition of the gate insulating film and the gate electrode, so that there is less concern about the thermal stability of both structures. When a 900 ° C. heat treatment step is required as in the first embodiment, the probability of occurrence of a defect may be increased particularly due to the stability of the gate electrode / gate insulating film interface. In this modification, only a thermal process of 500 ° C. or less is required after the formation of the gate electrode / gate insulating film interface. Accordingly, a metal material that can withstand about 500 ° C., for example, nitrogen-added hafnium silicide, nickel-rich nickel silicide, or the like can be used in the modification. Since these materials have a work function close to the silicon band edge, the threshold voltage of the transistor can be lowered. With this modification, it is possible to use these low threshold gate electrode materials without fear of a fundamental heat resistance failure. As described above, according to the present embodiment, the material has a large current driving force. A semiconductor device with little leakage current and a manufacturing method thereof can be provided.

As mentioned above, although embodiment of this invention was described, this invention is not limited to these, In the category of the summary of the invention as described in a claim, it can change variously. In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage. Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiment as necessary.

It is a figure which shows the evaluation result of XRD which investigated the crystallization behavior of the La-Hf-O film | membrane of embodiment which concerns on this invention. It is a figure which shows the example of the cross section TEM which investigated the presence or absence of the interface low dielectric constant layer of the La-Hf-O film | membrane of this embodiment, and a silicon substrate. Is a diagram illustrating an example of the embodiment of the La-Hf-O film and the physical thickness and SiO ₂ equivalent thickness relationship was examined whether the surface a low dielectric constant layer of the silicon substrate. FIG. 4 a is a diagram showing the relationship between the capacitance and voltage of the MOS capacitor of the La—Hf—O film formed at a deposition temperature of 500 ° C. in this embodiment. FIG. 4 b is a diagram showing the relationship between the capacitance and voltage of the MOS capacitor of the La—Hf—O film formed at a deposition temperature of 800 ° C. in this embodiment. It is a figure which shows the cross-sectional structure of CMOSFET by 1st Embodiment. It is a figure for demonstrating the manufacturing process of CMOSFET by 1st Embodiment. It is an example showing the SiO ₂ equivalent thickness change with respect to the heat treatment temperature after the insulating film is deposited in the first embodiment. It is a figure which shows an example of the result of the Rutherford backscattering method which investigated Si distribution inside La-Hf-O. It is a figure for demonstrating the manufacturing process of CMOSFET by the modification of 1st Embodiment. It is a figure for demonstrating the manufacturing process of CMOSFET by the modification of 1st Embodiment. It is a figure for demonstrating the manufacturing process of CMOSFET by the modification of 1st Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... p-type well region, 3 ... n-type well region, 4 ... Element isolation layer, 5, 15 ... Si addition La-Hf-O film (gate insulating layer), 6, 16 ... Gate electrode, 6a ... gate electrode for n-ch MIS transistor, 7 ... interlayer insulating film, 8, 18 ... gate sidewall, 9, 19 ... extension layer, 10 ... diffusion layer, 16a ... gate electrode for p-ch MIS transistor, 20 ... diffusion layer, 21 ... Groove.

Claims (15)

A semiconductor substrate;
A source region and a drain region formed separately from the semiconductor substrate;
An insulating film formed on and in contact with the semiconductor substrate between the source region and the drain region, and including La, Hf, Si, O, and amorphous;
A gate electrode formed on the insulating film;
A semiconductor device comprising: The La / Hf ratio in the insulating film is 0.9 or more and 1.1 or less,
2. The semiconductor device according to claim 1, wherein the Si concentration in the insulating film is not less than 1 atomic% and not more than 10 atomic%.   2. The semiconductor device according to claim 1, wherein in the thickness direction of the insulating film, the concentration of the Si is higher on the semiconductor substrate side than on the central region.   2. The semiconductor device according to claim 1, wherein in the thickness direction of the insulating film, the concentration of Si is higher on the gate electrode side than on a central region. Formed on a semiconductor substrate having an n-type element formation region and a p-type element formation region electrically separated by an element isolation layer;
In contact with the p-type element formation region between the n-type source region and the n-type drain region formed separately in the p-type element formation region, and the n-type source region and the n-type drain region An n-type semiconductor formed of a first insulating film that is formed and contains La, Hf, Si, and O and is amorphous, and a first gate electrode formed on the first insulating film Elements,
Formed in contact with the n-type element formation region between the p-type source region and the p-type drain region and the p-type source region and the p-type drain region formed separately in the n-type element formation region. A p-type semiconductor element comprising: a second insulating film that includes La, Hf, Si, and O and is amorphous; and a second gate electrode formed on the second insulating film. A semiconductor device comprising: The La / Hf ratio in each of the first insulating film and the second insulating film is 0.9 or more and 1.1 or less,
6. The semiconductor device according to claim 5, wherein a concentration of the Si in each of the first insulating film and the second insulating film is 1 atomic% or more and 10 atomic% or less.   6. The semiconductor according to claim 5, wherein in the thickness direction of each of the first insulating film and the second insulating film, the concentration of Si is higher on the semiconductor substrate side than on the central region. apparatus.   6. The semiconductor according to claim 5, wherein in the thickness direction of each of the first insulating film and the second insulating film, the Si concentration is higher on the gate electrode side than on the central region. apparatus. Forming an insulating film in contact with the semiconductor substrate, including La, Hf, Si, and O, and amorphous;
Heat-treating the insulating film;
Forming a gate electrode on the insulating film;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 9, further comprising a step of removing a natural oxide film on the semiconductor substrate before the step of forming the insulating film. A step of forming an insulating film in contact with a semiconductor substrate to which Si is exposed, including La, Hf, and O, and being amorphous;
Supplying the Si into the insulating film by heat treatment;
Forming a gate electrode on the insulating film;
A method for manufacturing a semiconductor device, comprising: In the step of forming the insulating film,
The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor substrate has a temperature of 800 ° C. or higher and lower than 950 ° C. In the step of forming the insulating film,
12. The method of manufacturing a semiconductor device according to claim 9, wherein an oxygen partial pressure in the atmosphere is 1 × 10 ⁻⁶ Pa or less. In the step of forming the insulating film,
12. The method of manufacturing a semiconductor device according to claim 9, wherein the insulating film is formed by a laser ablation method. In the step of supplying Si into the insulating film,
12. The method of manufacturing a semiconductor device according to claim 9, wherein the temperature of the semiconductor substrate is 200 ° C. or higher and 400 ° C. or lower, and the atmosphere thereof contains oxygen.

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